{"block":{"name":"edn","variant":"edn0","commit":"1521b5f2d5d90c126b1cbab588514f5ecff12f40","commit_short":"1521b5f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40","revision_info":"GitHub Revision: [`1521b5f`](https://github.com/lowrisc/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-01T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn0/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.26,"sim_time":38.929165,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":0.82,"sim_time":16.95573,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":0.93,"sim_time":95.743146,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":4.36,"sim_time":1524.3314480000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":1.3,"sim_time":188.837284,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":1.35,"sim_time":62.615497000000005,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":0.93,"sim_time":95.743146,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.3,"sim_time":188.837284,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":6.85,"sim_time":1253.332298,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":6.85,"sim_time":1253.332298,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"genbits":{"tests":{"edn_genbits":{"max_time":6.85,"sim_time":1253.332298,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.49,"sim_time":22.272133,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alerts":{"tests":{"edn_alert":{"max_time":1.63,"sim_time":40.800266,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"errs":{"tests":{"edn_err":{"max_time":1.56,"sim_time":95.462236,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"disable":{"tests":{"edn_disable":{"max_time":1.27,"sim_time":13.790790999999999,"passed":50,"total":50,"percent":100.0},"edn_disable_auto_req_mode":{"max_time":14.31,"sim_time":500.0,"passed":40,"total":50,"percent":80.0}},"passed":90,"total":100,"percent":90.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":4.83,"sim_time":319.65609600000005,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":0.92,"sim_time":19.314503000000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":1.37,"sim_time":82.602785,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":2.93,"sim_time":446.406042,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":2.93,"sim_time":446.406042,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.82,"sim_time":16.95573,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.93,"sim_time":95.743146,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.3,"sim_time":188.837284,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.24,"sim_time":55.989050000000006,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.82,"sim_time":16.95573,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.93,"sim_time":95.743146,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.3,"sim_time":188.837284,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.24,"sim_time":55.989050000000006,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":960,"total":970,"percent":98.96907216494846},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_tl_intg_err":{"max_time":2.33,"sim_time":133.59132699999998,"passed":20,"total":20,"percent":100.0},"edn_sec_cm":{"max_time":6.5,"sim_time":717.681807,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_config_regwen":{"tests":{"edn_regwen":{"max_time":0.92,"sim_time":23.622676,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.63,"sim_time":40.800266,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":6.5,"sim_time":717.681807,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":6.5,"sim_time":717.681807,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":6.5,"sim_time":717.681807,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":6.5,"sim_time":717.681807,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.63,"sim_time":40.800266,"passed":200,"total":200,"percent":100.0},"edn_sec_cm":{"max_time":6.5,"sim_time":717.681807,"passed":5,"total":5,"percent":100.0}},"passed":205,"total":205,"percent":100.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.63,"sim_time":40.800266,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":2.33,"sim_time":133.59132699999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":235,"total":235,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":93.02,"sim_time":33440.288456999995,"passed":41,"total":50,"percent":82.0}},"passed":41,"total":50,"percent":82.0}},"passed":41,"total":50,"percent":82.0}},"coverage":{"code":{"block":null,"line_statement":98.91,"branch":96.51,"condition_expression":94.2,"toggle":97.12,"fsm":91.94},"assertion":97.61,"functional":92.86},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"0.edn_disable_auto_req_mode.98848775749551585176762466090514057839784613268982746315588240828444003425811","seed":98848775749551585176762466090514057839784613268982746315588240828444003425811,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @   9387096 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0061b6c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @   9387096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"1.edn_disable_auto_req_mode.43172677117462556636216798484481673376448971371497751896593387023531108559186","seed":43172677117462556636216798484481673376448971371497751896593387023531108559186,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/1.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  14636885 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00c0a9c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  14636885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"9.edn_disable_auto_req_mode.100322590801784414717064250678594470025434099049117180837689372015446306145356","seed":100322590801784414717064250678594470025434099049117180837689372015446306145356,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  33515735 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000962 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  33515735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"22.edn_disable_auto_req_mode.112920729232551749793025208835458886746478391289123986009775343336230077746495","seed":112920729232551749793025208835458886746478391289123986009775343336230077746495,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/22.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  38027208 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000692 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  38027208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"30.edn_disable_auto_req_mode.111123971336079037181501036470498779866015814606492517933894775042589510826803","seed":111123971336079037181501036470498779866015814606492517933894775042589510826803,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/30.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  72790449 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001963 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  72790449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"38.edn_disable_auto_req_mode.98748122525597803801398656770347613685387410647838577194102675798912298699724","seed":98748122525597803801398656770347613685387410647838577194102675798912298699724,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/38.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  18575316 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  18575316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"41.edn_disable_auto_req_mode.3364515163882807616665641019078905058099217072321937426291039043523833904249","seed":3364515163882807616665641019078905058099217072321937426291039043523833904249,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/41.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  12680093 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000692 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  12680093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"12.edn_stress_all_with_rand_reset.55337725200735336751314556023681187014498184464355992202134663999621761168024","seed":55337725200735336751314556023681187014498184464355992202134663999621761168024,"line":205,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/12.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1447050598 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1447050598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"23.edn_stress_all_with_rand_reset.47496554136672705020025640065846606501994645160562130107883034197413314007001","seed":47496554136672705020025640065846606501994645160562130107883034197413314007001,"line":208,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/23.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 944186048 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 944186048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"36.edn_stress_all_with_rand_reset.100032855687998632575048830065486515812761822640180632143896994862537183936537","seed":100032855687998632575048830065486515812761822640180632143896994862537183936537,"line":241,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2662134331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2662134331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"42.edn_stress_all_with_rand_reset.15049149310810108548024888767147056466114759604607517600891167098486996792134","seed":15049149310810108548024888767147056466114759604607517600891167098486996792134,"line":138,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/42.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1059632346 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1059632346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"43.edn_stress_all_with_rand_reset.19074043668821816925466490225012863798674289469933550951939079788061463784509","seed":19074043668821816925466490225012863798674289469933550951939079788061463784509,"line":319,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2480080479 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2480080479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"46.edn_stress_all_with_rand_reset.93689424347836655488713412719592943325009148868908727112545892312926520512203","seed":93689424347836655488713412719592943325009148868908727112545892312926520512203,"line":180,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/46.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 922610374 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 922610374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"47.edn_stress_all_with_rand_reset.113648226209984067876481324707308480837552369753443497365356016684265859306531","seed":113648226209984067876481324707308480837552369753443497365356016684265859306531,"line":316,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/47.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3159663225 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3159663225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"14.edn_disable_auto_req_mode.110254483262120206703243684684555249911403978177794958851718980488879173561139","seed":110254483262120206703243684684555249911403978177794958851718980488879173561139,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"27.edn_disable_auto_req_mode.98098615845979297703453853348689567269539621834064318377545954332180248848731","seed":98098615845979297703453853348689567269539621834064318377545954332180248848731,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/27.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.95644532467541802781223734724916206825893174238580130767258928565720556673847","seed":95644532467541802781223734724916206825893174238580130767258928565720556673847,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[FCIBH] Illegal bin hit":[{"name":"edn_stress_all_with_rand_reset","qual_name":"31.edn_stress_all_with_rand_reset.102134377802090444045881252842396711845832251105351741456592096112870556602404","seed":102134377802090444045881252842396711845832251105351741456592096112870556602404,"line":218,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 666247198 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"37.edn_stress_all_with_rand_reset.2304634620701560541397839537617925881421134655645839743231399391885904594204","seed":2304634620701560541397839537617925881421134655645839743231399391885904594204,"line":199,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/37.edn_stress_all_with_rand_reset/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1888546007 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]}]}},"passed":1111,"total":1130,"percent":98.31858407079646}