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accesses.":[{"name":"kmac_stress_all_with_rand_reset","qual_name":"1.kmac_stress_all_with_rand_reset.44849213166391249112972278730476404805014228472618839212933856122322901948835","seed":44849213166391249112972278730476404805014228472618839212933856122322901948835,"line":100,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16500215056 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16500215056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_stress_all_with_rand_reset","qual_name":"3.kmac_stress_all_with_rand_reset.104294585367575391199796994791315861679030526163392964268514077850696066076095","seed":104294585367575391199796994791315861679030526163392964268514077850696066076095,"line":197,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4242439319 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4242439319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_stress_all_with_rand_reset","qual_name":"9.kmac_stress_all_with_rand_reset.3765980148714054800024653132755907796869209197153509544089822663894815369756","seed":3765980148714054800024653132755907796869209197153509544089822663894815369756,"line":94,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7740362703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7740362703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)":[{"name":"kmac_sideload_invalid","qual_name":"8.kmac_sideload_invalid.49674057750532735793839315920519544732206397448523508127297621557581077505657","seed":49674057750532735793839315920519544732206397448523508127297621557581077505657,"line":79,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10048324290 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x20b29000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)\n","UVM_INFO @ 10048324290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"kmac_sideload_invalid","qual_name":"10.kmac_sideload_invalid.84177189581476511508538799886593124985578690075778104641962482290099024646245","seed":84177189581476511508538799886593124985578690075778104641962482290099024646245,"line":84,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10073824499 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbe5fc000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)\n","UVM_INFO @ 10073824499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)":[{"name":"kmac_sideload_invalid","qual_name":"16.kmac_sideload_invalid.50114692303500338712619489733991427593188036169665634969991367362328324567612","seed":50114692303500338712619489733991427593188036169665634969991367362328324567612,"line":89,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10254644518 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8269d000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)\n","UVM_INFO @ 10254644518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!":[{"name":"kmac_key_error","qual_name":"16.kmac_key_error.108907143361653287309453516023263271955793176543315404092740207840635232356934","seed":108907143361653287309453516023263271955793176543315404092740207840635232356934,"line":105,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/16.kmac_key_error/latest/run.log","log_context":["UVM_ERROR @ 2166617877 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set! \n","UVM_INFO @ 2166617877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)":[{"name":"kmac_sideload_invalid","qual_name":"18.kmac_sideload_invalid.82989946020330507410594685260987952558352061277282183763115401087966579541828","seed":82989946020330507410594685260987952558352061277282183763115401087966579541828,"line":88,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10179161031 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4a095000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)\n","UVM_INFO @ 10179161031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24)":[{"name":"kmac_sideload_invalid","qual_name":"21.kmac_sideload_invalid.15860710150310899593090915369622770753570304330771746440036426401835200674461","seed":15860710150310899593090915369622770753570304330771746440036426401835200674461,"line":104,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10111765047 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x81805000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)\n","UVM_INFO @ 10111765047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)":[{"name":"kmac_sideload_invalid","qual_name":"22.kmac_sideload_invalid.27511913133218930497479311258639774869371539245976794155084335900480348222954","seed":27511913133218930497479311258639774869371539245976794155084335900480348222954,"line":90,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10089241405 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3f9ce000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)\n","UVM_INFO @ 10089241405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)":[{"name":"kmac_sideload_invalid","qual_name":"23.kmac_sideload_invalid.96359324503308291526935464946026506779798463193574388846609734409716553512747","seed":96359324503308291526935464946026506779798463193574388846609734409716553512747,"line":100,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10333829250 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x34cc7000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)\n","UVM_INFO @ 10333829250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"kmac_sideload_invalid","qual_name":"28.kmac_sideload_invalid.39750676183025334545401236748405432793740880797516426375241245575909022200966","seed":39750676183025334545401236748405432793740880797516426375241245575909022200966,"line":86,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10224250466 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x85571000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)\n","UVM_INFO @ 10224250466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)":[{"name":"kmac_sideload_invalid","qual_name":"29.kmac_sideload_invalid.83653237182679295098131555777074527988394586983749250568994212178493506604432","seed":83653237182679295098131555777074527988394586983749250568994212178493506604432,"line":94,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10324726540 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9d94000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)\n","UVM_INFO @ 10324726540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"kmac_sideload_invalid","qual_name":"30.kmac_sideload_invalid.4135294361445058669044943940309134904554098529142399816413171247181282661966","seed":4135294361445058669044943940309134904554098529142399816413171247181282661966,"line":84,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10079179562 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd8db9000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)\n","UVM_INFO @ 10079179562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)":[{"name":"kmac_sideload_invalid","qual_name":"43.kmac_sideload_invalid.81899698386110102188084731679365738789987851481741295733507556617623134047863","seed":81899698386110102188084731679365738789987851481741295733507556617623134047863,"line":78,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10016276532 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe0c00000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)\n","UVM_INFO @ 10016276532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"kmac_error","qual_name":"46.kmac_error.73439255360494632971131516043778085890473419844553516285206350605694305633332","seed":73439255360494632971131516043778085890473419844553516285206350605694305633332,"line":182,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/46.kmac_error/latest/run.log","log_context":["UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":923,"total":940,"percent":98.19148936170212}