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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.33209137433487167451979934685781245401518250678599656361975369207788054009193","seed":33209137433487167451979934685781245401518250678599656361975369207788054009193,"line":11345,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11335678628 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 11335678628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding 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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.21735879262887029889595763042206298913330283505990880156469660344758036364300","seed":21735879262887029889595763042206298913330283505990880156469660344758036364300,"line":7256,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3979971548 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3979971548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"3.lc_ctrl_stress_all_with_rand_reset.26772431878694428661067424342558207517173328297762296350832164518851737039424","seed":26772431878694428661067424342558207517173328297762296350832164518851737039424,"line":1337,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1126747737 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1126747737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"4.lc_ctrl_stress_all_with_rand_reset.10512030743194756928198056692082108972440984881537321248810757997162901302721","seed":10512030743194756928198056692082108972440984881537321248810757997162901302721,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 599909988 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 599909988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.44598918315409122309972939730612149386388473291397982028038540061151443885864","seed":44598918315409122309972939730612149386388473291397982028038540061151443885864,"line":7830,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2376382625 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2376382625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.21903988631341162822107122941116167869522426803862228569540298470847027134163","seed":21903988631341162822107122941116167869522426803862228569540298470847027134163,"line":3116,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1209834900 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1209834900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"10.lc_ctrl_stress_all_with_rand_reset.5110024548402257850962615966451557958477021276657409158497946575020147842829","seed":5110024548402257850962615966451557958477021276657409158497946575020147842829,"line":194,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 409721510 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 409721510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.104772383765342466991148137088156172925840518175216179158785767643274065084537","seed":104772383765342466991148137088156172925840518175216179158785767643274065084537,"line":2214,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1157045114 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1157045114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.89486236519623193826546140888331958401102525055316864780050083593611291869046","seed":89486236519623193826546140888331958401102525055316864780050083593611291869046,"line":1966,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14576608885 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 14576608885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.71162183151891094081744792581008207760437755742675360212124437030704359241398","seed":71162183151891094081744792581008207760437755742675360212124437030704359241398,"line":7287,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 31076473755 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 31076473755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"19.lc_ctrl_stress_all_with_rand_reset.49798741034149837484289479763568340332675046017266345274994106696262831082656","seed":49798741034149837484289479763568340332675046017266345274994106696262831082656,"line":8175,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9186153705 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 9186153705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.109238880867822618699604673003666171163382449836385549207374122720001240172964","seed":109238880867822618699604673003666171163382449836385549207374122720001240172964,"line":5799,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2091852165 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2091852165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.29895537918667203856593769915929891259765133431133080574997163780566488338154","seed":29895537918667203856593769915929891259765133431133080574997163780566488338154,"line":7470,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13720320035 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 13720320035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.27461433591428628984320982187069836800409192548127831126690206300306364455565","seed":27461433591428628984320982187069836800409192548127831126690206300306364455565,"line":471,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1300767152 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1300767152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.55133573585701447825162419028504640622118401682676215070341948843140053674467","seed":55133573585701447825162419028504640622118401682676215070341948843140053674467,"line":2172,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 12080195047 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 12080195047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.30112212069472689299093751467859112154522922224882501255423761439884818796108","seed":30112212069472689299093751467859112154522922224882501255423761439884818796108,"line":1958,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6594283187 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6594283187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"34.lc_ctrl_stress_all_with_rand_reset.59471362826611651212130779246351429491835611426761329133255527258091727975133","seed":59471362826611651212130779246351429491835611426761329133255527258091727975133,"line":2411,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1311276988 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1311276988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.2965626255916482018222518177129025288623844443896522680370803844417259295731","seed":2965626255916482018222518177129025288623844443896522680370803844417259295731,"line":7876,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3018516752 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3018516752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"38.lc_ctrl_stress_all_with_rand_reset.24663934150047920503105794130109869905423989135242291642645216118248830670663","seed":24663934150047920503105794130109869905423989135242291642645216118248830670663,"line":2260,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1350293692 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1350293692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.104529532382796789655376169903852353707953891454823317014667397899064740200231","seed":104529532382796789655376169903852353707953891454823317014667397899064740200231,"line":2260,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8105395490 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8105395490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.91592995376521030106717508204550984116743343510920799404260314339982368010008","seed":91592995376521030106717508204550984116743343510920799404260314339982368010008,"line":325,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11911464856 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 11911464856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.105941188780055376148903035382149512285170903229722597931724598108364897846411","seed":105941188780055376148903035382149512285170903229722597931724598108364897846411,"line":247,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1218506227 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1218506227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.30455201461206024051159354991420976799264955063987900508970305453643785036034","seed":30455201461206024051159354991420976799264955063987900508970305453643785036034,"line":1365,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 759552362 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 759552362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.63625542352376425029472606238484265029351618166279866840650229189342889448296","seed":63625542352376425029472606238484265029351618166279866840650229189342889448296,"line":13472,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3062439144 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestUnlocked4\n","UVM_INFO @ 3062439144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.10703034140874941644166617993830775572502789998713459449373282267421520395506","seed":10703034140874941644166617993830775572502789998713459449373282267421520395506,"line":2157,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 839197518 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_state_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q \n","UVM_INFO @ 839197518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_sec_mubi","qual_name":"18.lc_ctrl_sec_mubi.65413497707726033146717810219065640839466818478392704059804929355615837150350","seed":65413497707726033146717810219065640839466818478392704059804929355615837150350,"line":1634,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_mubi/latest/run.log","log_context":["UVM_ERROR @ 133985827 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 133985827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1001,"total":1030,"percent":97.18446601941747}