{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"1521b5f2d5d90c126b1cbab588514f5ecff12f40","commit_short":"1521b5f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40","revision_info":"GitHub Revision: [`1521b5f`](https://github.com/lowrisc/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-01T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":4.68,"sim_time":11337.944067,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"4.rstmgr_cnsty_chk_test.115624929758403085069923393772933050777832798381351884985919201145471446404106","seed":115624929758403085069923393772933050777832798381351884985919201145471446404106,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/4.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_ERROR @ 2036284067 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))  \n","UVM_INFO @ 2056764067 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 2077244067 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 2097724067 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 2118204067 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":9,"total":10,"percent":90.0}