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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.113770466353466687399803893441731192557232953060320890888795183794086540487365","seed":113770466353466687399803893441731192557232953060320890888795183794086540487365,"line":2468,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3927339443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.45308670357981753752512646493053955872008421677089808494302522764156147258379","seed":45308670357981753752512646493053955872008421677089808494302522764156147258379,"line":971,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 19304431343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.115730992273918919596118803767440568529791041846966697394374732254955197657791","seed":115730992273918919596118803767440568529791041846966697394374732254955197657791,"line":3364,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2501565788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"34.lc_ctrl_stress_all_with_rand_reset.49429056533664608573624933993664444163482469289123930923390334354933439404307","seed":49429056533664608573624933993664444163482469289123930923390334354933439404307,"line":511,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 8004458141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.78038550991006522303755913762171124979747909145840044421516829655416976180241","seed":78038550991006522303755913762171124979747909145840044421516829655416976180241,"line":399,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2565115074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.41117289998214245495839574499203111534257378115946196124566585208483408163552","seed":41117289998214245495839574499203111534257378115946196124566585208483408163552,"line":650,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2444502631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.46925602088598322728001307433917230883827245374215658644448833361918638709371","seed":46925602088598322728001307433917230883827245374215658644448833361918638709371,"line":371,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3643421064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.76139931144101424215765421472820391437027796461954458629357648396795217613330","seed":76139931144101424215765421472820391437027796461954458629357648396795217613330,"line":173,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 881261113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.71733311789461621785408377967021296082088129042224392773972147109682431220294","seed":71733311789461621785408377967021296082088129042224392773972147109682431220294,"line":2498,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1311186004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.83923466292552206264236806002116982174510972722164782756338129150830076844160","seed":83923466292552206264236806002116982174510972722164782756338129150830076844160,"line":1180,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 4961613232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_errors","qual_name":"1.lc_ctrl_errors.47028028855242600915254012262054671050361433523168733279669979608526954609022","seed":47028028855242600915254012262054671050361433523168733279669979608526954609022,"line":833,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_errors/latest/run.log","log_context":["UVM_INFO @ 108633911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"8.lc_ctrl_jtag_errors.69719259009144880341535623880221782587328545735255211663167830715711769860347","seed":69719259009144880341535623880221782587328545735255211663167830715711769860347,"line":1222,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_INFO @ 8786032514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!":[{"name":"lc_ctrl_jtag_priority","qual_name":"5.lc_ctrl_jtag_priority.55773600115086480107686379950278977778894433238091464670962524217796611785527","seed":55773600115086480107686379950278977778894433238091464670962524217796611785527,"line":157,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_priority/latest/run.log","log_context":["UVM_INFO @ 10006871848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error":[{"name":"lc_ctrl_jtag_state_failure","qual_name":"13.lc_ctrl_jtag_state_failure.81451679134380367868581351260482931404244682912648148432988596026298090081697","seed":81451679134380367868581351260482931404244682912648148432988596026298090081697,"line":177,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_state_failure/latest/run.log","log_context":["UVM_INFO @ 1186581726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:454) [lc_ctrl_common_vseq] wait timeout occurred!":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"23.lc_ctrl_stress_all_with_rand_reset.110143040610169609093456681566065719354833101940262651587334721012965204838100","seed":110143040610169609093456681566065719354833101940262651587334721012965204838100,"line":1907,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 11046494857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:246) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStProd":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"46.lc_ctrl_stress_all_with_rand_reset.55907583687603344171993303060679071092812443179084999001491611056686781020968","seed":55907583687603344171993303060679071092812443179084999001491611056686781020968,"line":3167,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2039058061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1000,"total":1030,"percent":97.0873786407767}