{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"f3ee88db1f6c979a899d8b35ac6ea706a46db43b","commit_short":"f3ee88d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/f3ee88db1f6c979a899d8b35ac6ea706a46db43b","revision_info":"GitHub Revision: [`f3ee88d`](https://github.com/lowrisc/opentitan/tree/f3ee88db1f6c979a899d8b35ac6ea706a46db43b)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-09T02:32:54Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":3.23,"sim_time":10932.634808,"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"6.rstmgr_cnsty_chk_test.10670424437861465052385955307703277902064724247049042728546570915870326286872","seed":10670424437861465052385955307703277902064724247049042728546570915870326286872,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/6.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 2056756082 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 2077236082 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 2097716082 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 2118196082 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"9.rstmgr_cnsty_chk_test.61539878991949935851594415904540217815009843703439279289251463993312551768205","seed":61539878991949935851594415904540217815009843703439279289251463993312551768205,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1864403361 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1882963361 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1901523361 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1920083361 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":8,"total":10,"percent":80.0}