{"block":{"name":"uart","variant":null,"commit":"f3ee88db1f6c979a899d8b35ac6ea706a46db43b","commit_short":"f3ee88d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/f3ee88db1f6c979a899d8b35ac6ea706a46db43b","revision_info":"GitHub Revision: [`f3ee88d`](https://github.com/lowrisc/opentitan/tree/f3ee88db1f6c979a899d8b35ac6ea706a46db43b)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-09T02:32:54Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":45.0,"sim_time":5890.599019,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":2.0,"sim_time":49.137216,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":22.0,"sim_time":16.479847000000003,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":4.0,"sim_time":2664.50731,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.0,"sim_time":30.783111,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":22.0,"sim_time":147.633905,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":22.0,"sim_time":16.479847000000003,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":30.783111,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":478.0,"sim_time":73716.37532199999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":45.0,"sim_time":5890.599019,"passed":50,"total":50,"percent":100.0},"uart_tx_rx":{"max_time":478.0,"sim_time":73716.37532199999,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":359.0,"sim_time":285197.600009,"passed":50,"total":50,"percent":100.0},"uart_rx_parity_err":{"max_time":398.0,"sim_time":130784.18998700002,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":478.0,"sim_time":73716.37532199999,"passed":50,"total":50,"percent":100.0},"uart_intr":{"max_time":359.0,"sim_time":285197.600009,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":441.0,"sim_time":219170.312016,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":343.0,"sim_time":225847.864636,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":411.0,"sim_time":158972.604207,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"rx_frame_err":{"tests":{"uart_intr":{"max_time":359.0,"sim_time":285197.600009,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":359.0,"sim_time":285197.600009,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":359.0,"sim_time":285197.600009,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":949.0,"sim_time":29688.18127,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":28.0,"sim_time":9778.659658,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":28.0,"sim_time":9778.659658,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":155.0,"sim_time":59348.147403999996,"passed":10,"total":50,"percent":20.0}},"passed":10,"total":50,"percent":20.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":110.0,"sim_time":53527.763295000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":46.0,"sim_time":6676.174296,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":61.0,"sim_time":6775.932181,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":1722.0,"sim_time":243660.352571,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":1368.0,"sim_time":300351.19371200004,"passed":43,"total":50,"percent":86.0}},"passed":43,"total":50,"percent":86.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":22.0,"sim_time":23.557616999999997,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":16.0,"sim_time":14.030014999999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":42.394951,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":42.394951,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":2.0,"sim_time":49.137216,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":22.0,"sim_time":16.479847000000003,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":30.783111,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":12.823069,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":2.0,"sim_time":49.137216,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":22.0,"sim_time":16.479847000000003,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":30.783111,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":12.823069,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1123,"total":1170,"percent":95.98290598290598},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":2.0,"sim_time":131.687414,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":3.0,"sim_time":127.094741,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":3.0,"sim_time":127.094741,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":111.0,"sim_time":5762.182028,"passed":83,"total":100,"percent":83.0}},"passed":83,"total":100,"percent":83.0}},"passed":83,"total":100,"percent":83.0}},"coverage":{"code":{"block":99.08,"line_statement":99.52,"branch":98.34,"condition_expression":null,"toggle":88.74,"fsm":100.0},"assertion":97.12,"functional":90.69},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1237) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"uart_stress_all_with_rand_reset","qual_name":"0.uart_stress_all_with_rand_reset.43645639936882158544211245027559004662012671521208461296242582966928855813853","seed":43645639936882158544211245027559004662012671521208461296242582966928855813853,"line":140,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3018926390 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3018926390 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 3018941534 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"55.uart_stress_all_with_rand_reset.6122715100359927510105119372079887839080627544097751817743475407314108261096","seed":6122715100359927510105119372079887839080627544097751817743475407314108261096,"line":210,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/55.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5153606797 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5153606797 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 10/10\n","UVM_INFO @ 5153613605 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2\n"]}],"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.113070174653572845306185681781653299047499434681992650638147224234237230604022","seed":113070174653572845306185681781653299047499434681992650638147224234237230604022,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 471508626 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 778748626 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 778748626 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2303948626 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.17838618496160900971242817588945986744509678765328569547766819071185415271885","seed":17838618496160900971242817588945986744509678765328569547766819071185415271885,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  14489274 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 367492098 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 367544730 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 367597362 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"2.uart_stress_all_with_rand_reset.107946042747401716243320775614972235216000419373726203089845172959667050216448","seed":107946042747401716243320775614972235216000419373726203089845172959667050216448,"line":176,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2084487924 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2084487924 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 2088714614 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/852\n","UVM_INFO @ 2112074808 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/852\n"]},{"name":"uart_stress_all","qual_name":"2.uart_stress_all.37430086126032877528614933221764932078742461851529336382195081826969973702583","seed":37430086126032877528614933221764932078742461851529336382195081826969973702583,"line":89,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 26855112731 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 26948272731 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 26948272731 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27268472731 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.25845049609473569695549337823293017671933680199804842084942026708567322765071","seed":25845049609473569695549337823293017671933680199804842084942026708567322765071,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 269333129 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 270242229 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 271151329 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 272060429 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.31099343325763792222808671160205726667047645988206544548931160039281587057382","seed":31099343325763792222808671160205726667047645988206544548931160039281587057382,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2928549647 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3034094691 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 3034115525 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_INFO @ 3034115525 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/17\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.99187562164102148135399084766252138481249238575165275787939159386819934932987","seed":99187562164102148135399084766252138481249238575165275787939159386819934932987,"line":99,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 27391032283 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 27391032283 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27396746523 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 27396746523 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.114386783294656111087075367076576493446032399884162118262797169330158001129999","seed":114386783294656111087075367076576493446032399884162118262797169330158001129999,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 327506187 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1474266187 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 1480466187 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 1480506187 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.91024120729086162888710893516961640383915868175237752072934784591847818880134","seed":91024120729086162888710893516961640383915868175237752072934784591847818880134,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 331736787 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 502565170 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 502565170 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 764083955 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"10.uart_noise_filter.45297995759095980585774206171083984088359371607238226855299510529487869742025","seed":45297995759095980585774206171083984088359371607238226855299510529487869742025,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 15848478085 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 15946506723 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 15946506723 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 16057166561 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all","qual_name":"10.uart_stress_all.53787525642435199884623282207840796006471991272537287654350850369489603834899","seed":53787525642435199884623282207840796006471991272537287654350850369489603834899,"line":119,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 179054248020 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 179054248020 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 180530419884 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 180530419884 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"11.uart_stress_all_with_rand_reset.55022310125773236663679475657648272398146870799941302449809506622075123592818","seed":55022310125773236663679475657648272398146870799941302449809506622075123592818,"line":184,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13526459796 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 13740143751 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/599\n","UVM_INFO @ 14312376746 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/599\n","UVM_ERROR @ 14674971281 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_noise_filter","qual_name":"14.uart_noise_filter.82484647288477404951614766841503329155021508204372567191512306844041662160205","seed":82484647288477404951614766841503329155021508204372567191512306844041662160205,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1919359194 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2005356872 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 2005356872 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2027088244 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"15.uart_noise_filter.39840387402281288657219111900132659595000107834354896395433570858351871278170","seed":39840387402281288657219111900132659595000107834354896395433570858351871278170,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 4158683322 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 5192983322 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 5193003322 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5193023322 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (30 [0x1e] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"20.uart_noise_filter.10830424706450427825031594024082070489798950780547904507665996098664485242868","seed":10830424706450427825031594024082070489798950780547904507665996098664485242868,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5298216668 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 5298216668 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5298216668 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 5308133652 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"23.uart_noise_filter.17486545365388724964089314164568709933902264160236081546608803041362654183864","seed":17486545365388724964089314164568709933902264160236081546608803041362654183864,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  19267685 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  28853591 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  29853611 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  30753629 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"27.uart_noise_filter.106708108981557853824706910694414921161022336455155974733392083598274645450420","seed":106708108981557853824706910694414921161022336455155974733392083598274645450420,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/27.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 120885908 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 326885702 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 340885688 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 360742811 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"27.uart_stress_all_with_rand_reset.35559955822448761768941792624815500842382021684538223833890241455081427724567","seed":35559955822448761768941792624815500842382021684538223833890241455081427724567,"line":111,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/27.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 167657128 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 208824124 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 578271524 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/390\n","UVM_ERROR @ 631605284 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n"]},{"name":"uart_noise_filter","qual_name":"28.uart_noise_filter.54392092098154189044908541039137413910071664205028100883177357645470051204186","seed":54392092098154189044908541039137413910071664205028100883177357645470051204186,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/28.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  12091857 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  12776073 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  13460289 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  14144505 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"32.uart_noise_filter.57883091911300934868128429541204756567561292814043065223827278489806922848385","seed":57883091911300934868128429541204756567561292814043065223827278489806922848385,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/32.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5104101047 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5111101040 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5116844624 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5120639492 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"34.uart_noise_filter.31854810098040540451910114745987792892420374636938863944475772586456538532645","seed":31854810098040540451910114745987792892420374636938863944475772586456538532645,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/34.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  49025439 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @  97212168 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @  97212168 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 162127796 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"35.uart_noise_filter.37396849692926471665888243769240408579509558367203657611753844517815081071625","seed":37396849692926471665888243769240408579509558367203657611753844517815081071625,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/35.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 19067761200 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 20214364272 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 20221384624 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 20521688344 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_noise_filter","qual_name":"36.uart_noise_filter.92159874308028078328320564271377930830659195379852152181103302741336874682865","seed":92159874308028078328320564271377930830659195379852152181103302741336874682865,"line":92,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/36.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 73426281137 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 73426281137 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 73632553918 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 73632553918 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"36.uart_stress_all.38106433112821400657952033390867845059434166768755794448835048294582157010764","seed":38106433112821400657952033390867845059434166768755794448835048294582157010764,"line":94,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/36.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 71655137298 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 73921377298 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 73921377298 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 75520057298 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_noise_filter","qual_name":"40.uart_noise_filter.14726248179644551401717657443625371854293588343525093680933266734080788535338","seed":14726248179644551401717657443625371854293588343525093680933266734080788535338,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/40.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 8068442584 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 8204082584 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8206822584 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8216622584 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"42.uart_noise_filter.67961090191525442808241003985754137040674937898892323588231735634717057632760","seed":67961090191525442808241003985754137040674937898892323588231735634717057632760,"line":89,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/42.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 23607028600 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 23615373244 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 23694854254 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 23694871495 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"43.uart_noise_filter.57350899083232237473968923745031168614547438927322157903631307755332515670988","seed":57350899083232237473968923745031168614547438927322157903631307755332515670988,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/43.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  44210290 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  44210290 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 669637783 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 669637783 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"44.uart_noise_filter.3888931076978133146598172446636879272641089619673132080510331883656994525945","seed":3888931076978133146598172446636879272641089619673132080510331883656994525945,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/44.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 713338000 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 722279248 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 732102856 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 742044112 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"49.uart_noise_filter.102939836876711209183911953638861584477347847802508484626599923155533251974195","seed":102939836876711209183911953638861584477347847802508484626599923155533251974195,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/49.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 59848571249 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 60012483309 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/16\n","UVM_INFO @ 61289562603 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 5/16\n","UVM_INFO @ 67766828087 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 6/16\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"84.uart_stress_all_with_rand_reset.4924810449796827625885790431023081478960997756605436358542639976708884681164","seed":4924810449796827625885790431023081478960997756605436358542639976708884681164,"line":93,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/84.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  43563218 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  53007568 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  53740894 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  54363110 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"88.uart_stress_all_with_rand_reset.44751087038532445247909990772037018051356547304084143460369020353754809413404","seed":44751087038532445247909990772037018051356547304084143460369020353754809413404,"line":146,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/88.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10873633553 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/357\n","UVM_INFO @ 10883699318 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 10883824319 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"91.uart_stress_all_with_rand_reset.52680441661913534996419928342284996611073896961580132724843060432131262306062","seed":52680441661913534996419928342284996611073896961580132724843060432131262306062,"line":144,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/91.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11055044956 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 11354189608 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/750\n","UVM_INFO @ 11771049252 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/750\n","UVM_ERROR @ 11830549609 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (149 [0x95] vs 85 [0x55]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.27934334517151191318268287392742984615342106843586053499040087591863457089167","seed":27934334517151191318268287392742984615342106843586053499040087591863457089167,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 816010475 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 816010475 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 820245135 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 11\n","UVM_ERROR @ 820255339 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.30048845292855414550390553771136145480469697398556079907080837845064173705746","seed":30048845292855414550390553771136145480469697398556079907080837845064173705746,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 117482545 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 117482545 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 157025477 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 157504659 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"18.uart_stress_all.61123897388939296742287282592945917489848680260083586242980668303200896499553","seed":61123897388939296742287282592945917489848680260083586242980668303200896499553,"line":183,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 812710075723 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 812710075723 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 813119075723 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 7\n","UVM_ERROR @ 813119275723 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"21.uart_noise_filter.28178286360714549177231673313912116958361610398595016152343369407258474065160","seed":28178286360714549177231673313912116958361610398595016152343369407258474065160,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 23761432487 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 23761432487 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 23793402487 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 23793402487 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"25.uart_noise_filter.11198476784388737935957905589427316800222384082654800124788402831763956890582","seed":11198476784388737935957905589427316800222384082654800124788402831763956890582,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/25.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 858338984 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 858338984 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 880658984 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 5\n","UVM_ERROR @ 880668984 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"29.uart_noise_filter.62021698429257350383464550437038312111584856856214305436737509385061352125902","seed":62021698429257350383464550437038312111584856856214305436737509385061352125902,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/29.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1603626968 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1603626968 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1612216184 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1615742394 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 8,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"31.uart_noise_filter.78845833697829965001545639372135513939242915318713821971747421100152429273016","seed":78845833697829965001545639372135513939242915318713821971747421100152429273016,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/31.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 549137197 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 551137189 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 551137189 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 556303835 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"33.uart_noise_filter.63322513743819554137864748968284185665793931764991399022728222649972887611543","seed":63322513743819554137864748968284185665793931764991399022728222649972887611543,"line":88,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/33.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 36699761977 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 36699761977 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 36734339887 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 6\n","UVM_ERROR @ 36734350413 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"37.uart_noise_filter.114973520331259010644068221221149947090018126025484813193987242034104884931439","seed":114973520331259010644068221221149947090018126025484813193987242034104884931439,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/37.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 7416102565 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 7416102565 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 7496230129 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 7496250963 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (229 [0xe5] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"45.uart_noise_filter.18831752723412072741141356635241520312116965235046136165460573015979094661017","seed":18831752723412072741141356635241520312116965235046136165460573015979094661017,"line":88,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/45.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 19965049285 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19965049285 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 20410369285 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 10,                                 clk_pulses: 0\n","UVM_ERROR @ 20410489285 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"47.uart_stress_all.11915277315109403643865143201956061471665645311348227229162652012483443622638","seed":11915277315109403643865143201956061471665645311348227229162652012483443622638,"line":97,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/47.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 72396679394 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 72396749394 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (237 [0xed] vs 238 [0xee]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 72396759394 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 72396769394 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (237 [0xed] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_stress_all","qual_name":"4.uart_stress_all.73873761115202014830351701156168667444547032147460447021559494038045682482570","seed":73873761115202014830351701156168667444547032147460447021559494038045682482570,"line":92,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 38389117762 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 38389159429 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (250 [0xfa] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 38390951110 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 38390992777 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.66702456074071305371573550973866451705373759777606018742087501307173951858224","seed":66702456074071305371573550973866451705373759777606018742087501307173951858224,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 10339135807 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10339145908 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (97 [0x61] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 10755559633 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 10755559633 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"12.uart_noise_filter.80223975193402849691935057745597846595678085629691474487873114084352057915481","seed":80223975193402849691935057745597846595678085629691474487873114084352057915481,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2581374196 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2581476236 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2647669584 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2647669584 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"16.uart_noise_filter.72482494432341257117587121882885451927128950277197451775874040663608579840549","seed":72482494432341257117587121882885451927128950277197451775874040663608579840549,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 23536510296 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 23536520934 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 23588530116 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 23588540754 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"17.uart_noise_filter.53168304563515986237242203796042639751559579058378102085619613979803198478331","seed":53168304563515986237242203796042639751559579058378102085619613979803198478331,"line":95,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 61925488628 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 61925528628 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (120 [0x78] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 61925568628 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 61925608628 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (120 [0x78] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"18.uart_noise_filter.21877546415898338428687536437674316334494340499061822377864127587747020977474","seed":21877546415898338428687536437674316334494340499061822377864127587747020977474,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 22893610348 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 22893943684 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (231 [0xe7] vs 190 [0xbe]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 22893985351 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 22894068685 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (231 [0xe7] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"24.uart_noise_filter.94249043607538775820501108423662288413256561049869830816615792131344146533939","seed":94249043607538775820501108423662288413256561049869830816615792131344146533939,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 76947716129 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 76947757796 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 76947799463 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 76947841130 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"26.uart_noise_filter.41141599697302047945718056246473004777514097623189827907213212158310169767448","seed":41141599697302047945718056246473004777514097623189827907213212158310169767448,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/26.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2291113687 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2291155354 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2291238688 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 2291280355 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"30.uart_noise_filter.24676432563813244197947840793494811343829843267421407990378513501610437586716","seed":24676432563813244197947840793494811343829843267421407990378513501610437586716,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/30.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1039021219 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1039059681 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1124368397 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1124368397 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"31.uart_stress_all_with_rand_reset.14821764623432401003081079249675111518548795387749256473839098153948987140274","seed":14821764623432401003081079249675111518548795387749256473839098153948987140274,"line":149,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/31.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9465498967 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 9465538967 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 249 [0xf9]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 9537698967 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/248\n","UVM_INFO @ 9741538967 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/248\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"36.uart_stress_all_with_rand_reset.75662834860759689715948391920414675198222631283601993101826665264932103892899","seed":75662834860759689715948391920414675198222631283601993101826665264932103892899,"line":152,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/36.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5449034361 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5449054361 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 5520914361 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/697\n","UVM_ERROR @ 5581234361 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"39.uart_noise_filter.98121699260802038245079870636198304129659341457846070849336413890085614045402","seed":98121699260802038245079870636198304129659341457846070849336413890085614045402,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/39.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3273956634 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 3273967160 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 3296513852 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 3296524378 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"61.uart_stress_all_with_rand_reset.55804042565215143356764293599010396497802916386302346137465968136699072967099","seed":55804042565215143356764293599010396497802916386302346137465968136699072967099,"line":116,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/61.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 817578548 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 817598956 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (117 [0x75] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 937577588 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/134\n","UVM_INFO @ 1092127372 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/134\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"81.uart_stress_all_with_rand_reset.114749962453238568025030334647932331691028990323686805554364436545745405068025","seed":114749962453238568025030334647932331691028990323686805554364436545745405068025,"line":96,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/81.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 924793346 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 924821917 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 933136078 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/324\n","UVM_ERROR @ 983792461 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]}],"UVM_ERROR (cip_base_vseq.sv:1150) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"uart_stress_all_with_rand_reset","qual_name":"15.uart_stress_all_with_rand_reset.46244514814851206348234838627215486458745414004430197962842238640950663111495","seed":46244514814851206348234838627215486458745414004430197962842238640950663111495,"line":190,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 8664558856 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 10/10\n","UVM_INFO @ 8664718856 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 10/10\n"]}],"UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"18.uart_stress_all_with_rand_reset.69366762866782421090550820144695716409540207630495347848685868895676028734044","seed":69366762866782421090550820144695716409540207630495347848685868895676028734044,"line":177,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7570588216 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 7570588216 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_ERROR @ 7570588216 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark\n","UVM_INFO @ 7643548216 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/29\n"]}],"UVM_FATAL (cip_base_vseq.sv:454) [uart_common_vseq] wait timeout occurred!":[{"name":"uart_stress_all_with_rand_reset","qual_name":"59.uart_stress_all_with_rand_reset.68568516755059323235363229054009298706538944109960696661066169823300983671686","seed":68568516755059323235363229054009298706538944109960696661066169823300983671686,"line":115,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/59.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10115326918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_stress_all_with_rand_reset","qual_name":"63.uart_stress_all_with_rand_reset.42012049849825148144269062444830257296513661618765792634066658654230397446980","seed":42012049849825148144269062444830257296513661618765792634066658654230397446980,"line":100,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/63.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 132817881 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 132984549 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 3/5\n"]}],"UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark":[{"name":"uart_stress_all_with_rand_reset","qual_name":"82.uart_stress_all_with_rand_reset.3509010823809773991092218790901587809546834742236533501887655686786789561317","seed":3509010823809773991092218790901587809546834742236533501887655686786789561317,"line":110,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/82.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 535850223 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 535912725 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 3/10\n"]}]}},"passed":1256,"total":1320,"percent":95.15151515151516}