{"block":{"name":"dma","variant":null,"commit":"1bd5f9a0371f862b10968297092488568751b0ed","commit_short":"1bd5f9a","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1bd5f9a0371f862b10968297092488568751b0ed","revision_info":"GitHub Revision: [`1bd5f9a`](https://github.com/lowrisc/opentitan/tree/1bd5f9a0371f862b10968297092488568751b0ed)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-30T03:06:07Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/dma/data/dma_testplan.html","stages":{"V1":{"testpoints":{"dma_memory_smoke":{"tests":{"dma_memory_smoke":{"max_time":8.0,"sim_time":572.6385379999999,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dma_handshake_smoke":{"tests":{"dma_handshake_smoke":{"max_time":9.0,"sim_time":1726.213217,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dma_generic_smoke":{"tests":{"dma_generic_smoke":{"max_time":9.0,"sim_time":2362.08996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"dma_csr_hw_reset":{"max_time":2.0,"sim_time":18.218274,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"dma_csr_rw":{"max_time":2.0,"sim_time":31.748518,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"dma_csr_bit_bash":{"max_time":16.0,"sim_time":5620.91492,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"dma_csr_aliasing":{"max_time":8.0,"sim_time":2356.6810269999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"dma_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":45.24101,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"dma_csr_rw":{"max_time":2.0,"sim_time":31.748518,"passed":5,"total":5,"percent":100.0},"dma_csr_aliasing":{"max_time":8.0,"sim_time":2356.6810269999996,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":113,"total":113,"percent":100.0},"V2":{"testpoints":{"dma_memory_region_lock":{"tests":{"dma_memory_region_lock":{"max_time":182.0,"sim_time":6914.3895489999995,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"dma_memory_tl_error":{"tests":{"dma_memory_stress":{"max_time":1372.0,"sim_time":180128.545979,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_handshake_tl_error":{"tests":{"dma_handshake_stress":{"max_time":531.0,"sim_time":233083.878868,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_handshake_stress":{"tests":{"dma_handshake_stress":{"max_time":531.0,"sim_time":233083.878868,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_memory_stress":{"tests":{"dma_memory_stress":{"max_time":1372.0,"sim_time":180128.545979,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_generic_stress":{"tests":{"dma_generic_stress":{"max_time":1326.0,"sim_time":84639.918479,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"dma_handshake_mem_buffer_overflow":{"tests":{"dma_handshake_stress":{"max_time":531.0,"sim_time":233083.878868,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_abort":{"tests":{"dma_abort":{"max_time":10.0,"sim_time":3044.879668,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"dma_stress_all":{"tests":{"dma_stress_all":{"max_time":485.00000000000006,"sim_time":135012.251183,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"alert_test":{"tests":{"dma_alert_test":{"max_time":2.0,"sim_time":56.864925,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"dma_intr_test":{"max_time":2.0,"sim_time":12.599785,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"dma_tl_errors":{"max_time":4.0,"sim_time":51.800083,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"dma_tl_errors":{"max_time":4.0,"sim_time":51.800083,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"dma_csr_hw_reset":{"max_time":2.0,"sim_time":18.218274,"passed":1,"total":1,"percent":100.0},"dma_csr_rw":{"max_time":2.0,"sim_time":31.748518,"passed":5,"total":5,"percent":100.0},"dma_csr_aliasing":{"max_time":8.0,"sim_time":2356.6810269999996,"passed":1,"total":1,"percent":100.0},"dma_same_csr_outstanding":{"max_time":3.0,"sim_time":210.741782,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"dma_csr_hw_reset":{"max_time":2.0,"sim_time":18.218274,"passed":1,"total":1,"percent":100.0},"dma_csr_rw":{"max_time":2.0,"sim_time":31.748518,"passed":5,"total":5,"percent":100.0},"dma_csr_aliasing":{"max_time":8.0,"sim_time":2356.6810269999996,"passed":1,"total":1,"percent":100.0},"dma_same_csr_outstanding":{"max_time":3.0,"sim_time":210.741782,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":81,"total":81,"percent":100.0},"V2S":{"testpoints":{"dma_illegal_addr_range":{"tests":{"dma_mem_enabled":{"max_time":35.0,"sim_time":378.468717,"passed":5,"total":5,"percent":100.0},"dma_generic_stress":{"max_time":1326.0,"sim_time":84639.918479,"passed":5,"total":5,"percent":100.0},"dma_handshake_stress":{"max_time":531.0,"sim_time":233083.878868,"passed":3,"total":3,"percent":100.0}},"passed":13,"total":13,"percent":100.0},"dma_config_lock":{"tests":{"dma_config_lock":{"max_time":14.0,"sim_time":337.069957,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tl_intg_err":{"tests":{"dma_tl_intg_err":{"max_time":5.0,"sim_time":801.694012,"passed":25,"total":25,"percent":100.0},"dma_sec_cm":{"max_time":2.0,"sim_time":22.603119,"passed":5,"total":5,"percent":100.0}},"passed":30,"total":30,"percent":100.0}},"passed":58,"total":58,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"dma_short_transfer":{"max_time":168.0,"sim_time":12766.100391,"passed":25,"total":25,"percent":100.0},"dma_longer_transfer":{"max_time":7.0,"sim_time":248.959834,"passed":5,"total":5,"percent":100.0},"dma_stress_all_with_rand_reset":{"max_time":20.0,"sim_time":6210.696690000001,"passed":0,"total":1,"percent":0.0}},"passed":30,"total":31,"percent":96.7741935483871}},"passed":30,"total":31,"percent":96.7741935483871}},"coverage":{"code":{"block":97.38,"line_statement":96.89,"branch":95.83,"condition_expression":null,"toggle":83.12,"fsm":92.96},"assertion":96.61,"functional":80.87},"cov_report_page":"/nightly/current_run/scratch/master/dma-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"dma_stress_all_with_rand_reset","qual_name":"0.dma_stress_all_with_rand_reset.94791697387356225082269881362828973408910329329211666315090644271109611227927","seed":94791697387356225082269881362828973408910329329211666315090644271109611227927,"line":124,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 6210696690ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":267,"total":268,"percent":99.6268656716418}