{"block":{"name":"uart","variant":null,"commit":"1bd5f9a0371f862b10968297092488568751b0ed","commit_short":"1bd5f9a","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1bd5f9a0371f862b10968297092488568751b0ed","revision_info":"GitHub Revision: [`1bd5f9a`](https://github.com/lowrisc/opentitan/tree/1bd5f9a0371f862b10968297092488568751b0ed)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-30T03:06:07Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":29.0,"sim_time":6284.243283,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":14.834438,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":45.659777999999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":2.0,"sim_time":130.723836,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.0,"sim_time":15.034692999999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":41.291913,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":45.659777999999996,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":15.034692999999999,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":145.0,"sim_time":66048.844493,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":29.0,"sim_time":6284.243283,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":145.0,"sim_time":66048.844493,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":128.0,"sim_time":76824.77677699999,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":234.0,"sim_time":104518.107012,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":145.0,"sim_time":66048.844493,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":128.0,"sim_time":76824.77677699999,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":280.0,"sim_time":191774.018928,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":240.0,"sim_time":113872.596673,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":460.0,"sim_time":328051.39164600003,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"rx_frame_err":{"tests":{"uart_intr":{"max_time":128.0,"sim_time":76824.77677699999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":128.0,"sim_time":76824.77677699999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":128.0,"sim_time":76824.77677699999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":524.0,"sim_time":14674.278389000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":25.0,"sim_time":8853.607254,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":25.0,"sim_time":8853.607254,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":46.0,"sim_time":64290.998117,"passed":1,"total":10,"percent":10.0}},"passed":1,"total":10,"percent":10.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":72.0,"sim_time":42463.280968,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":27.0,"sim_time":7002.895538,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":53.0,"sim_time":6352.751719,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":921.0,"sim_time":112098.50074799999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":951.0,"sim_time":453155.099486,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":2.0,"sim_time":41.868561,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":2.0,"sim_time":140.57583,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":2210.921715,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":2210.921715,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":14.834438,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":45.659777999999996,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":15.034692999999999,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":40.231324,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":14.834438,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":45.659777999999996,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":15.034692999999999,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":40.231324,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":387,"total":397,"percent":97.48110831234257},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":2.0,"sim_time":264.068231,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":2.0,"sim_time":225.47459899999998,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":2.0,"sim_time":225.47459899999998,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":75.0,"sim_time":11466.81353,"passed":16,"total":20,"percent":80.0}},"passed":16,"total":20,"percent":80.0}},"passed":16,"total":20,"percent":80.0}},"coverage":{"code":{"block":99.08,"line_statement":99.52,"branch":98.34,"condition_expression":null,"toggle":88.74,"fsm":100.0},"assertion":98.85,"functional":90.69},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.58394619627000603183767937445273283883754614238315726115003624306489822121307","seed":58394619627000603183767937445273283883754614238315726115003624306489822121307,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 23169720941 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 24215792838 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 24215792838 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 24472460788 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.47586073486191216769697153276763501906320366128137814509711472601425202656341","seed":47586073486191216769697153276763501906320366128137814509711472601425202656341,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1285108002 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2327116338 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2327324673 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2327908011 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"2.uart_stress_all_with_rand_reset.4736175215493761841393672214409279564105134210032313558220431606577763011151","seed":4736175215493761841393672214409279564105134210032313558220431606577763011151,"line":239,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10547744869 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/839\n","UVM_ERROR @ 10595880062 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_INFO @ 10697035122 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/839\n","UVM_ERROR @ 10704535212 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.21070264666756111992007423621643643803064507634608969543500411052923935461160","seed":21070264666756111992007423621643643803064507634608969543500411052923935461160,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 64250456126 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 64254789494 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 64255581167 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 64256289506 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.76574765602016900425506094414927017423336918953448950641117864228453785051991","seed":76574765602016900425506094414927017423336918953448950641117864228453785051991,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 461660251 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 461660251 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 464803127 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 464803127 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.32562610850103007653574901553095426725278793746101883199930378408657191421962","seed":32562610850103007653574901553095426725278793746101883199930378408657191421962,"line":162,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 148934672724 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 149404485224 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 149404532099 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 149404547724 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (247 [0xf7] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.17265337219361701090233720724726440804338732810656713689558654283319741785478","seed":17265337219361701090233720724726440804338732810656713689558654283319741785478,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 20250699777 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 20251007469 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 20251315161 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 20251622853 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.25899717755133877866795891326158606945073076701164241586835977194094599333343","seed":25899717755133877866795891326158606945073076701164241586835977194094599333343,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  16115282 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  24924797 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  30353363 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  38067641 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"13.uart_stress_all_with_rand_reset.8516031661424845246719480526878832274633879078735720412421355142881089363672","seed":8516031661424845246719480526878832274633879078735720412421355142881089363672,"line":100,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  46605825 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 148565825 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 148585825 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 148605825 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.1447416322274624336105566023178863335732623386386121139565201708034628381225","seed":1447416322274624336105566023178863335732623386386121139565201708034628381225,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 101644579 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 101654888 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 62 [0x3e]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 102407445 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0\n","UVM_ERROR @ 102417754 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.89794029084087744942173870275230852286838833850922365462776879161549400377691","seed":89794029084087744942173870275230852286838833850922365462776879161549400377691,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1730102904 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1730142904 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1827622904 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1827622904 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.86047911449356541936670511776139784835332602026534316409080392360556350984487","seed":86047911449356541936670511776139784835332602026534316409080392360556350984487,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 10742068079 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10742169089 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (237 [0xed] vs 123 [0x7b]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 10834734653 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 10834744754 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"11.uart_stress_all_with_rand_reset.79423056154912876069671522531384135045548133423824061586518321410388129555501","seed":79423056154912876069671522531384135045548133423824061586518321410388129555501,"line":126,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1264428325 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1264506757 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 1272859765 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/208\n","UVM_ERROR @ 1328389621 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n"]}],"UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"8.uart_stress_all_with_rand_reset.84820732710305029932520058971779648630901121383962044703315554361038629436711","seed":84820732710305029932520058971779648630901121383962044703315554361038629436711,"line":165,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 12184193664 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/296\n","UVM_ERROR @ 12459529200 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12459529200 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 12796809676 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/296\n"]}]}},"passed":439,"total":453,"percent":96.90949227373068}