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Summary ---\n","\n","\n"]},{"name":"gpio_stress_all","qual_name":"5.gpio_stress_all.53653200053316042492988733971299845098759386133357297323296802757480545055792","seed":53653200053316042492988733971299845098759386133357297323296802757480545055792,"line":836,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/5.gpio_stress_all/latest/run.log","log_context":["UVM_INFO @ 6450193334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all","qual_name":"6.gpio_stress_all.49664494894048652917510738999038962061005415462959249975547949949131519678563","seed":49664494894048652917510738999038962061005415462959249975547949949131519678563,"line":331,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/6.gpio_stress_all/latest/run.log","log_context":["UVM_INFO @ 1217875853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_rand_straps","qual_name":"6.gpio_rand_straps.58362021724002518822142187905519796138912306636997510605238117895833155455986","seed":58362021724002518822142187905519796138912306636997510605238117895833155455986,"line":75,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/6.gpio_rand_straps/latest/run.log","log_context":["UVM_INFO @   2452730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all","qual_name":"7.gpio_stress_all.97026375071425867293973472949574581060782010345196275619689226064833782623131","seed":97026375071425867293973472949574581060782010345196275619689226064833782623131,"line":78,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/7.gpio_stress_all/latest/run.log","log_context":["UVM_INFO @ 316254778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all","qual_name":"8.gpio_stress_all.111086700396299426184858046903882451514104977613423092111279974535318873631688","seed":111086700396299426184858046903882451514104977613423092111279974535318873631688,"line":2317,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/8.gpio_stress_all/latest/run.log","log_context":["UVM_INFO @ 14792892231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all","qual_name":"9.gpio_stress_all.9093740184916117316650461978572763573390459879084421993801976526578183749871","seed":9093740184916117316650461978572763573390459879084421993801976526578183749871,"line":486,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/9.gpio_stress_all/latest/run.log","log_context":["UVM_INFO @ 3279620549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL sequencer 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(uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"7.gpio_stress_all_with_rand_reset.43119573725930919941573967352549129418287308321481792399947241708344224159940","seed":43119573725930919941573967352549129418287308321481792399947241708344224159940,"line":669,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/7.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 4857792264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"9.gpio_stress_all_with_rand_reset.29631959569704910072976010478497911565880445468897032319688963388013729541615","seed":29631959569704910072976010478497911565880445468897032319688963388013729541615,"line":314,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/9.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 525914538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done)":[{"name":"gpio_stress_all_with_rand_reset","qual_name":"1.gpio_stress_all_with_rand_reset.86189238196251721376038560292057479151132154062071249873388557086139342370579","seed":86189238196251721376038560292057479151132154062071249873388557086139342370579,"line":290,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3898135254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"2.gpio_stress_all_with_rand_reset.13277488983183325313276999389820187713336608678575042755978000189296360272411","seed":13277488983183325313276999389820187713336608678575042755978000189296360272411,"line":81,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 783406775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"3.gpio_stress_all_with_rand_reset.37960611462836655509466420640048404324008029190767280693513025486706370406027","seed":37960611462836655509466420640048404324008029190767280693513025486706370406027,"line":83,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  47931103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"4.gpio_stress_all_with_rand_reset.23240391446768915815799023068368429936279164591697440549527690361007500472176","seed":23240391446768915815799023068368429936279164591697440549527690361007500472176,"line":80,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @   6061793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"6.gpio_stress_all_with_rand_reset.3468068945956641648668206673835080684330750671316164622431731931572445564149","seed":3468068945956641648668206673835080684330750671316164622431731931572445564149,"line":80,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/6.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  12268493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"8.gpio_stress_all_with_rand_reset.88572073123182057800674700247598903541457397686044388663004803580526815837922","seed":88572073123182057800674700247598903541457397686044388663004803580526815837922,"line":80,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/8.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @   7859842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"gpio_same_csr_outstanding","qual_name":"2.gpio_same_csr_outstanding.80487453998228917549440886801220492152547472185250285872587164475491569933706","seed":80487453998228917549440886801220492152547472185250285872587164475491569933706,"line":77,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/2.gpio_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @  39628284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: *":[{"name":"gpio_csr_rw","qual_name":"4.gpio_csr_rw.71821655303828920490966224475636040604200962318300812882832079038592109125061","seed":71821655303828920490966224475636040604200962318300812882832079038592109125061,"line":76,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/4.gpio_csr_rw/latest/run.log","log_context":["UVM_INFO @   4220163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: *":[{"name":"gpio_tl_intg_err","qual_name":"6.gpio_tl_intg_err.64030706259641492267367155205750725848045113498339762601831137179510033915286","seed":64030706259641492267367155205750725848045113498339762601831137179510033915286,"line":303,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/6.gpio_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 313033827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: 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