{"block":{"name":"uart","variant":null,"commit":"2348eb2d2a78c1cb023cfd0db2dc7500b046cbf7","commit_short":"2348eb2","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/2348eb2d2a78c1cb023cfd0db2dc7500b046cbf7","revision_info":"GitHub Revision: [`2348eb2`](https://github.com/lowrisc/opentitan/tree/2348eb2d2a78c1cb023cfd0db2dc7500b046cbf7)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-06-06T03:31:11Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":23.0,"sim_time":10546.286837,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":16.630214,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":13.016971,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":3.0,"sim_time":526.57285,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":2.0,"sim_time":20.962329,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":56.558508,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":13.016971,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":20.962329,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":87.0,"sim_time":64504.285342,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":23.0,"sim_time":10546.286837,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":87.0,"sim_time":64504.285342,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":364.0,"sim_time":229431.53571999999,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":615.0,"sim_time":176590.61006,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":87.0,"sim_time":64504.285342,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":364.0,"sim_time":229431.53571999999,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":550.0,"sim_time":285721.08494599996,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":199.0,"sim_time":98726.428646,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":461.0,"sim_time":311543.687291,"passed":199,"total":200,"percent":99.5}},"passed":199,"total":200,"percent":99.5},"rx_frame_err":{"tests":{"uart_intr":{"max_time":364.0,"sim_time":229431.53571999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":364.0,"sim_time":229431.53571999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":364.0,"sim_time":229431.53571999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":572.0,"sim_time":19505.802957,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":17.0,"sim_time":8344.966813000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":17.0,"sim_time":8344.966813000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":63.0,"sim_time":201689.341525,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":81.0,"sim_time":38241.651854,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":31.0,"sim_time":7183.892424,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":66.0,"sim_time":7039.520196,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":786.0,"sim_time":130634.888923,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":875.0,"sim_time":193540.71439500002,"passed":6,"total":10,"percent":60.0}},"passed":6,"total":10,"percent":60.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":2.0,"sim_time":82.412103,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":2.0,"sim_time":17.082701,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":79.563848,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":79.563848,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":16.630214,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":13.016971,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":20.962329,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":23.075771,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":16.630214,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":13.016971,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":20.962329,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":23.075771,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":381,"total":397,"percent":95.96977329974811},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":2.0,"sim_time":100.25846,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":2.0,"sim_time":87.107618,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":2.0,"sim_time":87.107618,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":64.0,"sim_time":15378.791277,"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0}},"coverage":{"code":{"block":99.08,"line_statement":99.52,"branch":98.34,"condition_expression":null,"toggle":88.74,"fsm":100.0},"assertion":98.56,"functional":90.69},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.52077194587008364910052856703460330677122352358272080043987729929545965428344","seed":52077194587008364910052856703460330677122352358272080043987729929545965428344,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  18334342 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  21542701 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  33459463 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @  35167810 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.76941928695305181591578315907784840737491761778552102820584405308443359222902","seed":76941928695305181591578315907784840737491761778552102820584405308443359222902,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 326583740 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 326583740 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1393596167 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (205 [0xcd] vs 154 [0x9a]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1651661364 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"7.uart_stress_all.110962117660465355806597656799056709241600170109414238695349511111553874401508","seed":110962117660465355806597656799056709241600170109414238695349511111553874401508,"line":92,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 57427720245 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 59392220245 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 10,                                 clk_pulses: 0\n","UVM_ERROR @ 59393345245 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (75 [0x4b] vs 175 [0xaf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 59614720245 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.11891627156224708952035353387364100553054239426690166318395800641376594209569","seed":11891627156224708952035353387364100553054239426690166318395800641376594209569,"line":92,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 201652925004 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 201652925004 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 201659008313 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 201659008313 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"9.uart_stress_all_with_rand_reset.37845678792525162268505307988920376253001032218279740167917634882878777725694","seed":37845678792525162268505307988920376253001032218279740167917634882878777725694,"line":179,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 11087301047 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 11087461047 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 7/10\n"]}],"UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_long_xfer_wo_dly","qual_name":"0.uart_long_xfer_wo_dly.33009892968333046839370793693815408239623487196503623734210963199017301155707","seed":33009892968333046839370793693815408239623487196503623734210963199017301155707,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_long_xfer_wo_dly/latest/run.log","log_context":["UVM_ERROR @ 21385735191 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 21631678335 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 21928504239 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 22061564127 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.91779891658897827845912130451735415047216215381561209091838432579972926554382","seed":91779891658897827845912130451735415047216215381561209091838432579972926554382,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 371747167 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 379907167 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 379907167 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 388687167 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.61342772717451005690758341540669418463104615727364404028605870693848957515712","seed":61342772717451005690758341540669418463104615727364404028605870693848957515712,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2241822624 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2246873124 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2246873124 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2248277163 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.76998019807632118560471745004566630206716350167402820678100037842538693763739","seed":76998019807632118560471745004566630206716350167402820678100037842538693763739,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  84684054 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  84684054 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 151775026 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0\n","UVM_ERROR @ 151795644 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (40 [0x28] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.41455805927872009305540748692334831287945652366513203410347325793318932445849","seed":41455805927872009305540748692334831287945652366513203410347325793318932445849,"line":95,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 94338632343 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 94338672343 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (48 [0x30] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 94421112343 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_ERROR @ 94421112343 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark\n"]},{"name":"uart_stress_all","qual_name":"1.uart_stress_all.65578194576164948188752666675670530779271836718914919700398829584130274910611","seed":65578194576164948188752666675670530779271836718914919700398829584130274910611,"line":98,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 137274273671 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 137274690341 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 137274732008 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 137275023677 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 110 [0x6e]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.109393588735859303632172601534668008704335303689075735052281820046671594816931","seed":109393588735859303632172601534668008704335303689075735052281820046671594816931,"line":191,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 165586953181 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 165587116445 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (62 [0x3e] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 165816808485 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 165816828893 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.47056442642867173701333014887646879192145347133813752729983929762860845142103","seed":47056442642867173701333014887646879192145347133813752729983929762860845142103,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  72275104 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @  72566773 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 317735401 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 317735401 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr\n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.8376184445090144990515896949438262172890101697489311616943480485992465424170","seed":8376184445090144990515896949438262172890101697489311616943480485992465424170,"line":88,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 74026577874 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 74027012654 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (152 [0x98] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 74027056132 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 74027230044 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (152 [0x98] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"8.uart_stress_all.15642928255577695594603302532090147886463882562178703513246796235537187717926","seed":15642928255577695594603302532090147886463882562178703513246796235537187717926,"line":98,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 136434741839 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 136434923659 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (245 [0xf5] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 136493060604 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 136493106059 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.947990402943413966602148897655592981949746484749307851941075453008708646607","seed":947990402943413966602148897655592981949746484749307851941075453008708646607,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 32488476369 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 32488518036 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 33282857724 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 33282899391 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}],"UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark":[{"name":"uart_stress_all_with_rand_reset","qual_name":"4.uart_stress_all_with_rand_reset.68345306057830169379073364670348619184386161469150947355989760085688160578110","seed":68345306057830169379073364670348619184386161469150947355989760085688160578110,"line":212,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 42834471671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/892\n","UVM_INFO @ 44248871671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/892\n","UVM_INFO @ 44956071671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/892\n","UVM_INFO @ 45894471671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/892\n"]}],"UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"11.uart_stress_all_with_rand_reset.5055699372868331556482620974197353552343408250529934903517884467054713157426","seed":5055699372868331556482620974197353552343408250529934903517884467054713157426,"line":179,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8755725075 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_ERROR @ 8755725075 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark\n","UVM_INFO @ 8993725075 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/138\n","UVM_ERROR @ 9008485075 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark":[{"name":"uart_fifo_reset","qual_name":"163.uart_fifo_reset.39780197042556922056169612172874054586172287570485069046670301070308125719534","seed":39780197042556922056169612172874054586172287570485069046670301070308125719534,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/163.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 926524959 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7\n","UVM_INFO @ 1723192055 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7\n","UVM_INFO @ 8443791351 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7\n","UVM_INFO @ 37937106423 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7\n"]}]}},"passed":434,"total":453,"percent":95.80573951434879}