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---\n","\n","\n"]},{"name":"gpio_rand_straps","qual_name":"9.gpio_rand_straps.110082001695457840174535793980469174323665413337181227910869755886321700535639","seed":110082001695457840174535793980469174323665413337181227910869755886321700535639,"line":75,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/9.gpio_rand_straps/latest/run.log","log_context":["UVM_INFO @   4907697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -*":[{"name":"gpio_stress_all_with_rand_reset","qual_name":"0.gpio_stress_all_with_rand_reset.35617050436694396701751916270727243300879551740331835248833087008205468846351","seed":35617050436694396701751916270727243300879551740331835248833087008205468846351,"line":349,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 591276166 ps: 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---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"3.gpio_stress_all_with_rand_reset.68303161596253241241023187557897585186026653839947587065901480295449940169633","seed":68303161596253241241023187557897585186026653839947587065901480295449940169633,"line":78,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @   2316407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"4.gpio_stress_all_with_rand_reset.3347220555324764373308488388587846883363197950731022687477149388917298666719","seed":3347220555324764373308488388587846883363197950731022687477149388917298666719,"line":168,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 149472573 ps: (uvm_report_catcher.svh:705) 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---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"6.gpio_stress_all_with_rand_reset.42081277546680867457678735536111900216042103383833940776099876915103499437315","seed":42081277546680867457678735536111900216042103383833940776099876915103499437315,"line":140,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/6.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  45130520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"8.gpio_stress_all_with_rand_reset.3103076973667829827787075973504906621353012925795841121073441294226977939686","seed":3103076973667829827787075973504906621353012925795841121073441294226977939686,"line":80,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/8.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @   2275964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_stress_all_with_rand_reset","qual_name":"9.gpio_stress_all_with_rand_reset.37541435518990761592516509400930726541334432683019684686241887640342126760169","seed":37541435518990761592516509400930726541334432683019684686241887640342126760169,"line":80,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/9.gpio_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  12021155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"gpio_same_csr_outstanding","qual_name":"4.gpio_same_csr_outstanding.9090862318342987495980741932984801502256794857407638099098871446097880910230","seed":9090862318342987495980741932984801502256794857407638099098871446097880910230,"line":79,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/4.gpio_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @  17084766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: *":[{"name":"gpio_tl_intg_err","qual_name":"6.gpio_tl_intg_err.94936966811130426964529402816212581848073841828307933502378915257634182327935","seed":94936966811130426964529402816212581848073841828307933502378915257634182327935,"line":135,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/6.gpio_tl_intg_err/latest/run.log","log_context":["UVM_INFO @  44260395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"gpio_tl_intg_err","qual_name":"8.gpio_tl_intg_err.13642083414765995670754515655655793302326555932585175721962051480842887356685","seed":13642083414765995670754515655655793302326555932585175721962051480842887356685,"line":137,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/8.gpio_tl_intg_err/latest/run.log","log_context":["UVM_INFO @  81652184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: *":[{"name":"gpio_tl_intg_err","qual_name":"11.gpio_tl_intg_err.56916459273006521189565313808718828271077804712091560914786813697409075238410","seed":56916459273006521189565313808718828271077804712091560914786813697409075238410,"line":212,"log_path":"/nightly/current_run/scratch/master/gpio-sim-vcs/11.gpio_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 207288135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":276,"total":303,"percent":91.08910891089108}