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---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.27160017110680452277758200524657151858568938471020535829817875205819587565443","seed":27160017110680452277758200524657151858568938471020535829817875205819587565443,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 685419649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.87120563114958305743039366268167124291243276380337176942889123014786605170887","seed":87120563114958305743039366268167124291243276380337176942889123014786605170887,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 2856277571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.104101502972438766988166332088497354842904139577151474994086095161054731919817","seed":104101502972438766988166332088497354842904139577151474994086095161054731919817,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 4737035144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.97010238032728740384115751782688841565897820848966617450250534371375028338488","seed":97010238032728740384115751782688841565897820848966617450250534371375028338488,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 2464509979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.102999818377258018205638831102592813798425366464101442441723965323097948844358","seed":102999818377258018205638831102592813798425366464101442441723965323097948844358,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 691299720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.sram_ctrl_csr_mem_rw_with_rand_reset.57986363031038458248158883567700131637399211929023318083722030002921743009165","seed":57986363031038458248158883567700131637399211929023318083722030002921743009165,"line":85,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10007560495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"4.sram_ctrl_csr_mem_rw_with_rand_reset.97365623817818130813515729898457448013781683170396256189077712501596498435965","seed":97365623817818130813515729898457448013781683170396256189077712501596498435965,"line":85,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10004701789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * 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