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[*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.83366239781541573009987945545819002827084845851092367837152595938460873535102","seed":83366239781541573009987945545819002827084845851092367837152595938460873535102,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  58384127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.66441479557677998284665077351196042200110974166206580654364577542315921177051","seed":66441479557677998284665077351196042200110974166206580654364577542315921177051,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  45085453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.71067916192089528511208541784508265259808024837725790720800728354172809309119","seed":71067916192089528511208541784508265259808024837725790720800728354172809309119,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  66013878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.91951826340080386204896729838347538703031513098579337288667088930886398594705","seed":91951826340080386204896729838347538703031513098579337288667088930886398594705,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 127930822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.108296422096070507723070778072513912547091495380576756194566192746206555378058","seed":108296422096070507723070778072513912547091495380576756194566192746206555378058,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  59574447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.107808435232736422083470493077195188448878949030034408371098141587682906434533","seed":107808435232736422083470493077195188448878949030034408371098141587682906434533,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 120393248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.73657947710252651088918609812633952188089828995948496122974334271130444442223","seed":73657947710252651088918609812633952188089828995948496122974334271130444442223,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 243161053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.61547620755423301885139884845173355670940983200444804006044095910806225757904","seed":61547620755423301885139884845173355670940983200444804006044095910806225757904,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  33649370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"2.sram_ctrl_csr_mem_rw_with_rand_reset.20830943643961522088069791632118529928473185067460868937150043630435543504563","seed":20830943643961522088069791632118529928473185067460868937150043630435543504563,"line":88,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  94277926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"3.sram_ctrl_csr_mem_rw_with_rand_reset.46253001119660136132396130697833330665047289088176549764572686229011418374720","seed":46253001119660136132396130697833330665047289088176549764572686229011418374720,"line":85,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10002160492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":222,"total":248,"percent":89.51612903225806}