{"block":{"name":"uart","variant":null,"commit":"e804155037bae974a43fb854e9b7de8c06f5a948","commit_short":"e804155","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/e804155037bae974a43fb854e9b7de8c06f5a948","revision_info":"GitHub Revision: [`e804155`](https://github.com/lowrisc/opentitan/tree/e804155037bae974a43fb854e9b7de8c06f5a948)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-06-12T15:00:31Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":17.0,"sim_time":5342.127801,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":28.036673,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":34.008962,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":3.0,"sim_time":154.85565400000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":2.0,"sim_time":39.74608,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":3.0,"sim_time":412.59571600000004,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":34.008962,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":39.74608,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":104.0,"sim_time":112164.267397,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":17.0,"sim_time":5342.127801,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":104.0,"sim_time":112164.267397,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":135.0,"sim_time":97977.527813,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":196.0,"sim_time":185193.54395,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":104.0,"sim_time":112164.267397,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":135.0,"sim_time":97977.527813,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":299.0,"sim_time":163644.933912,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":168.0,"sim_time":178472.272023,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":380.0,"sim_time":135435.727377,"passed":199,"total":200,"percent":99.5}},"passed":199,"total":200,"percent":99.5},"rx_frame_err":{"tests":{"uart_intr":{"max_time":135.0,"sim_time":97977.527813,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":135.0,"sim_time":97977.527813,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":135.0,"sim_time":97977.527813,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":430.0,"sim_time":19569.864273,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":30.0,"sim_time":7447.009709,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":30.0,"sim_time":7447.009709,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":47.0,"sim_time":107093.70045100001,"passed":1,"total":10,"percent":10.0}},"passed":1,"total":10,"percent":10.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":70.0,"sim_time":36266.17968,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":16.0,"sim_time":14416.346878,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":39.0,"sim_time":5276.878971,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":642.0,"sim_time":149311.02110800002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":859.0,"sim_time":323241.465524,"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":2.0,"sim_time":38.63834,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":2.0,"sim_time":48.181188,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":119.128254,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":119.128254,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":28.036673,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":34.008962,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":39.74608,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":89.770899,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":28.036673,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":34.008962,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":39.74608,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":89.770899,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":384,"total":397,"percent":96.72544080604534},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.0,"sim_time":123.070217,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":3.0,"sim_time":102.984649,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":3.0,"sim_time":102.984649,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":45.0,"sim_time":9328.126638,"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0}},"coverage":{"code":{"block":99.08,"line_statement":99.52,"branch":98.34,"condition_expression":null,"toggle":88.74,"fsm":100.0},"assertion":98.85,"functional":90.69},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.32483672380559491989200625948781075079314833266888567213853021657492811829253","seed":32483672380559491989200625948781075079314833266888567213853021657492811829253,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  53441329 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 107213883 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 107213883 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 254426927 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.53518499090338795830386200528617929563685171142244157076155871272127552404001","seed":53518499090338795830386200528617929563685171142244157076155871272127552404001,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 639594220 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 639594220 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 647804812 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 653278540 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.2728563382850211447732785490646159015034369392163413457773771162034919531140","seed":2728563382850211447732785490646159015034369392163413457773771162034919531140,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @   6565080 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @  69629598 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @  69712934 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @  69796270 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (230 [0xe6] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.32417935306772445643217342612064090889362033332595850176000715550252147027976","seed":32417935306772445643217342612064090889362033332595850176000715550252147027976,"line":89,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 107035311095 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 107036366659 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 107037588891 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 107038811123 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.2522948601850192763523838860594759597063887490659832068483837196838458891445","seed":2522948601850192763523838860594759597063887490659832068483837196838458891445,"line":109,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 21722009800 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 22009778743 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 22009778743 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 22159368337 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.14977929264296148881814734495099199397998300320897904719513296601821926820247","seed":14977929264296148881814734495099199397998300320897904719513296601821926820247,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 284012727 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1826632727 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1826632727 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3058472727 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"8.uart_stress_all.48849397934327230962817254270187016004541762090696818468737001953375980361602","seed":48849397934327230962817254270187016004541762090696818468737001953375980361602,"line":111,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 427238858772 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 428167241199 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 2\n","UVM_ERROR @ 428167324533 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 428167407867 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 178 [0xb2]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.76134254046229649781568038678717625100043585974238847538610911847799133607183","seed":76134254046229649781568038678717625100043585974238847538610911847799133607183,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18782907584 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 19850723003 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 19859556619 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 19987602383 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"14.uart_stress_all_with_rand_reset.12662644473274943195771635222169411318460837491115170170686409710583110422086","seed":12662644473274943195771635222169411318460837491115170170686409710583110422086,"line":173,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11532590183 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 11611244973 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 11616706577 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_INFO @ 11839901563 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/149\n"]}],"UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_stress_all_with_rand_reset","qual_name":"3.uart_stress_all_with_rand_reset.50336793420222117606116095922514313586346892509619986578367115369535879292096","seed":50336793420222117606116095922514313586346892509619986578367115369535879292096,"line":89,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 180369911 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 180379911 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 239569911 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/668\n","UVM_INFO @ 288509911 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/668\n"]},{"name":"uart_stress_all","qual_name":"4.uart_stress_all.97943732452134770578197676500728742940491351987743329152939885167846675687783","seed":97943732452134770578197676500728742940491351987743329152939885167846675687783,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5653960525 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5653970525 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (111 [0x6f] vs 229 [0xe5]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 5865990525 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 5865990525 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.47006729077643068161351477144068388813107732763090625501588880155582764490634","seed":47006729077643068161351477144068388813107732763090625501588880155582764490634,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3073588659 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 3073630325 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 3073671991 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 3073817822 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.114021198471067019158746588947297819365201119079992940382881020347724070615904","seed":114021198471067019158746588947297819365201119079992940382881020347724070615904,"line":88,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 60222759100 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 60222804555 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (52 [0x34] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 60734627855 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 60734627855 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.21007863738654477484223242086162105059388457539970169700674033738002969168534","seed":21007863738654477484223242086162105059388457539970169700674033738002969168534,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 537676516 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 537676516 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 570326516 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 2\n","UVM_ERROR @ 570346516 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}],"UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"17.uart_stress_all_with_rand_reset.10030244417056532899536988713243529534635308909986338316794673653164927746861","seed":10030244417056532899536988713243529534635308909986338316794673653164927746861,"line":109,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1878799415 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_INFO @ 1949239415 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/613\n","UVM_ERROR @ 2078019415 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2078019415 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_fifo_reset","qual_name":"21.uart_fifo_reset.30265856767817709651757385231122532741075152127578998177022448723279928213617","seed":30265856767817709651757385231122532741075152127578998177022448723279928213617,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 4621260069 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5\n","UVM_INFO @ 11372860069 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5\n","UVM_INFO @ 37080410069 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5\n","UVM_INFO @ 65514960069 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5\n"]}]}},"passed":437,"total":453,"percent":96.46799116997792}