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[*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.72675355215113543963925866275498441571730378173114972897404260907252629742970","seed":72675355215113543963925866275498441571730378173114972897404260907252629742970,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  32874842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.113461660966979961992948926215044035940610425400521999602312746658459427085645","seed":113461660966979961992948926215044035940610425400521999602312746658459427085645,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  44804506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.94454462329260401323205677433792155038558056157934554766945260769946785640174","seed":94454462329260401323205677433792155038558056157934554766945260769946785640174,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  32323642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.71542203518615134257097032193720024173478731774586837244577956712693624128997","seed":71542203518615134257097032193720024173478731774586837244577956712693624128997,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 168700118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.86777246221643772888434585226675694671466283854648705210388728079269532023577","seed":86777246221643772888434585226675694671466283854648705210388728079269532023577,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  48663699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.53250692230917590460787438538529154055839011044639821037707026885079181611969","seed":53250692230917590460787438538529154055839011044639821037707026885079181611969,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  88568935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.85345596906231457549658607731162485138655237285915787376446866267064612150102","seed":85345596906231457549658607731162485138655237285915787376446866267064612150102,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 311527930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.46930896021979959002275977734969988547485111115068351392705540805266889316341","seed":46930896021979959002275977734969988547485111115068351392705540805266889316341,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 179132123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*])":[{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"4.sram_ctrl_stress_all_with_rand_reset.102193904241346353994362543261466953783770397532593880910332660954673003171636","seed":102193904241346353994362543261466953783770397532593880910332660954673003171636,"line":115,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 209354136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"4.sram_ctrl_csr_mem_rw_with_rand_reset.101164110285396368728933193942183339217547128017179659928635269320988357752672","seed":101164110285396368728933193942183339217547128017179659928635269320988357752672,"line":85,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10016329437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":222,"total":248,"percent":89.51612903225806}