{"block":{"name":"sram_ctrl","variant":"main","commit":"9b639d2bc3321697d040cde7b4aea812807d96ab","commit_short":"9b639d2","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/9b639d2bc3321697d040cde7b4aea812807d96ab","revision_info":"GitHub Revision: [`9b639d2`](https://github.com/lowrisc/opentitan/tree/9b639d2bc3321697d040cde7b4aea812807d96ab)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-06-26T15:00:32Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_main/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":6.0,"sim_time":691.591566,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":19.848497,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":43.551970000000004,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":3.0,"sim_time":137.38436199999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":79.171007,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":6.0,"sim_time":360.262066,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":43.551970000000004,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":79.171007,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":324.0,"sim_time":183934.215141,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":136.0,"sim_time":30320.129466,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0}},"passed":37,"total":37,"percent":100.0},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":55.0,"sim_time":24389.825998,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":215.0,"sim_time":5644.982499,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":236.0,"sim_time":174791.133377,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":84.0,"sim_time":48444.584004000004,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":83.0,"sim_time":28211.568039,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":47.0,"sim_time":6766.850029,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":6.0,"sim_time":729.01339,"passed":8,"total":8,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":381.0,"sim_time":206965.550771,"passed":8,"total":8,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":7.0,"sim_time":2748.365063,"passed":0,"total":8,"percent":0.0},"sram_ctrl_throughput_w_partial_write":{"max_time":9.0,"sim_time":13195.931712,"passed":0,"total":8,"percent":0.0},"sram_ctrl_throughput_w_readback":{"max_time":7.0,"sim_time":1340.636,"passed":0,"total":8,"percent":0.0}},"passed":0,"total":24,"percent":0.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":19.0,"sim_time":2947.534584,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":5.0,"sim_time":3351.862646,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":785.0,"sim_time":322389.407246,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":2.0,"sim_time":14.778762,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":6.0,"sim_time":307.33711800000003,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":6.0,"sim_time":307.33711800000003,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":19.848497,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":43.551970000000004,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":79.171007,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":16.667096,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":19.848497,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":43.551970000000004,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":79.171007,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":16.667096,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":135,"total":159,"percent":84.90566037735849},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":44.0,"sim_time":87947.71261599999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3176.703586,"passed":5,"total":5,"percent":100.0},"sram_ctrl_tl_intg_err":{"max_time":4.0,"sim_time":364.720332,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3176.703586,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":4.0,"sim_time":364.720332,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":19.0,"sim_time":2947.534584,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":19.0,"sim_time":2947.534584,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":43.551970000000004,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":47.0,"sim_time":6766.850029,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":47.0,"sim_time":6766.850029,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":47.0,"sim_time":6766.850029,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":83.0,"sim_time":28211.568039,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":8.0,"sim_time":4155.232945,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":44.0,"sim_time":87947.71261599999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":8.0,"sim_time":4770.4240549999995,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":6.0,"sim_time":691.591566,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":6.0,"sim_time":691.591566,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":47.0,"sim_time":6766.850029,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3176.703586,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":83.0,"sim_time":28211.568039,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3176.703586,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3176.703586,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":6.0,"sim_time":691.591566,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3176.703586,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":88,"total":88,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":45.0,"sim_time":19180.137655000002,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0}},"coverage":{"code":{"block":96.17,"line_statement":96.9,"branch":94.34,"condition_expression":null,"toggle":91.84,"fsm":100.0},"assertion":98.1,"functional":96.4},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*])":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.37461380668206925583175049528866451996263910745519829583383139503661199878531","seed":37461380668206925583175049528866451996263910745519829583383139503661199878531,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 689127526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"0.sram_ctrl_throughput_w_partial_write.53399262960494341040419024040533189638767000384654687364456906752931554015681","seed":53399262960494341040419024040533189638767000384654687364456906752931554015681,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 1384821247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"1.sram_ctrl_max_throughput.78543713116136611292820814661393430107091633866100983703492561107982288695109","seed":78543713116136611292820814661393430107091633866100983703492561107982288695109,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 2748365063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"1.sram_ctrl_throughput_w_partial_write.94563511307217604749611837511364264428634009649098293389976738139978814312940","seed":94563511307217604749611837511364264428634009649098293389976738139978814312940,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 667867313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"2.sram_ctrl_max_throughput.36013634816419029027685646857855769477483454813553691380976416265934207348677","seed":36013634816419029027685646857855769477483454813553691380976416265934207348677,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 1393445640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"2.sram_ctrl_throughput_w_partial_write.99363490166830481900596877804190659713582288911610193210026274216061837273452","seed":99363490166830481900596877804190659713582288911610193210026274216061837273452,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 2626862427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"3.sram_ctrl_max_throughput.44856493424533946287529208525867869557541362458835514455349347914242555361301","seed":44856493424533946287529208525867869557541362458835514455349347914242555361301,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 1297675236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"3.sram_ctrl_throughput_w_partial_write.92493039742513272737048580166019929711834880187338713399070449890216694985981","seed":92493039742513272737048580166019929711834880187338713399070449890216694985981,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 13195931712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"4.sram_ctrl_max_throughput.99367586340729275114105758182004585440183353984644592602198355354928647099519","seed":99367586340729275114105758182004585440183353984644592602198355354928647099519,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 1407302198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"4.sram_ctrl_throughput_w_partial_write.90129512807750718397529430629647392469808817264551298602346326591756758956822","seed":90129512807750718397529430629647392469808817264551298602346326591756758956822,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 9427396993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"5.sram_ctrl_max_throughput.18885484691991134335577820844638327858945394018473341881734543536797291296319","seed":18885484691991134335577820844638327858945394018473341881734543536797291296319,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 2662375489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"5.sram_ctrl_throughput_w_partial_write.33530072839018748966841375134816702334864515797402081423330142714802946431969","seed":33530072839018748966841375134816702334864515797402081423330142714802946431969,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 5473927049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"6.sram_ctrl_max_throughput.80693707111673172904845637018560860535835112177526838539061555032916592394484","seed":80693707111673172904845637018560860535835112177526838539061555032916592394484,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 868330849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"6.sram_ctrl_throughput_w_partial_write.69414994258327076042392722486851024969086677085020831702621227088428279350570","seed":69414994258327076042392722486851024969086677085020831702621227088428279350570,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 689438721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"7.sram_ctrl_max_throughput.50946235091455969172330617781073096929454554472116292847312146117163411603914","seed":50946235091455969172330617781073096929454554472116292847312146117163411603914,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 2643339572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"7.sram_ctrl_throughput_w_partial_write.36312139168426565856052208649442296952824670096263595266143546265045139376023","seed":36312139168426565856052208649442296952824670096263595266143546265045139376023,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 2871025534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.4541792082987899208984503754116203424879529676601032991275927190103631029573","seed":4541792082987899208984503754116203424879529676601032991275927190103631029573,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 671097102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.87918792515305065189475707777483398006659848776264867745172936454791500502675","seed":87918792515305065189475707777483398006659848776264867745172936454791500502675,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 1355379536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.53516197107749803378915777744014706539954448298460373028101348292598819610284","seed":53516197107749803378915777744014706539954448298460373028101348292598819610284,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 709085102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.34127876650092439199282037558688119223537314824623195391888517327863787967491","seed":34127876650092439199282037558688119223537314824623195391888517327863787967491,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 2764397728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.91306425814125140623161569927157405454129541840143035696598816687273001612286","seed":91306425814125140623161569927157405454129541840143035696598816687273001612286,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 695012329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.20224070214050788741586878466024017553890221064966451919221486181416105081945","seed":20224070214050788741586878466024017553890221064966451919221486181416105081945,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 1340636000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.3484372842618082756551160618325568855189555100290649182630810389956793126901","seed":3484372842618082756551160618325568855189555100290649182630810389956793126901,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 2764174275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.18009576073279154163231386863119333165040112254883589454765493463160437989463","seed":18009576073279154163231386863119333165040112254883589454765493463160437989463,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 2772716774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":224,"total":248,"percent":90.3225806451613}