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[UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.94956773730907370826234390163998418720546051794494215611265265312356650920319","seed":94956773730907370826234390163998418720546051794494215611265265312356650920319,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 121310901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.30845251496550593043640998782833589960539631387443492896164264490780914573709","seed":30845251496550593043640998782833589960539631387443492896164264490780914573709,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  44635522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.88026410118387097152792069017565104852297533065270035431492300449222460145039","seed":88026410118387097152792069017565104852297533065270035431492300449222460145039,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  63162342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.96463570903140610661447817694948045351678157823340161302015539660614451803295","seed":96463570903140610661447817694948045351678157823340161302015539660614451803295,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  22879966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.107867636585630265623092130085155470477609395753036767802655090679377290520982","seed":107867636585630265623092130085155470477609395753036767802655090679377290520982,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  56353489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.43849841021447405031546248752987573628742879771687666566574624444006155204917","seed":43849841021447405031546248752987573628742879771687666566574624444006155204917,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  60292042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (mem_model.sv:49) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch":[{"name":"sram_ctrl_stress_all","qual_name":"7.sram_ctrl_stress_all.82344605742979318951577241070259300725463007253725819081964856706876918096838","seed":82344605742979318951577241070259300725463007253725819081964856706876918096838,"line":197,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 2607073319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":223,"total":248,"percent":89.91935483870968}