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[UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"9.otbn_stress_all_with_rand_reset.16975413091976823249804430009680582330514247696106338381896655289626568810452","seed":16975413091976823249804430009680582330514247696106338381896655289626568810452,"line":170,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2256374430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"otbn_mem_gnt_acc_err","qual_name":"0.otbn_mem_gnt_acc_err.83319988025619840144415376458765500774408426948635636975337979791975097513107","seed":83319988025619840144415376458765500774408426948635636975337979791975097513107,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]},{"name":"otbn_single","qual_name":"78.otbn_single.68506859702434987536327364887357151714371439232622452896114875481947771610935","seed":68506859702434987536327364887357151714371439232622452896114875481947771610935,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/78.otbn_single/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed":[{"name":"otbn_sec_cm","qual_name":"0.otbn_sec_cm.8718843320621505757714336849045535806658742271555876420163191902519717668092","seed":8718843320621505757714336849045535806658742271555876420163191902519717668092,"line":140,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log","log_context":["UVM_ERROR @  75459768 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @  75459768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"otbn_sec_cm","qual_name":"1.otbn_sec_cm.85972243217821836708611807451872131988323405884119985706660214729500765747603","seed":85972243217821836708611807451872131988323405884119985706660214729500765747603,"line":104,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log","log_context":["UVM_ERROR @  68089019 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @  68089019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"otbn_sec_cm","qual_name":"4.otbn_sec_cm.75550109732037178143164284760583609492787601480712114820101838779322012932947","seed":75550109732037178143164284760583609492787601480712114820101838779322012932947,"line":85,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log","log_context":["UVM_ERROR @   1036905 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @   1036905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS)":[{"name":"otbn_partial_wipe","qual_name":"1.otbn_partial_wipe.111989135649285016115636449600578583368039777085354278023837575310651970424144","seed":111989135649285016115636449600578583368039777085354278023837575310651970424144,"line":123,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_partial_wipe/latest/run.log","log_context":["UVM_ERROR @  26730923 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A\n","UVM_INFO @  26730923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"2.otbn_stress_all_with_rand_reset.36690625615618796017154901203092015034052707999824582394733395074218013554218","seed":36690625615618796017154901203092015034052707999824582394733395074218013554218,"line":222,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 484879894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed":[{"name":"otbn_zero_state_err_urnd","qual_name":"4.otbn_zero_state_err_urnd.19826490084770272502345957106228838928278429246957493929562365322689703720429","seed":19826490084770272502345957106228838928278429246957493929562365322689703720429,"line":107,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log","log_context":["UVM_ERROR @  33754958 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  33754958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.90735898443621006873847885355045503251900175684417933871896582050298544145915","seed":90735898443621006873847885355045503251900175684417933871896582050298544145915,"line":154,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  62885375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status":[{"name":"otbn_escalate","qual_name":"57.otbn_escalate.70393049093676076928431470374090169429835314758178962806814594198043767807159","seed":70393049093676076928431470374090169429835314758178962806814594198043767807159,"line":106,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/57.otbn_escalate/latest/run.log","log_context":["UVM_INFO @   4851883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":418,"total":436,"percent":95.87155963302752}