{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"58f8fdd5396817b775d2c69af9a6322ac7a84e5a","commit_short":"58f8fdd","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/58f8fdd5396817b775d2c69af9a6322ac7a84e5a","revision_info":"GitHub Revision: [`58f8fdd`](https://github.com/lowrisc/opentitan/tree/58f8fdd5396817b775d2c69af9a6322ac7a84e5a)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-07-10T15:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":4.0,"sim_time":11337.940266000001,"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"0.rstmgr_cnsty_chk_test.84647224662756122035009795813713493022930020343011452187082976045904921507438","seed":84647224662756122035009795813713493022930020343011452187082976045904921507438,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/0.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1752194117 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1769634117 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1787074117 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1804514117 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"2.rstmgr_cnsty_chk_test.98770486874298129703490779739058288029715539877886482269392170892169581009986","seed":98770486874298129703490779739058288029715539877886482269392170892169581009986,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/2.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1752190845 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1769630845 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1787070845 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1804510845 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":8,"total":10,"percent":80.0}