{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"41d86cc59c8c62237e3c582490eb8bb9462c9a07","commit_short":"41d86cc","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/41d86cc59c8c62237e3c582490eb8bb9462c9a07","revision_info":"GitHub Revision: [`41d86cc`](https://github.com/lowrisc/opentitan/tree/41d86cc59c8c62237e3c582490eb8bb9462c9a07)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-07T15:00:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":4.02,"sim_time":9328.869239,"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"5.rstmgr_cnsty_chk_test.111035026725970378287568313390325314239539951007585145774452288481759264948260","seed":111035026725970378287568313390325314239539951007585145774452288481759264948260,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/5.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1816312467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1834392467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1852472467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1870552467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"9.rstmgr_cnsty_chk_test.59159089268295499667991828849749401822368065973125504961726554000782396630046","seed":59159089268295499667991828849749401822368065973125504961726554000782396630046,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1896456136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1915336136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1934216136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1953096136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":8,"total":10,"percent":80.0}