{"block":{"name":"uart","variant":null,"commit":"41d86cc59c8c62237e3c582490eb8bb9462c9a07","commit_short":"41d86cc","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/41d86cc59c8c62237e3c582490eb8bb9462c9a07","revision_info":"GitHub Revision: [`41d86cc`](https://github.com/lowrisc/opentitan/tree/41d86cc59c8c62237e3c582490eb8bb9462c9a07)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-08-07T15:00:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":22.0,"sim_time":6277.605159,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":2.0,"sim_time":93.79529,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":12.46973,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":4.0,"sim_time":1199.180666,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":2.0,"sim_time":87.814452,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":42.295093,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":2.0,"sim_time":12.46973,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":87.814452,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":181.0,"sim_time":113819.909051,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":22.0,"sim_time":6277.605159,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":181.0,"sim_time":113819.909051,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":774.0,"sim_time":573530.4257489999,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":91.0,"sim_time":70330.016859,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":181.0,"sim_time":113819.909051,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":774.0,"sim_time":573530.4257489999,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":154.0,"sim_time":191610.282058,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":96.0,"sim_time":114931.007395,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":370.0,"sim_time":179186.161446,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"rx_frame_err":{"tests":{"uart_intr":{"max_time":774.0,"sim_time":573530.4257489999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":774.0,"sim_time":573530.4257489999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":774.0,"sim_time":573530.4257489999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":553.0,"sim_time":20733.959964,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":24.0,"sim_time":13048.563853,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":24.0,"sim_time":13048.563853,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":43.0,"sim_time":135441.526764,"passed":2,"total":10,"percent":20.0}},"passed":2,"total":10,"percent":20.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":38.0,"sim_time":30563.991631999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":39.0,"sim_time":12144.249311000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":24.0,"sim_time":4702.880665,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":997.0,"sim_time":138189.55274900002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":1146.0,"sim_time":393446.04532200005,"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":2.0,"sim_time":70.700256,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":2.0,"sim_time":13.646037,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":243.06289900000002,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":3.0,"sim_time":243.06289900000002,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":2.0,"sim_time":93.79529,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":12.46973,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":87.814452,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":107.11483100000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":2.0,"sim_time":93.79529,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":2.0,"sim_time":12.46973,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":2.0,"sim_time":87.814452,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":2.0,"sim_time":107.11483100000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":386,"total":397,"percent":97.22921914357683},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":2.0,"sim_time":511.10274200000003,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":3.0,"sim_time":343.18156300000004,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":3.0,"sim_time":343.18156300000004,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":70.0,"sim_time":9297.763363,"passed":18,"total":20,"percent":90.0}},"passed":18,"total":20,"percent":90.0}},"passed":18,"total":20,"percent":90.0}},"coverage":{"code":{"block":99.08,"line_statement":99.52,"branch":98.34,"condition_expression":null,"toggle":73.08,"fsm":100.0},"assertion":98.85,"functional":90.69},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.5101172536272880232191396558796414483777922438704374857418037802010005104568","seed":5101172536272880232191396558796414483777922438704374857418037802010005104568,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 17649602165 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 17649642165 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (129 [0x81] vs 249 [0xf9]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 17649722165 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 17649842165 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (129 [0x81] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.5159399629930427942764095736755747775418330770420846787239251726881401938157","seed":5159399629930427942764095736755747775418330770420846787239251726881401938157,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 777211199 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 777221300 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 777241502 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 777251603 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.96679745041497539435189307197235211345657487756766689347963706496691038296967","seed":96679745041497539435189307197235211345657487756766689347963706496691038296967,"line":91,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 59035846764 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 59412286764 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 59412286764 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 59412286764 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all","qual_name":"4.uart_stress_all.101324946249107811204641642126762300572787301991740977783308932779975210239989","seed":101324946249107811204641642126762300572787301991740977783308932779975210239989,"line":102,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 125876390774 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 125876618049 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 125876708959 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 125876936234 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 124 [0x7c]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.109859876927269227455092620824961662967815689177036454558075945052316955382989","seed":109859876927269227455092620824961662967815689177036454558075945052316955382989,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 137463973 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 137474282 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 229492416 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 229492416 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.52028306454120996712409833215590831552888559505530352690521967981907550851802","seed":52028306454120996712409833215590831552888559505530352690521967981907550851802,"line":104,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 393109259044 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 393109279877 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 393109321543 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 393109342376 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"6.uart_stress_all.34958399675288345516237423040689440300575799529621231985330670054334797658176","seed":34958399675288345516237423040689440300575799529621231985330670054334797658176,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5614938425 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5615020057 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (201 [0xc9] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 5615060873 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5615244545 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (201 [0xc9] vs 63 [0x3f]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.114459386759267420489222546697172408354380071132223256532765154065189072229384","seed":114459386759267420489222546697172408354380071132223256532765154065189072229384,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 10904346455 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10904361380 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (161 [0xa1] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 10927689155 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 10927719005 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}],"UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"1.uart_stress_all_with_rand_reset.72465567174010604919298261904981710962327268042521193546445647120410852949382","seed":72465567174010604919298261904981710962327268042521193546445647120410852949382,"line":186,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 5758079867 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 5758207529 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 7/10\n"]}],"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.27415209383656525972629146328132142409582099324041146103526511636217001088708","seed":27415209383656525972629146328132142409582099324041146103526511636217001088708,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @   8719892 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 103538100 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0\n","UVM_ERROR @ 103653886 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 103685464 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.60560590581608275046016282504971137080989345667052287343264746302671005739640","seed":60560590581608275046016282504971137080989345667052287343264746302671005739640,"line":90,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 24381589426 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 24381589426 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 24389444722 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 24389444722 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.43117195963187054574351751424808882466980554435834974452213398155672214240227","seed":43117195963187054574351751424808882466980554435834974452213398155672214240227,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  15056872 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  15698958 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  16214732 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  16719980 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"18.uart_stress_all_with_rand_reset.24894326618925994105576849071952174402406866445771525193166424695322551240180","seed":24894326618925994105576849071952174402406866445771525193166424695322551240180,"line":97,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 657440796 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 657956570 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 658251298 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 663230096 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}]}},"passed":440,"total":453,"percent":97.13024282560707}