{"block":{"name":"chip","variant":null,"commit":"d3fa90dfeea2cf0415ca04e02edf2549dba9f6e4","commit_short":"d3fa90d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d3fa90dfeea2cf0415ca04e02edf2549dba9f6e4","revision_info":"GitHub Revision: [`d3fa90d`](https://github.com/lowrisc/opentitan/tree/d3fa90dfeea2cf0415ca04e02edf2549dba9f6e4)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-14T15:00:29Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":18.592164162546396,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":18.592164162546396,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"chip_sw_uart_rand_baudrate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":30.18372672609985,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":21.65159262623638,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":453.41,"sim_time":286.038275,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":453.41,"sim_time":286.038275,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":453.41,"sim_time":286.038275,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_example_tests":{"tests":{"chip_sw_example_rom":{"max_time":54.44,"sim_time":10.320001,"passed":0,"total":3,"percent":0.0},"chip_sw_example_manufacturer":{"max_time":13.175125871784985,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_example_concurrency":{"max_time":262.99,"sim_time":168.756,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest_signed":{"max_time":12.343600946478546,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":12,"percent":25.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":10.98,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":12.09,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":12.09,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":36.87,"sim_time":68.071808,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":56,"total":101,"percent":55.445544554455445},"V2":{"testpoints":{"chip_sw_spi_device_flash_mode":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":19.739947456866503,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":3600.18688312266,"sim_time":0.0,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":448.4,"sim_time":364.113,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":16.36738219484687,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":14.79530216101557,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":14.32948349788785,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":13.122260194271803,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":3.82,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":3.82,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":15.34733933582902,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":18.202268863096833,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":17.785510098561645,"sim_time":0.0,"passed":0,"total":6,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":17.785510098561645,"sim_time":0.0,"passed":0,"total":6,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":167.18,"sim_time":131.626,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":166.41,"sim_time":132.418,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":481.66,"sim_time":309.799,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":11.778188752010465,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":13.910596786998212,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":112.42,"sim_time":122.76,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":387.79,"sim_time":266.811,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":709.34,"sim_time":607.346,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":709.34,"sim_time":607.346,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":597.19,"sim_time":386.663,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":304.74,"sim_time":182.515,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":304.74,"sim_time":182.515,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":467.27,"sim_time":2310.368,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":263.78,"sim_time":164.352,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":425.64,"sim_time":245.01,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"max_time":270.87,"sim_time":165.816,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":280.04,"sim_time":178.084,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"max_time":266.51,"sim_time":163.946,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":276.63,"sim_time":185.408,"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":303.27,"sim_time":185.248,"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":302.17,"sim_time":185.328,"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":287.93,"sim_time":185.392,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":12,"percent":0.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":60.72,"sim_time":10.180001,"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc_jitter_en":{"max_time":64.42,"sim_time":10.400001,"passed":0,"total":3,"percent":0.0},"chip_sw_hmac_enc_jitter_en":{"max_time":63.99,"sim_time":10.380001,"passed":0,"total":3,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":65.07,"sim_time":10.300001,"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":56.7,"sim_time":10.340001,"passed":0,"total":3,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":13.834178528748453,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter":{"max_time":292.8,"sim_time":161.333,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":21,"percent":14.285714285714286},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":583.95,"sim_time":1962.7768600000002,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":55.14,"sim_time":10.120001,"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":62.00000000000001,"sim_time":10.120001,"passed":0,"total":3,"percent":0.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":59.18,"sim_time":10.100001,"passed":0,"total":3,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq":{"max_time":53.7,"sim_time":10.140001,"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":60.21,"sim_time":10.160001,"passed":0,"total":3,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":45.87,"sim_time":10.200001,"passed":0,"total":3,"percent":0.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":54.4,"sim_time":10.220001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":24,"percent":12.5},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":18.49261718802154,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":14.071650856174529,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":25.557516059838235,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1623.58,"sim_time":943.541,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":162.35,"sim_time":118.448,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sleep_all_reset_reqs":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":304.74,"sim_time":182.515,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":14.455887614749372,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":162.35,"sim_time":118.448,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":22.659176881425083,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":19.613221491687,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":25.359783648513258,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":14.804937624372542,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":17.51296680327505,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1623.58,"sim_time":943.541,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":481.66,"sim_time":309.799,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":506.91999999999996,"sim_time":411.856,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":430.51,"sim_time":305.276,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":538.7,"sim_time":331.203,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":278.15,"sim_time":163.64,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1623.58,"sim_time":943.541,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":14.77100601606071,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":14.242090979591012,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1623.58,"sim_time":943.541,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":17.010627835989,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":538.7,"sim_time":331.203,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":586.72,"sim_time":454.954,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":13.73915305081755,"sim_time":0.0,"passed":0,"total":90,"percent":0.0}},"passed":0,"total":90,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":17.293660880066454,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":25.38598665781319,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":19.768871168605983,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":15.54989113099873,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":14.242090979591012,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_lc_ctrl_otp_hw_cfg":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg":{"max_time":13.68710670992732,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_dpe_key_derivation_prod":{"max_time":536.35,"sim_time":351.292581,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":20.831462102010846,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":21.75161405466497,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":23.689170232973993,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":22.891746311448514,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":573.29,"sim_time":351.420094,"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":258.39,"sim_time":157.24,"passed":0,"total":3,"percent":0.0},"chip_sw_sram_ctrl_execution_main":{"max_time":14.163248381577432,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_prim_tl_access":{"max_time":130.13,"sim_time":117.768,"passed":0,"total":3,"percent":0.0},"chip_rv_dm_lc_disabled":{"max_time":112.42,"sim_time":122.76,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":42,"percent":7.142857142857143},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":295.8,"sim_time":173.132,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":64.42,"sim_time":10.400001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_aes_gcm":{"tests":{"chip_sw_aes_enc":{"max_time":295.8,"sim_time":173.132,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":64.42,"sim_time":10.400001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":274.44,"sim_time":164.418,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":270.87,"sim_time":165.816,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":285.61,"sim_time":173.703,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":63.99,"sim_time":10.380001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":280.04,"sim_time":178.084,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":241.82999999999998,"sim_time":167.332,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":338.17,"sim_time":188.834,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":56.7,"sim_time":10.340001,"passed":0,"total":3,"percent":0.0}},"passed":6,"total":9,"percent":66.66666666666667},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_dpe_key_derivation":{"max_time":573.29,"sim_time":351.420094,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":19.815207458101213,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":340.61,"sim_time":211.977,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":266.51,"sim_time":163.946,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":2514.43,"sim_time":2224.125,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":2514.43,"sim_time":2224.125,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":17.34195260796696,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":296.14,"sim_time":176.051,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":2417.11,"sim_time":972.571,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"tests":{"chip_sw_keymgr_dpe_key_derivation":{"max_time":573.29,"sim_time":351.420094,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":65.07,"sim_time":10.300001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":5122.78,"sim_time":1492.286,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":60.72,"sim_time":10.180001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":425.64,"sim_time":245.01,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":425.64,"sim_time":245.01,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":425.64,"sim_time":245.01,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":563.32,"sim_time":280.67,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":258.39,"sim_time":157.24,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":258.39,"sim_time":157.24,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":604.53,"sim_time":358.422936,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":13.834178528748453,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":14.163248381577432,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1623.58,"sim_time":943.541,"passed":0,"total":100,"percent":0.0},"chip_sw_data_integrity_escalation":{"max_time":17.785510098561645,"sim_time":0.0,"passed":0,"total":6,"percent":0.0}},"passed":0,"total":106,"percent":0.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":563.32,"sim_time":280.67,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":573.29,"sim_time":351.420094,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":604.53,"sim_time":358.422936,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":286.88,"sim_time":178.532971,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":563.32,"sim_time":280.67,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":573.29,"sim_time":351.420094,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":604.53,"sim_time":358.422936,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":286.88,"sim_time":178.532971,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":15.689383602701128,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_hw_cfg":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg":{"max_time":13.68710670992732,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":20.831462102010846,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":21.75161405466497,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":23.689170232973993,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":22.891746311448514,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":18.026116161607206,"sim_time":0.0,"passed":0,"total":15,"percent":0.0},"chip_prim_tl_access":{"max_time":130.13,"sim_time":117.768,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":30,"percent":0.0},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":130.13,"sim_time":117.768,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_nvm_cnt":{"tests":{"chip_sw_otp_ctrl_nvm_cnt":{"max_time":10.730532901361585,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_sw_parts":{"tests":{"chip_sw_otp_ctrl_sw_parts":{"max_time":11.889988738112152,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":18.49261718802154,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":60.72,"sim_time":10.180001,"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc_jitter_en":{"max_time":64.42,"sim_time":10.400001,"passed":0,"total":3,"percent":0.0},"chip_sw_hmac_enc_jitter_en":{"max_time":63.99,"sim_time":10.380001,"passed":0,"total":3,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":65.07,"sim_time":10.300001,"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":56.7,"sim_time":10.340001,"passed":0,"total":3,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":13.834178528748453,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter":{"max_time":292.8,"sim_time":161.333,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":21,"percent":14.285714285714286},"chip_sw_soc_proxy_external_reset_requests":{"tests":{"chip_sw_soc_proxy_smoketest":{"max_time":244.55999999999997,"sim_time":156.224,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_soc_proxy_external_irqs":{"tests":{"chip_sw_soc_proxy_smoketest":{"max_time":244.55999999999997,"sim_time":156.224,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_soc_proxy_external_wakeup_requests":{"tests":{"chip_sw_soc_proxy_external_wakeup":{"max_time":250.23999999999998,"sim_time":157.901,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_soc_proxy_gpios":{"tests":{"chip_sw_soc_proxy_gpios":{"max_time":262.99,"sim_time":180.46991599999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":533.27,"sim_time":269.337,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":388.35,"sim_time":198.25,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":331.6,"sim_time":179.995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":286.88,"sim_time":178.532971,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":506.91999999999996,"sim_time":411.856,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":506.91999999999996,"sim_time":411.856,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_smoketest":{"tests":{"chip_sw_aes_smoketest":{"max_time":273.64,"sim_time":173.124,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":304.0,"sim_time":182.243,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":277.16,"sim_time":162.133,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":270.37,"sim_time":164.11,"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":325.97,"sim_time":192.739161,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":314.07,"sim_time":194.768,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":320.86,"sim_time":185.52,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":391.11,"sim_time":219.386,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_smoketest":{"max_time":290.26,"sim_time":165.821,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":296.26,"sim_time":163.948,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":385.94,"sim_time":266.835,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":276.41,"sim_time":160.92,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":293.31,"sim_time":164.585,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":310.99,"sim_time":175.104,"passed":3,"total":3,"percent":100.0}},"passed":42,"total":42,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":13.201961630955338,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_signed":{"tests":{"chip_sw_uart_smoketest_signed":{"max_time":12.343600946478546,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":19.739947456866503,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_secure_boot":{"tests":{"base_rom_e2e_smoke":{"max_time":15.334186308085918,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":236.71,"sim_time":165.16,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":187.62,"sim_time":174.488,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":205.6,"sim_time":168.92,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":239.4,"sim_time":171.608,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":16.336287417449057,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_rv_dm_lc_disabled":{"max_time":112.42,"sim_time":122.76,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":23.621608421206474,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":21.611494957469404,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":16.706190234981477,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_rma":{"max_time":18.312073756940663,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":16.336287417449057,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":604.3,"sim_time":549.832,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":404.33,"sim_time":372.728,"passed":0,"total":3,"percent":0.0},"rom_volatile_raw_unlock":{"max_time":84.35779192857444,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":9,"percent":0.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":87.0657147327438,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":12.97938276361674,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":23.001013127155602,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":209.73,"sim_time":118.068,"passed":0,"total":30,"percent":0.0}},"passed":0,"total":30,"percent":0.0},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":209.73,"sim_time":118.068,"passed":0,"total":30,"percent":0.0}},"passed":0,"total":30,"percent":0.0},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":12.09,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_same_csr_outstanding":{"max_time":14.78,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":12.09,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_same_csr_outstanding":{"max_time":14.78,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":322.75,"sim_time":498.269078,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":14.15,"sim_time":12.844181,"passed":50,"total":50,"percent":100.0},"xbar_smoke_large_delays":{"max_time":401.2,"sim_time":2487.387992,"passed":50,"total":50,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":477.41,"sim_time":2164.586362,"passed":50,"total":50,"percent":100.0},"xbar_random_zero_delays":{"max_time":137.17,"sim_time":82.968003,"passed":50,"total":50,"percent":100.0},"xbar_random_large_delays":{"max_time":1794.78,"sim_time":13313.977261,"passed":50,"total":50,"percent":100.0},"xbar_random_slow_rsp":{"max_time":2936.1,"sim_time":14310.302083,"passed":50,"total":50,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":169.49,"sim_time":209.300891,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":213.17,"sim_time":258.00901500000003,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":300.88,"sim_time":570.4899740000001,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":213.17,"sim_time":258.00901500000003,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":469.8,"sim_time":879.3603850000001,"passed":50,"total":50,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":3600.187243984081,"sim_time":0.0,"passed":40,"total":50,"percent":80.0}},"passed":90,"total":100,"percent":90.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":225.91,"sim_time":412.74931599999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":2022.74,"sim_time":3210.120423,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_error":{"max_time":2334.03,"sim_time":4250.560111,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":3600.441440643742,"sim_time":0.0,"passed":47,"total":50,"percent":94.0},"xbar_stress_all_with_reset_error":{"max_time":3472.7,"sim_time":6279.249485,"passed":50,"total":50,"percent":100.0}},"passed":97,"total":100,"percent":97.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":12.70819110237062,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":12.823555767536163,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":12.818113286048174,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":62.23897334001959,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":9.570727995596826,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":9.964281119406223,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":12.97349976375699,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":10.47076555620879,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":71.59879422932863,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":11.059772888198495,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":12.169771269895136,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":11.948000879958272,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":11.276484766975045,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":170.4424476539716,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":12.94094300456345,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":12.507989658974111,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":11.666718690656126,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":12.164968491531909,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":89.60972404759377,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":12.992262233048677,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":13.796602912247181,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":11.474058639258146,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":12.673851850442588,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":127.15162339061497,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":12.506149561144412,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":10.648508201353252,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":11.124031507410109,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":10.9891456682235,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":29.68596040084958,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":10.374924064613879,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":12.632550719194114,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":12.641054050065577,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":11.501785803586245,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":92.88552859332412,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_dev":{"max_time":12.750982507131994,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod":{"max_time":11.883635678328574,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod_end":{"max_time":12.160360980778933,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_rma":{"max_time":13.048762079328299,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":12.436349616385996,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":12.450928063131869,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":11.88104543555528,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":9,"percent":0.0},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":12.61073763947934,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0}},"passed":976,"total":1561,"percent":62.524023062139655},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":349.65,"sim_time":196.16797,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":201.29,"sim_time":137.0925,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"V3":{"testpoints":{"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":11.578077578917146,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":11.592490232549608,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":12.025482560507953,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":14.957472270354629,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1623.58,"sim_time":943.541,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":18.10480530373752,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":287.35,"sim_time":177.024,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":12.764853166416287,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":30.913035748526454,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":11.578077578917146,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":11.592490232549608,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":12.025482560507953,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":11.588408659212291,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":11.347388252615929,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":12.632644092664123,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":86.67501221783459,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0}},"passed":0,"total":120,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":59.9,"sim_time":10.280001,"passed":0,"total":3,"percent":0.0},"chip_sw_aes_gcm":{"max_time":394.64,"sim_time":203.631,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_kat_test":{"max_time":286.67,"sim_time":163.578,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":245.21000000000004,"sim_time":161.174,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_0":{"max_time":602.34,"sim_time":327.558,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":537.93,"sim_time":300.595,"passed":3,"total":3,"percent":100.0},"chip_sw_dma_inline_hashing":{"max_time":333.99,"sim_time":207.439,"passed":3,"total":3,"percent":100.0},"chip_sw_dma_abort":{"max_time":348.3,"sim_time":211.779,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn":{"max_time":85.503483382985,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_test_unlocked0_sw":{"max_time":91.62465868052095,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_dev_otbn":{"max_time":11.088412242941558,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_dev_sw":{"max_time":12.568047363311052,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_otbn":{"max_time":12.293133543804288,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_sw":{"max_time":12.30185557436198,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_end_otbn":{"max_time":12.994551431387663,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_end_sw":{"max_time":11.394153278321028,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_rma_otbn":{"max_time":12.680396943353117,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_sigverify_mod_exp_rma_sw":{"max_time":12.705219089984894,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_entropy_src_smoketest":{"max_time":324.59,"sim_time":190.651,"passed":3,"total":3,"percent":100.0},"chip_sw_mbx_smoketest":{"max_time":650.11,"sim_time":414.685688,"passed":3,"total":3,"percent":100.0}},"passed":24,"total":60,"percent":40.0}},"passed":24,"total":60,"percent":40.0}},"coverage":{"code":{"block":null,"line_statement":67.15,"branch":77.13,"condition_expression":71.07,"toggle":45.64,"fsm":57.14},"assertion":76.58,"functional":84.95},"cov_report_page":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode":[{"name":"chip_csr_bit_bash","qual_name":"0.chip_csr_bit_bash.928118192639174722949212863779225088040634843403858101519910634551781733982","seed":928118192639174722949212863779225088040634843403858101519910634551781733982,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"0.chip_csr_aliasing.56711794044761012469441114936717660050895608381221058163787241502207978980027","seed":56711794044761012469441114936717660050895608381221058163787241502207978980027,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"0.chip_same_csr_outstanding.75146624512704759614603958112128896618201240289258800928021952597178250901132","seed":75146624512704759614603958112128896618201240289258800928021952597178250901132,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_bit_bash","qual_name":"1.chip_csr_bit_bash.29681036717133911634116049690823207699073998628272853187196357377920592631037","seed":29681036717133911634116049690823207699073998628272853187196357377920592631037,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"1.chip_csr_aliasing.60374123331773182025857385823349997056377182458821580889191445984964519990011","seed":60374123331773182025857385823349997056377182458821580889191445984964519990011,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"1.chip_same_csr_outstanding.31397070904003662359192129419521836266456774311870634058287740893835141662977","seed":31397070904003662359192129419521836266456774311870634058287740893835141662977,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_bit_bash","qual_name":"2.chip_csr_bit_bash.46930787032319138970591946662747424525892962107751738824080394146034950724219","seed":46930787032319138970591946662747424525892962107751738824080394146034950724219,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"2.chip_csr_aliasing.108569670128499777706952534965038366455949632522101175684740109428347343048330","seed":108569670128499777706952534965038366455949632522101175684740109428347343048330,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"2.chip_same_csr_outstanding.67874082965729809698505516351356623520413589408853019093302002954059393034120","seed":67874082965729809698505516351356623520413589408853019093302002954059393034120,"line":142,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode":[{"name":"chip_sw_example_rom","qual_name":"0.chip_sw_example_rom.52474920942147798796832689721790767923693332778265191126294305402941499721882","seed":52474920942147798796832689721790767923693332778265191126294305402941499721882,"line":290,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_example_rom","qual_name":"1.chip_sw_example_rom.42310916846097244811408109851336936215018335337640877172343486610380647211570","seed":42310916846097244811408109851336936215018335337640877172343486610380647211570,"line":290,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_example_rom","qual_name":"2.chip_sw_example_rom.49309991355973623605535417683440260939533931544988566908847416162623761742673","seed":49309991355973623605535417683440260939533931544988566908847416162623761742673,"line":290,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_example_manufacturer","qual_name":"0.chip_sw_example_manufacturer.26854749056946626871759909203546894971228448729724913699174896679386880374630","seed":26854749056946626871759909203546894971228448729724913699174896679386880374630,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.893s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"0.chip_sw_data_integrity_escalation.51817045336683948483984239817128479883344533953831952081576764274548585188493","seed":51817045336683948483984239817128479883344533953831952081576764274548585188493,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.405s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.74368052640856870927812747530489297354178733065943375655035642135365534922397","seed":74368052640856870927812747530489297354178733065943375655035642135365534922397,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.333s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"0.chip_sw_sleep_pin_retention.112726388072690569034780142189448058008267987638290327931041982401985280417682","seed":112726388072690569034780142189448058008267987638290327931041982401985280417682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.888s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"0.chip_sw_uart_tx_rx.109492775599840091569579794230949615523507990925459228466271001364002702448126","seed":109492775599840091569579794230949615523507990925459228466271001364002702448126,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.786s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"0.chip_sw_uart_tx_rx_bootstrap.12332456468862999911323278707012809292331326478526982413452420669179549052385","seed":12332456468862999911323278707012809292331326478526982413452420669179549052385,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.270s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"0.chip_sw_inject_scramble_seed.65468012828936371370174435919635959083906471899161556055042193271035138626755","seed":65468012828936371370174435919635959083906471899161556055042193271035138626755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.382s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"0.chip_sw_exit_test_unlocked_bootstrap.37992332815619823232716015798886070383958173617053226302757949596269614575563","seed":37992332815619823232716015798886070383958173617053226302757949596269614575563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.552s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"0.chip_sw_uart_rand_baudrate.65859442429867579457920017473550379118002066039162130999802045591550385462615","seed":65859442429867579457920017473550379118002066039162130999802045591550385462615,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.833s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"0.chip_sw_uart_tx_rx_alt_clk_freq.54491365685411031996073692690445803547515822479247196220619780886559992782925","seed":54491365685411031996073692690445803547515822479247196220619780886559992782925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.875s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"0.chip_sw_i2c_host_tx_rx.96817771267462253808297252619411563097716253918944214211421669463450799431529","seed":96817771267462253808297252619411563097716253918944214211421669463450799431529,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.324s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"0.chip_sw_i2c_device_tx_rx.111767548310928935763741319742302633619128835909534490550174569794522560217801","seed":111767548310928935763741319742302633619128835909534490550174569794522560217801,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.403s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"0.chip_sw_spi_device_tpm.11856307132015775038429214430063026688284698286042698835689040278804926489322","seed":11856307132015775038429214430063026688284698286042698835689040278804926489322,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.123s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"0.chip_sw_spi_host_tx_rx.40907930887319601338351114963736207955467789179916303879167645855701107254188","seed":40907930887319601338351114963736207955467789179916303879167645855701107254188,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.131s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"0.chip_sw_lc_ctrl_otp_hw_cfg.105289769739672629693212041291517019738174128456746138980091965501561325361558","seed":105289769739672629693212041291517019738174128456746138980091965501561325361558,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1553966) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.114271615281597955633761533403002566939209482641254348275661205203032554761979","seed":114271615281597955633761533403002566939209482641254348275661205203032554761979,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.383s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"0.chip_sw_otp_ctrl_lc_signals_dev.9914049115302586760169524519138131067833136365053678469594476738223522403125","seed":9914049115302586760169524519138131067833136365053678469594476738223522403125,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.897s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"0.chip_sw_otp_ctrl_lc_signals_prod.72075796311046889369462778375518278980856296907319917512137063591899352530435","seed":72075796311046889369462778375518278980856296907319917512137063591899352530435,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.394s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.52424598407807553764975532399549255985297687980752319853487534134389050112932","seed":52424598407807553764975532399549255985297687980752319853487534134389050112932,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.394s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"0.chip_sw_otp_ctrl_vendor_test_csr_access.53952259785162997893964842192837595445703398647317684778520628831361723438644","seed":53952259785162997893964842192837595445703398647317684778520628831361723438644,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.181s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_nvm_cnt","qual_name":"0.chip_sw_otp_ctrl_nvm_cnt.104687207473359572732407921404202436908665904091023577329337969166536453986037","seed":104687207473359572732407921404202436908665904091023577329337969166536453986037,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_nvm_cnt/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_sw_parts","qual_name":"0.chip_sw_otp_ctrl_sw_parts.5851382297334046070821937758728849420924030689226774951979598407222932124938","seed":5851382297334046070821937758728849420924030689226774951979598407222932124938,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_sw_parts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"0.chip_sw_lc_ctrl_transition.49300248404152895938775372313986379081293042427386002138734195373248372776344","seed":49300248404152895938775372313986379081293042427386002138734195373248372776344,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.641s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.90030471512938777455449696151139962923272941285943632407050298693861662191712","seed":90030471512938777455449696151139962923272941285943632407050298693861662191712,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.795s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.98717066344954293466558649858516024778206019602821575124708593820948887419222","seed":98717066344954293466558649858516024778206019602821575124708593820948887419222,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.131s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"0.chip_sw_lc_walkthrough_prodend.635525089173830091962763563000154027803289899373456672857633714809007415781","seed":635525089173830091962763563000154027803289899373456672857633714809007415781,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.366s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.18489688796212314737687814329741930280986644059364568808362410832751342331392","seed":18489688796212314737687814329741930280986644059364568808362410832751342331392,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.748s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.21104664146610435949393740924788966745810205821689135348881424831559710646347","seed":21104664146610435949393740924788966745810205821689135348881424831559710646347,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.363s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_main_power_glitch_reset.70549131552770121160593900247093524956855891919317809665837086257642151240313","seed":70549131552770121160593900247093524956855891919317809665837086257642151240313,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.957s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.12205714689605607341364819621646276340595643557578560415245284194109862639916","seed":12205714689605607341364819621646276340595643557578560415245284194109862639916,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.407s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.71413755670140170253968328027751455937771657610599834676504980719070778011980","seed":71413755670140170253968328027751455937771657610599834676504980719070778011980,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.909s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.15496109284071972337030586770037429777328955532609043967411198755030077037116","seed":15496109284071972337030586770037429777328955532609043967411198755030077037116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.706s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"0.chip_sw_pwrmgr_sleep_disabled.43520950611584910563208740511047182527457313255973850867413667126619824349298","seed":43520950611584910563208740511047182527457313255973850867413667126619824349298,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.367s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"0.chip_sw_pwrmgr_wdog_reset.25685018674778321720349602387256756603286427643810879550383808518909893190925","seed":25685018674778321720349602387256756603286427643810879550383808518909893190925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.324s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.56444163072308008512276443009240464730625937158763818990893042573873711829396","seed":56444163072308008512276443009240464730625937158763818990893042573873711829396,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["Another command (pid=1357117) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"0.chip_sw_alert_handler_escalation.11564734532593209019325088648757120276899452536075634442783120306496741281867","seed":11564734532593209019325088648757120276899452536075634442783120306496741281867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.267s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.66835797004094973024209958909261039914482121788852054620398122569383020361349","seed":66835797004094973024209958909261039914482121788852054620398122569383020361349,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.686s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.81673100598437546836789907535215809923811542716276293385294224371015186144140","seed":81673100598437546836789907535215809923811542716276293385294224371015186144140,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=271042) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.88479579639369422582036556549997445052727576082397192745291315884343112310280","seed":88479579639369422582036556549997445052727576082397192745291315884343112310280,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.788s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"0.chip_sw_alert_handler_lpg_clkoff.94357798211253956898760263812137489603670904311752044923357762307848247912358","seed":94357798211253956898760263812137489603670904311752044923357762307848247912358,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 8.590s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"0.chip_sw_alert_handler_lpg_reset_toggle.72356230910289652301854283891446425583935074892122760407215904692359550996879","seed":72356230910289652301854283891446425583935074892122760407215904692359550996879,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.041s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.55508080726706415290684198405666168098778764950617570327054425988526436581704","seed":55508080726706415290684198405666168098778764950617570327054425988526436581704,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.246s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.46703560123136845541401587779151934876378804804127717762411921355119381621274","seed":46703560123136845541401587779151934876378804804127717762411921355119381621274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.342s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"0.chip_sw_kmac_app_rom.37269078461575799248735047503845842524358296260342482030075207163525215774973","seed":37269078461575799248735047503845842524358296260342482030075207163525215774973,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1516940) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=1516763) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=1519301) is running. Waiting for it to complete on the server (server_pid=207925)...\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en.101466024987608518721540324285781651619545196557885647837706117265752671677300","seed":101466024987608518721540324285781651619545196557885647837706117265752671677300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1741009) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"0.chip_sw_sram_ctrl_execution_main.2960205935409569561533157956856911291785416183045553608191773921469881200011","seed":2960205935409569561533157956856911291785416183045553608191773921469881200011,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.370s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_coremark","qual_name":"0.chip_sw_coremark.97693788992275346228841112521931371282445507505889900852522563917098771974809","seed":97693788992275346228841112521931371282445507505889900852522563917098771974809,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_coremark/latest/run.log","log_context":["---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.54582089214699720321835239084216046392576788195878747160537658152875762254541","seed":54582089214699720321835239084216046392576788195878747160537658152875762254541,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.387s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.13290173937248368507347692012793658391063994197287956501495484729163252376768","seed":13290173937248368507347692012793658391063994197287956501495484729163252376768,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.384s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"0.chip_sw_ast_clk_outputs.63904233484669509591099950882166877490749637114674841302907192680265305952011","seed":63904233484669509591099950882166877490749637114674841302907192680265305952011,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.510s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"0.chip_sw_lc_ctrl_program_error.39032697703214798888096672433744645532629377485010879619873679454887755708471","seed":39032697703214798888096672433744645532629377485010879619873679454887755708471,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.381s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.72570578115802885488023910278434373479575103588924803481470964835778611455689","seed":72570578115802885488023910278434373479575103588924803481470964835778611455689,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.81692268024273612843455840793413492860346342740357958302854865879082356775529","seed":81692268024273612843455840793413492860346342740357958302854865879082356775529,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["Another command (pid=1689169) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=1690233) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=1690726) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"0.chip_sw_rv_dm_access_after_escalation_reset.6534685673508555230600415830438734653261676058355316231000251083183674929372","seed":6534685673508555230600415830438734653261676058355316231000251083183674929372,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.811s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"0.chip_sw_power_virus.48067010812182394030006706687081440509022842528463749912641956950527215286376","seed":48067010812182394030006706687081440509022842528463749912641956950527215286376,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.373s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"0.base_rom_e2e_smoke.83720523058853084050029985427785232598698315286610215482519573073879272368611","seed":83720523058853084050029985427785232598698315286610215482519573073879272368611,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 329, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 261, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"0.rom_e2e_smoke.86759485516242277587460693903785173312459025461895857974739040261903505348433","seed":86759485516242277587460693903785173312459025461895857974739040261903505348433,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.97728931788385013405362057092053282740401740182375888985412739737525578544847","seed":97728931788385013405362057092053282740401740182375888985412739737525578544847,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.78219905915100454009256535002356373862772428101903374280655964646201631258573","seed":78219905915100454009256535002356373862772428101903374280655964646201631258573,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.41579061584499381102110894561407556001785071293968503261848079075669906507805","seed":41579061584499381102110894561407556001785071293968503261848079075669906507805,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=207858) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=207919) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=211159) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.79245109188184069489951481378913561548436710971606276666498690742688284303747","seed":79245109188184069489951481378913561548436710971606276666498690742688284303747,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.104804429642497800887591240292461187682377479929936498229578798990962689609734","seed":104804429642497800887591240292461187682377479929936498229578798990962689609734,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.36730172919709655686364956206036957523402182087641989739836901882466844195544","seed":36730172919709655686364956206036957523402182087641989739836901882466844195544,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=390540) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.6676916004713815112521966555618257492143585015427135241051284577092047822502","seed":6676916004713815112521966555618257492143585015427135241051284577092047822502,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.17678718705382794161472140615746646216735809092914144127833042360831030402221","seed":17678718705382794161472140615746646216735809092914144127833042360831030402221,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=207858) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=207919) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.90017517268267013677990578790980739749295991583784433869172392075113645820447","seed":90017517268267013677990578790980739749295991583784433869172392075113645820447,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.51080001779903571293078228692483862243117490510549268975632786796195815129896","seed":51080001779903571293078228692483862243117490510549268975632786796195815129896,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.31547298316822031806715657451470409300586658452940542084329202627556671135870","seed":31547298316822031806715657451470409300586658452940542084329202627556671135870,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=389377) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.59525089669897712432563648870550639876383046324918241893704564433976288363477","seed":59525089669897712432563648870550639876383046324918241893704564433976288363477,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.67896112341709945587951558902445570781745984628292753646931143948751692281133","seed":67896112341709945587951558902445570781745984628292753646931143948751692281133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=239844) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.15911626901768587277572909631997195398698318243527338730060321417010213651033","seed":15911626901768587277572909631997195398698318243527338730060321417010213651033,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=386690) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.52711710622048078514270977592068357476511459098924817049821591980593965313857","seed":52711710622048078514270977592068357476511459098924817049821591980593965313857,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=386936) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.102929318942441054569039556545560998394637390583474951836496775109865269556399","seed":102929318942441054569039556545560998394637390583474951836496775109865269556399,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.46118885363271376319972669129332153609952003930502896573468161679432367815849","seed":46118885363271376319972669129332153609952003930502896573468161679432367815849,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.15934484353644693442587917289320842350598818141805386244277524246777052339309","seed":15934484353644693442587917289320842350598818141805386244277524246777052339309,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=214007) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.113283435864649207771773791731763063542593326884179490571264221475060053855168","seed":113283435864649207771773791731763063542593326884179490571264221475060053855168,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.84589831959970417431544975141157272201369542345662271444904127356286514578009","seed":84589831959970417431544975141157272201369542345662271444904127356286514578009,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=467166) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.99111548026185279861367379456643817528960937767672106188086820457901591852638","seed":99111548026185279861367379456643817528960937767672106188086820457901591852638,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.44474975215205134655102810514561961744407387908277420073176060455945696578233","seed":44474975215205134655102810514561961744407387908277420073176060455945696578233,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=466050) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.7029252841671667191141161669756109066977679464621412140638550872471698375690","seed":7029252841671667191141161669756109066977679464621412140638550872471698375690,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["Another command (pid=208075) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=215037) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=231386) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.91476920452920453763951043878792038464629029930177722863220873659564923383804","seed":91476920452920453763951043878792038464629029930177722863220873659564923383804,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=466710) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.33517999284749382796235866283469540134788096896643162510700176882086599843811","seed":33517999284749382796235866283469540134788096896643162510700176882086599843811,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.77217345143733295306452407051776943448397036669393513599509047991228582772377","seed":77217345143733295306452407051776943448397036669393513599509047991228582772377,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.64740987867873376386818032803753355197796684849721248208028158318367583879458","seed":64740987867873376386818032803753355197796684849721248208028158318367583879458,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.57137978244313720798094300860180587511040843605576154962686681628910707869398","seed":57137978244313720798094300860180587511040843605576154962686681628910707869398,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["Another command (pid=210728) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=207871) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=212527) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.36385970542599467238821470773690218244370674918185234982983084571451663148567","seed":36385970542599467238821470773690218244370674918185234982983084571451663148567,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.89633463523918368254773517480043493793883465500547295726592768525155113145833","seed":89633463523918368254773517480043493793883465500547295726592768525155113145833,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.104966310431004134086354348082803404720620964223985624532911260006338625405768","seed":104966310431004134086354348082803404720620964223985624532911260006338625405768,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.62327865610956869171076695609609856374174712448966105743441217136074359308166","seed":62327865610956869171076695609609856374174712448966105743441217136074359308166,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=470260) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.29245113580477517877247593682037592365461139747438988053659737478709342540300","seed":29245113580477517877247593682037592365461139747438988053659737478709342540300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=210876) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=214007) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=214671) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.98243582358338479087875575590750089720560495623494246064611731491109975316193","seed":98243582358338479087875575590750089720560495623494246064611731491109975316193,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.29229925117479250602183204207492987064196498705392076039837934798556657753322","seed":29229925117479250602183204207492987064196498705392076039837934798556657753322,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.45881622734339650195058558637958528879261488348136473759646674628428680935390","seed":45881622734339650195058558637958528879261488348136473759646674628428680935390,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.345744395524045834273001962476828926616355553760176842723660071329496154696","seed":345744395524045834273001962476828926616355553760176842723660071329496154696,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=386024) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.111997521955702631910774642213797556188565923410431114822457229066722814858332","seed":111997521955702631910774642213797556188565923410431114822457229066722814858332,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.112915983701455988630137056362445209382434953667218023360919485632460620508293","seed":112915983701455988630137056362445209382434953667218023360919485632460620508293,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.57988274901737610593443905533856706278199103584112148731113019166844644106096","seed":57988274901737610593443905533856706278199103584112148731113019166844644106096,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.16075989215895741659818543416713537169226861505034911635850159064399988849286","seed":16075989215895741659818543416713537169226861505034911635850159064399988849286,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.24913405619753011517772756499740317338005296614981446052569143946157796091955","seed":24913405619753011517772756499740317338005296614981446052569143946157796091955,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.25208172189758362896419416273562143199052076783953105127304009732681964290384","seed":25208172189758362896419416273562143199052076783953105127304009732681964290384,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"0.rom_e2e_static_critical.71363289820362428929181016615237373204237577668320829016482416824498344404428","seed":71363289820362428929181016615237373204237577668320829016482416824498344404428,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.88962626823741539379556583158094577225363870459460507592198459228653187275450","seed":88962626823741539379556583158094577225363870459460507592198459228653187275450,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.12786900002803757213382843932758643317555034225302883973767475669840858901917","seed":12786900002803757213382843932758643317555034225302883973767475669840858901917,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_invalid_meas.84544714844891307251287265671746910802874745086510457161691288094919587290426","seed":84544714844891307251287265671746910802874745086510457161691288094919587290426,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.93880347294646637431306321573139889482854485121613841960033160800553886791644","seed":93880347294646637431306321573139889482854485121613841960033160800553886791644,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["Another command (pid=207919) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=211363) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=207871) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.37123329518577011349486033349232574523218394256874990729557804509616143595119","seed":37123329518577011349486033349232574523218394256874990729557804509616143595119,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=215037) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_otbn.48281912645802332743242976374571595343527180801749968067760156398316426392328","seed":48281912645802332743242976374571595343527180801749968067760156398316426392328,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=469992) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_sw.63774830090502898253856579766950739452808862564735907643624690065810915711681","seed":63774830090502898253856579766950739452808862564735907643624690065810915711681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_otbn.114051490521887687305929373310843393197183410481919359276597848020123722171583","seed":114051490521887687305929373310843393197183410481919359276597848020123722171583,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_sw.92303250141380421792425626927930105922082918932709987821473364289925951884553","seed":92303250141380421792425626927930105922082918932709987821473364289925951884553,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_otbn.74929004678702104783997444027121207172747364002653037901238213270585634321405","seed":74929004678702104783997444027121207172747364002653037901238213270585634321405,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_sw.21681854374534152073469673299210527921598025427124989161184099845521122165428","seed":21681854374534152073469673299210527921598025427124989161184099845521122165428,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_otbn.18190141719864244955996861760457725838416174614063921973180245560037415412442","seed":18190141719864244955996861760457725838416174614063921973180245560037415412442,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_sw.109771451206953863041487856274045583914553871819943498995667529820901734625790","seed":109771451206953863041487856274045583914553871819943498995667529820901734625790,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.81414173763479904121424305255253658315218834654205568962825483313654402139274","seed":81414173763479904121424305255253658315218834654205568962825483313654402139274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=215037) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=231386) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.73126306342068533859172000491477518334312227768067360122487815956736893809210","seed":73126306342068533859172000491477518334312227768067360122487815956736893809210,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=224155) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=224203) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=234059) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.72666896035636616782943405599339569601252574456605734530009134898468253657024","seed":72666896035636616782943405599339569601252574456605734530009134898468253657024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=211412) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"0.chip_sw_uart_smoketest_signed.67486436506776896103515558861461212499189562197533385968696841127079535295437","seed":67486436506776896103515558861461212499189562197533385968696841127079535295437,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.53788252273949993204112161190460259611189047068026788234923024498746661436581","seed":53788252273949993204112161190460259611189047068026788234923024498746661436581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.382s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"1.chip_sw_example_manufacturer.68018749285471996381483498350886812401417384062240779358466585221624464908556","seed":68018749285471996381483498350886812401417384062240779358466585221624464908556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.347s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"1.chip_sw_data_integrity_escalation.87777170725096370002283199531972114174206721443828025080535443849189389233754","seed":87777170725096370002283199531972114174206721443828025080535443849189389233754,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.570s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.73638045006429083169695723088475417026139607289032252624662557081086424178681","seed":73638045006429083169695723088475417026139607289032252624662557081086424178681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.165s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"1.chip_sw_sleep_pin_retention.96170376630103942652065028274947531138318184704902213844636966277132197456282","seed":96170376630103942652065028274947531138318184704902213844636966277132197456282,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.298s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"1.chip_sw_uart_tx_rx.56547849908286883008115031723374914146136754027346904970096658631502389773237","seed":56547849908286883008115031723374914146136754027346904970096658631502389773237,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.778s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"1.chip_sw_uart_tx_rx_bootstrap.8668196634506164547077497088907491416372411331433263015384025108310649846885","seed":8668196634506164547077497088907491416372411331433263015384025108310649846885,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.644s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"1.chip_sw_inject_scramble_seed.31844351767517899633780539695907618690522882535864052576344354001489689080093","seed":31844351767517899633780539695907618690522882535864052576344354001489689080093,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.274s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"1.chip_sw_exit_test_unlocked_bootstrap.102464828456316583489645227518173538892137279207280890154163760127811303333713","seed":102464828456316583489645227518173538892137279207280890154163760127811303333713,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.535s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"1.chip_sw_uart_rand_baudrate.66080828491574776978230266179702985855058819483158175155906032317415084870767","seed":66080828491574776978230266179702985855058819483158175155906032317415084870767,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.022s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"1.chip_sw_uart_tx_rx_alt_clk_freq.69143933217151777729859994631204602423459409836259979235892212818741727853162","seed":69143933217151777729859994631204602423459409836259979235892212818741727853162,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 10.117s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"1.chip_sw_i2c_host_tx_rx.68209480917646013834478631016411831774100319068909787840330718969524154029800","seed":68209480917646013834478631016411831774100319068909787840330718969524154029800,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.371s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"1.chip_sw_i2c_device_tx_rx.48407101453314459294799507833964833760222123810163075731061269547307447911509","seed":48407101453314459294799507833964833760222123810163075731061269547307447911509,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.364s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"1.chip_sw_spi_device_tpm.46191201410266319560174198869274755145477383355883218465872929207415402539705","seed":46191201410266319560174198869274755145477383355883218465872929207415402539705,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.390s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"1.chip_sw_spi_host_tx_rx.12852184856958434312405231147668693134621934148488369136685589996362053022475","seed":12852184856958434312405231147668693134621934148488369136685589996362053022475,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.567s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"1.chip_sw_lc_ctrl_otp_hw_cfg.3297729462894880596648001813172296520174492704158388118035442326869964802074","seed":3297729462894880596648001813172296520174492704158388118035442326869964802074,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=2013206) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=2013486) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.46086724828060785775592778978093970154213919602733400891413947394587221988690","seed":46086724828060785775592778978093970154213919602733400891413947394587221988690,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.740s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"1.chip_sw_otp_ctrl_lc_signals_dev.52187961530291604930836157823238246922766245555117805199870576716245531634130","seed":52187961530291604930836157823238246922766245555117805199870576716245531634130,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.799s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"1.chip_sw_otp_ctrl_lc_signals_prod.11786283813660549098212140359396064800728635711163040826336465503556049983021","seed":11786283813660549098212140359396064800728635711163040826336465503556049983021,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.805s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.26621250317270913274844743027452130181432598745180118170025648969654345998865","seed":26621250317270913274844743027452130181432598745180118170025648969654345998865,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.709s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"1.chip_sw_otp_ctrl_vendor_test_csr_access.63382922891756329003559570608951771275042222095714770441398093182677276192585","seed":63382922891756329003559570608951771275042222095714770441398093182677276192585,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.886s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"1.chip_sw_lc_ctrl_transition.16498338353784832051812653890308329324385632498954026566108950002544874391442","seed":16498338353784832051812653890308329324385632498954026566108950002544874391442,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.817s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.76956002146427324461931795832941697842574423917237878548604586806925426772730","seed":76956002146427324461931795832941697842574423917237878548604586806925426772730,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.235s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.11217427916216560577399415242223243039422664336195671802308609102909513583550","seed":11217427916216560577399415242223243039422664336195671802308609102909513583550,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.494s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"1.chip_sw_lc_walkthrough_prodend.97712410773812575684713361565775204096061727294122403760082582234432153907223","seed":97712410773812575684713361565775204096061727294122403760082582234432153907223,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.446s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.52939799139362904115071886945719078601795690992021421490815660391467449764517","seed":52939799139362904115071886945719078601795690992021421490815660391467449764517,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.007s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"1.chip_sw_lc_walkthrough_testunlocks.95411551706781738663237258554088756867261107352336665217139394863955164207507","seed":95411551706781738663237258554088756867261107352336665217139394863955164207507,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.183s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_main_power_glitch_reset.107366335229537832010112865786102179348815939170026570434290307906803621716389","seed":107366335229537832010112865786102179348815939170026570434290307906803621716389,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.544s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.67783389821684374831687195064656730624084506304333966190653395580665810853787","seed":67783389821684374831687195064656730624084506304333966190653395580665810853787,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.217s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.109845530081056267341363213598666547121762620845545455574116732777380657113107","seed":109845530081056267341363213598666547121762620845545455574116732777380657113107,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.703s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.36402625039277081187269224957174788437760520217749667423105317413027426868680","seed":36402625039277081187269224957174788437760520217749667423105317413027426868680,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.393s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"1.chip_sw_pwrmgr_sleep_disabled.39378080633671226447825176884189540168779802244184816960216015134587804744130","seed":39378080633671226447825176884189540168779802244184816960216015134587804744130,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.731s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"1.chip_sw_pwrmgr_wdog_reset.23430673699883396896773229133646884286078588358289299223770949624732485528144","seed":23430673699883396896773229133646884286078588358289299223770949624732485528144,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.226s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.107691095903949218736580718543162625871518767103033439078674631217450569453467","seed":107691095903949218736580718543162625871518767103033439078674631217450569453467,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["Another command (pid=1822329) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"1.chip_sw_alert_handler_escalation.45886767443564506327389996205954505359576510560403945150332674439524514202897","seed":45886767443564506327389996205954505359576510560403945150332674439524514202897,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.340s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.31143297103579552939336269783811409790441535417463970156722076815741469307524","seed":31143297103579552939336269783811409790441535417463970156722076815741469307524,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.242s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.107865551422193761315101919244395041244799614835232472700203007333065053677459","seed":107865551422193761315101919244395041244799614835232472700203007333065053677459,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.65237908203742145997314899129129514952209026256168845256819981680222336500076","seed":65237908203742145997314899129129514952209026256168845256819981680222336500076,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.354s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"1.chip_sw_alert_handler_lpg_clkoff.103559353416676490832191338634718498561143851378649656189265464229688877884786","seed":103559353416676490832191338634718498561143851378649656189265464229688877884786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.753s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"1.chip_sw_alert_handler_lpg_reset_toggle.1173671376293033464941539507842830066289720902022976078933288377525752589181","seed":1173671376293033464941539507842830066289720902022976078933288377525752589181,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.343s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"1.chip_sw_alert_handler_entropy.22010612291112770487079866826175986596938018677035202801539301436631635911507","seed":22010612291112770487079866826175986596938018677035202801539301436631635911507,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.365s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"1.chip_sw_csrng_fuse_en_sw_app_read_test.94989901652920186985203557406568221891185321261323316239519725412979782336833","seed":94989901652920186985203557406568221891185321261323316239519725412979782336833,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.951s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"1.chip_sw_kmac_app_rom.50385967950297257247436259669542453662548918877600616792103859526124708042008","seed":50385967950297257247436259669542453662548918877600616792103859526124708042008,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log","log_context":["INFO: [build_sw_collateral_for_sim.py:207] cquery_cmd = ./bazelisk.sh cquery labels(data, //sw/device/tests:kmac_app_rom_test_sim_dv) union labels(srcs, //sw/device/tests:kmac_app_rom_test_sim_dv) --ui_event_filters=-info --noshow_progress --//hw/top=darjeeling --//hw/top=darjeeling --output=starlark\n","---- STDOUT ----\n","\n","---- STDERR ----\n","Another command (pid=1982658) is running. Waiting for it to complete on the server (server_pid=207925)...\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"1.chip_sw_sram_ctrl_scrambled_access_jitter_en.54238019910672415588155658863925762035200398652037791277656556939075929365512","seed":54238019910672415588155658863925762035200398652037791277656556939075929365512,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=2178345) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"1.chip_sw_sram_ctrl_execution_main.463185471633500363559399532689858266516516829314805474160964763811498562814","seed":463185471633500363559399532689858266516516829314805474160964763811498562814,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.655s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"1.chip_sw_clkmgr_reset_frequency.38593159247029021304458735245667984674261837963948179592469694809093698121116","seed":38593159247029021304458735245667984674261837963948179592469694809093698121116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.571s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"1.chip_sw_clkmgr_sleep_frequency.48148762869076517968022022722666953178461662884287984378270982213980135739775","seed":48148762869076517968022022722666953178461662884287984378270982213980135739775,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.301s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"1.chip_sw_ast_clk_outputs.99107925925879686344576212572321775686280399180015008142416996469873116585039","seed":99107925925879686344576212572321775686280399180015008142416996469873116585039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.767s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"1.chip_sw_lc_ctrl_program_error.17857453857884844136055788303862511801472749906800005409878972277577443926079","seed":17857453857884844136055788303862511801472749906800005409878972277577443926079,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.517s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.98703264371180110899460809608205503458147118451705090544071534237184405959474","seed":98703264371180110899460809608205503458147118451705090544071534237184405959474,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=2127833) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.54477798944761746362609515893165212857841220043347932310154007100649350978020","seed":54477798944761746362609515893165212857841220043347932310154007100649350978020,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=2122710) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"1.chip_sw_rv_dm_access_after_escalation_reset.5530037409381667347298814090380684169066295364274726372702974663421820945772","seed":5530037409381667347298814090380684169066295364274726372702974663421820945772,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.435s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"1.chip_sw_power_virus.27430926161984828734365539242345151569918125333279694110799260304401631374263","seed":27430926161984828734365539242345151569918125333279694110799260304401631374263,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.213s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"1.base_rom_e2e_smoke.4930655285051555651138291672551630624281200861602164373167973144477253007158","seed":4930655285051555651138291672551630624281200861602164373167973144477253007158,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 329, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 261, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"1.rom_e2e_smoke.109038739504733869326377840626081812586247762172801939403808665332109054927106","seed":109038739504733869326377840626081812586247762172801939403808665332109054927106,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"1.rom_e2e_shutdown_exception_c.23805064315837737141255863808102260196509253795909862726012538183856105863345","seed":23805064315837737141255863808102260196509253795909862726012538183856105863345,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"1.rom_e2e_shutdown_output.3453987282116523293161761726351906653591118135022465443660829168271599842651","seed":3453987282116523293161761726351906653591118135022465443660829168271599842651,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=512355) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.47102933734543455587702445247158596921632053511709865578967126528095992249468","seed":47102933734543455587702445247158596921632053511709865578967126528095992249468,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=241619) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=240811) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=242176) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.99624891312674485468777023826081240340511625318752803157441564798745160276353","seed":99624891312674485468777023826081240340511625318752803157441564798745160276353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.61857477201442427232508447071519653399350371611014096838876552183592475858296","seed":61857477201442427232508447071519653399350371611014096838876552183592475858296,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.98414077902945992641219738751951464598510134289192895515635969826260180704819","seed":98414077902945992641219738751951464598510134289192895515635969826260180704819,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.79532203881693132197705602911005173421371749540596811291018965779494318690612","seed":79532203881693132197705602911005173421371749540596811291018965779494318690612,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=391692) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"1.rom_e2e_static_critical.89203202120510395718639885541546237332375346701387744503321584433851544896063","seed":89203202120510395718639885541546237332375346701387744503321584433851544896063,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_meas.42655546834197312731090556029407858104580195927512182048601454344356174084600","seed":42655546834197312731090556029407858104580195927512182048601454344356174084600,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_no_meas.1953784699910298924929387602363133715564424596084321020768102909167581136188","seed":1953784699910298924929387602363133715564424596084321020768102909167581136188,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_invalid_meas.36110185658122897986786156054263970283235913057128187157843319299407707734076","seed":36110185658122897986786156054263970283235913057128187157843319299407707734076,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["Another command (pid=486138) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=500040) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=486181) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.84272437694679050177430455377608409540488253966273620042467460869210422783919","seed":84272437694679050177430455377608409540488253966273620042467460869210422783919,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["Another command (pid=224203) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=234059) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=233497) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.106389966833912831005601517111796812681083683458733011341133022383264930577527","seed":106389966833912831005601517111796812681083683458733011341133022383264930577527,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["Another command (pid=241619) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=240811) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=242176) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_dev_otbn.111770632416935055168579552801448751265759937048992609455438718571408965135559","seed":111770632416935055168579552801448751265759937048992609455438718571408965135559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_dev_sw.101530733527659452868305921412917614502033828426380101515560016868012683714060","seed":101530733527659452868305921412917614502033828426380101515560016868012683714060,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_otbn.110665960968110924213851398828950107814004260030163275540560977852898690324990","seed":110665960968110924213851398828950107814004260030163275540560977852898690324990,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_sw.73897687791569758980139063349663497894523218125942489343768856542758221214023","seed":73897687791569758980139063349663497894523218125942489343768856542758221214023,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_end_otbn.27028555796807698506293096702354999826328366717331870613676065763420663658241","seed":27028555796807698506293096702354999826328366717331870613676065763420663658241,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_end_sw.12492221548729252996670033055866757265771333122750151783168553297810084020660","seed":12492221548729252996670033055866757265771333122750151783168553297810084020660,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_rma_otbn.56773200824147235952192229257045800517177300343986404890873808638922895675492","seed":56773200824147235952192229257045800517177300343986404890873808638922895675492,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_rma_sw.113504063084465018793164909805469284947430671247359215588186518075279907901740","seed":113504063084465018793164909805469284947430671247359215588186518075279907901740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.93239692951684369796074509441264879784504179436574979262836290891047855504570","seed":93239692951684369796074509441264879784504179436574979262836290891047855504570,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=215037) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.108269264401055890259766263012682423957918766179788010249196827350441304738564","seed":108269264401055890259766263012682423957918766179788010249196827350441304738564,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=234059) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=233497) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=216195) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.14784602018820315445029164457420191589122752814400206198639914221209838850361","seed":14784602018820315445029164457420191589122752814400206198639914221209838850361,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=233497) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=224038) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=216195) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"1.chip_sw_uart_smoketest_signed.98536469171181596320877029020850093623045734613104521497309373624431443336390","seed":98536469171181596320877029020850093623045734613104521497309373624431443336390,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.93434924388749152930496361474873271212039099988318913305552038713382488573006","seed":93434924388749152930496361474873271212039099988318913305552038713382488573006,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.419s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"2.chip_sw_example_manufacturer.53147347571848540554603726419163731394790756524022918471044154060904317916812","seed":53147347571848540554603726419163731394790756524022918471044154060904317916812,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.427s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"2.chip_sw_data_integrity_escalation.95872047170072411217064156639802790655562567899297774006640940156238510011468","seed":95872047170072411217064156639802790655562567899297774006640940156238510011468,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.405s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"2.chip_sw_sleep_pin_wake.50520735603391892017472620307968107462503810947278693569138503346732221361793","seed":50520735603391892017472620307968107462503810947278693569138503346732221361793,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.383s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"2.chip_sw_sleep_pin_retention.96264090893846049315601236552065733900121674244538320864063235385081566787702","seed":96264090893846049315601236552065733900121674244538320864063235385081566787702,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.424s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"2.chip_sw_uart_tx_rx.9636921828399745687812923280448825409722767302944109802592419567817437245040","seed":9636921828399745687812923280448825409722767302944109802592419567817437245040,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.825s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"2.chip_sw_uart_tx_rx_bootstrap.42380694115061248101297823301759262866530265935562555890634530710184292043333","seed":42380694115061248101297823301759262866530265935562555890634530710184292043333,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.694s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"2.chip_sw_inject_scramble_seed.67044876857084613166155771787831179414768567834520245371786635586242550059904","seed":67044876857084613166155771787831179414768567834520245371786635586242550059904,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.871s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"2.chip_sw_exit_test_unlocked_bootstrap.8379986660282223151584036202023142441254698418511411311341818578380724292774","seed":8379986660282223151584036202023142441254698418511411311341818578380724292774,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.382s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"2.chip_sw_uart_rand_baudrate.80800064704545558728145422043698098641869529659086671920445064301279756977160","seed":80800064704545558728145422043698098641869529659086671920445064301279756977160,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.335s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"2.chip_sw_uart_tx_rx_alt_clk_freq.99281820240105702206733497135088229252555151526291001176623256451262865246234","seed":99281820240105702206733497135088229252555151526291001176623256451262865246234,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.878s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"2.chip_sw_i2c_host_tx_rx.17132170855682764871866868463769947224729961343770442746683510922299181759837","seed":17132170855682764871866868463769947224729961343770442746683510922299181759837,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.308s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"2.chip_sw_i2c_device_tx_rx.83888879958320600005509575935656338773168384902676741827176158773642526166607","seed":83888879958320600005509575935656338773168384902676741827176158773642526166607,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.372s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"2.chip_sw_spi_device_tpm.53417681995627402140806832580070654502310665854818308438694530001979896915752","seed":53417681995627402140806832580070654502310665854818308438694530001979896915752,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.526s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"2.chip_sw_spi_host_tx_rx.17105996350688408581017378144986079149316937678227674078124746136183019246433","seed":17105996350688408581017378144986079149316937678227674078124746136183019246433,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.544s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"2.chip_sw_lc_ctrl_otp_hw_cfg.25391707382203647497622109035465102446438669765727914858057980575516715193444","seed":25391707382203647497622109035465102446438669765727914858057980575516715193444,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=2513970) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=2517431) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.106774309882922129947024850531082628014731311657228237394944644747945439209361","seed":106774309882922129947024850531082628014731311657228237394944644747945439209361,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.156s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"2.chip_sw_otp_ctrl_lc_signals_dev.52665234070427046047980289746840494204177832359939080824037935201738041653490","seed":52665234070427046047980289746840494204177832359939080824037935201738041653490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.869s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"2.chip_sw_otp_ctrl_lc_signals_prod.33877148802922805269164101999106121697281708186066779668233648790023373943001","seed":33877148802922805269164101999106121697281708186066779668233648790023373943001,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.306s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.100290907886816529551965909692203531070952019610668051609080264391811605718297","seed":100290907886816529551965909692203531070952019610668051609080264391811605718297,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.353s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"2.chip_sw_otp_ctrl_vendor_test_csr_access.4285596847923004447468158417270322356555904489678671484834049384022818483954","seed":4285596847923004447468158417270322356555904489678671484834049384022818483954,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.931s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"2.chip_sw_lc_ctrl_transition.105285823373965754295202288671144891909045272116489408826871777429888147764300","seed":105285823373965754295202288671144891909045272116489408826871777429888147764300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.585s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.57664862739027210611939964121812742845159018360179765066168822173203399355737","seed":57664862739027210611939964121812742845159018360179765066168822173203399355737,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.615s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.10202103862572470174337353887480787775630687976986294830366177637920798848728","seed":10202103862572470174337353887480787775630687976986294830366177637920798848728,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.834s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"2.chip_sw_lc_walkthrough_prodend.18736460394417802824346791103583488346318784141291151475493883862898179215897","seed":18736460394417802824346791103583488346318784141291151475493883862898179215897,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.816s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.56862425198628412560532502648738151200206437996239404515658111712569390699943","seed":56862425198628412560532502648738151200206437996239404515658111712569390699943,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.298s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"2.chip_sw_lc_walkthrough_testunlocks.72901706543316895031971750229753028157370703075705495823346668058031947715403","seed":72901706543316895031971750229753028157370703075705495823346668058031947715403,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.835s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_main_power_glitch_reset.99115978709478258161013965474370070921613631218532198078042331643907059958415","seed":99115978709478258161013965474370070921613631218532198078042331643907059958415,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.391s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.37433263240122640502367619927645474060831533484065101205164251385146450564005","seed":37433263240122640502367619927645474060831533484065101205164251385146450564005,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.837s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.59832685784043212543388224662874749954852736746819892548134818741156629398778","seed":59832685784043212543388224662874749954852736746819892548134818741156629398778,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.151s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.11655949382529925306746777623418773459001511627550226748976140789775436782662","seed":11655949382529925306746777623418773459001511627550226748976140789775436782662,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.863s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"2.chip_sw_pwrmgr_sleep_disabled.51495176790964628006956986145026482474198583341680954156444652149358629673682","seed":51495176790964628006956986145026482474198583341680954156444652149358629673682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.235s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"2.chip_sw_pwrmgr_wdog_reset.79314919984139100504018238443034732622657781928932375804303894547244508781661","seed":79314919984139100504018238443034732622657781928932375804303894547244508781661,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.545s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.17006197593079819163348809265087361761592986846607734174147425238562242631166","seed":17006197593079819163348809265087361761592986846607734174147425238562242631166,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"2.chip_sw_alert_handler_escalation.44726728459429204233637723326438068970029837256627535622472690660451413501925","seed":44726728459429204233637723326438068970029837256627535622472690660451413501925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.361s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.7376573280037026924288441733359158164228214155670038755816376395239369336600","seed":7376573280037026924288441733359158164228214155670038755816376395239369336600,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.817s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.9634307223998216723273455349497029093430929836811733130440571172288793645701","seed":9634307223998216723273455349497029093430929836811733130440571172288793645701,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.23345192541356742724871253372897602009850292210658687995602995890244802494454","seed":23345192541356742724871253372897602009850292210658687995602995890244802494454,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.565s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"2.chip_sw_alert_handler_lpg_clkoff.47243254511726975095876332680270379999881651968812885668015921631335601907625","seed":47243254511726975095876332680270379999881651968812885668015921631335601907625,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.456s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"2.chip_sw_alert_handler_lpg_reset_toggle.25902912444818411313310892684878368967950813669156094729743941876654245354397","seed":25902912444818411313310892684878368967950813669156094729743941876654245354397,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.852s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"2.chip_sw_alert_handler_entropy.102069139322562505802678965889364834463660631413382941154008527043090598961825","seed":102069139322562505802678965889364834463660631413382941154008527043090598961825,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.344s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.71961048463275067899826473809450326305936706446022975197104004113602960371840","seed":71961048463275067899826473809450326305936706446022975197104004113602960371840,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.564s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"2.chip_sw_kmac_app_rom.95309717784953611030226840256923005046464944074207013153047937027079130206531","seed":95309717784953611030226840256923005046464944074207013153047937027079130206531,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).\n","DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the build_info section will use a fixed version string\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"2.chip_sw_sram_ctrl_scrambled_access_jitter_en.112191067182512495002221026488411208693304242896961462131272611679116712403982","seed":112191067182512495002221026488411208693304242896961462131272611679116712403982,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=2685795) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"2.chip_sw_sram_ctrl_execution_main.23325954719525523401150864757928978127552977546229453270837317383775848732618","seed":23325954719525523401150864757928978127552977546229453270837317383775848732618,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.632s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"2.chip_sw_clkmgr_reset_frequency.83764306959978376151508397647003562492242778896585849857345463647318486218780","seed":83764306959978376151508397647003562492242778896585849857345463647318486218780,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.282s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"2.chip_sw_clkmgr_sleep_frequency.24890834394533360918841441383601652583041320182734657562095478192327358093468","seed":24890834394533360918841441383601652583041320182734657562095478192327358093468,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.360s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"2.chip_sw_ast_clk_outputs.1285506975375386059019109609442273217288997488471842904115340830341681456402","seed":1285506975375386059019109609442273217288997488471842904115340830341681456402,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.256s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"2.chip_sw_lc_ctrl_program_error.18541651624832770887292714757535304401761560575537961964376349964284669987304","seed":18541651624832770887292714757535304401761560575537961964376349964284669987304,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.103s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3460876666689430726252898008354657893970759364232975209046224260197207252559","seed":3460876666689430726252898008354657893970759364232975209046224260197207252559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.110726663743141320971268681637180140068424533906405453919455321483055908235837","seed":110726663743141320971268681637180140068424533906405453919455321483055908235837,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"2.chip_sw_rv_dm_access_after_escalation_reset.99082509363826078211847428305024492148010566806817707499845431538468856825163","seed":99082509363826078211847428305024492148010566806817707499845431538468856825163,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.408s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"2.chip_sw_power_virus.45858291647129019302018650457775765247871197213922726056296414419892100466523","seed":45858291647129019302018650457775765247871197213922726056296414419892100466523,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.316s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"2.base_rom_e2e_smoke.18559584971571914635588583825050952108037550595193094090279391993645323109100","seed":18559584971571914635588583825050952108037550595193094090279391993645323109100,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 329, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 261, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"2.rom_e2e_smoke.74832531324912231831036007944686050964383909015074173052880425637661719340423","seed":74832531324912231831036007944686050964383909015074173052880425637661719340423,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_smoke/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=2707584) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"2.rom_e2e_shutdown_exception_c.11369702550280938488635072352840646253082429135897626102363800432933136355237","seed":11369702550280938488635072352840646253082429135897626102363800432933136355237,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"2.rom_e2e_shutdown_output.13562662362499598108769032766028579679886430691355682354127594692457324685410","seed":13562662362499598108769032766028579679886430691355682354127594692457324685410,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=566529) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.60467725455023118552488822799835074038650077518986840174021691245548286832722","seed":60467725455023118552488822799835074038650077518986840174021691245548286832722,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=215037) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=224155) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=224203) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.79970742589527687925811537316177914294557443126582485206014928783702019181024","seed":79970742589527687925811537316177914294557443126582485206014928783702019181024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.104246924396826387043705392332524175352995268121899268001316914337208249000573","seed":104246924396826387043705392332524175352995268121899268001316914337208249000573,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.104662797763548467272695452700178491584752611978240159171081556762991373957044","seed":104662797763548467272695452700178491584752611978240159171081556762991373957044,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.2919423369538026410329813928790867293708737847722181794253749934154551373184","seed":2919423369538026410329813928790867293708737847722181794253749934154551373184,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=393608) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"2.rom_e2e_static_critical.102608094656827909765593874558234238236520875452780074549830830159845595157802","seed":102608094656827909765593874558234238236520875452780074549830830159845595157802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_meas.81457634675496740706715003871606354513819246738640798627671272147080201407893","seed":81457634675496740706715003871606354513819246738640798627671272147080201407893,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=563617) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_no_meas.72369076342666795235963788875477355146886349777230890349073593236703998585099","seed":72369076342666795235963788875477355146886349777230890349073593236703998585099,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_invalid_meas.78594348339202026947471765881138477488711541263533177215137897902577873460202","seed":78594348339202026947471765881138477488711541263533177215137897902577873460202,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=563243) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.16129260859968297464336098993895507906732756460782174559167448103393524585844","seed":16129260859968297464336098993895507906732756460782174559167448103393524585844,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=247961) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.53411411193711262223258010417715620884954771688575395637744357084455887231461","seed":53411411193711262223258010417715620884954771688575395637744357084455887231461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=246257) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_dev_otbn.110088960030209121391710052285126031744711697727659567275243659541889688251720","seed":110088960030209121391710052285126031744711697727659567275243659541889688251720,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_dev_sw.75654733638901139803861631068166527335061830385399146827110154030545360791439","seed":75654733638901139803861631068166527335061830385399146827110154030545360791439,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_otbn.64548085647028367412127584846966087529479521446640780330518492528918875196612","seed":64548085647028367412127584846966087529479521446640780330518492528918875196612,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_sw.17937484057433949697169951013541283688039105212626985356227773011479799418185","seed":17937484057433949697169951013541283688039105212626985356227773011479799418185,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_end_otbn.68094268620085856841989802780385881524005790693904576707255645586226741804808","seed":68094268620085856841989802780385881524005790693904576707255645586226741804808,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_end_sw.53439018159841269214239081194670259870584092534648889914775606858849811001615","seed":53439018159841269214239081194670259870584092534648889914775606858849811001615,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=568009) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_rma_otbn.94598639820793458736456794892097346924778403792715452149309997254956585302453","seed":94598639820793458736456794892097346924778403792715452149309997254956585302453,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_rma_sw.9919711431407620453086109076654332332453971809116629183916367228879578748908","seed":9919711431407620453086109076654332332453971809116629183916367228879578748908,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.101377825229738431510002723092085647839327484567925501026305688750079366251398","seed":101377825229738431510002723092085647839327484567925501026305688750079366251398,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=249049) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.18831172136896999114903327226250169551361163970394721164508398947870912279629","seed":18831172136896999114903327226250169551361163970394721164508398947870912279629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=247961) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.73860101165824668937596456986591624485750561632601541852194628093171584238049","seed":73860101165824668937596456986591624485750561632601541852194628093171584238049,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=248001) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"2.chip_sw_uart_smoketest_signed.103072902510616994301703447055311806130523818701503300539637626852649200623797","seed":103072902510616994301703447055311806130523818701503300539637626852649200623797,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.78305786990044677985583448775756523986453547690827043972721197193492465702011","seed":78305786990044677985583448775756523986453547690827043972721197193492465702011,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.548s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"3.chip_sw_data_integrity_escalation.45534072013144466754215201196209261574252382620824288598486930071435911416460","seed":45534072013144466754215201196209261574252382620824288598486930071435911416460,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.606s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"3.chip_sw_uart_tx_rx.55170311015723400567436820567205972468934416198175701355469018192668210457209","seed":55170311015723400567436820567205972468934416198175701355469018192668210457209,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.650s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"3.chip_sw_uart_rand_baudrate.55840124293948041793487100596179925318328457959182039810060341137411348154544","seed":55840124293948041793487100596179925318328457959182039810060341137411348154544,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.375s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"3.chip_sw_uart_tx_rx_alt_clk_freq.68189829371591867363232052598952934999489327262795131103072810547982757526340","seed":68189829371591867363232052598952934999489327262795131103072810547982757526340,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.319s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"3.chip_sw_lc_ctrl_transition.28013151920691330692010957558181187420360215925512936250674899150922696942059","seed":28013151920691330692010957558181187420360215925512936250674899150922696942059,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.089s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.60994350766770406422415454357548245025046937635738626395264288766054357224404","seed":60994350766770406422415454357548245025046937635738626395264288766054357224404,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"4.chip_sw_data_integrity_escalation.72504291782549902456681949884301388853823473384217935625285405759523066841461","seed":72504291782549902456681949884301388853823473384217935625285405759523066841461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.732s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"4.chip_sw_uart_tx_rx.67474539689707240740981805896015280929924330913522999144749966765053491586625","seed":67474539689707240740981805896015280929924330913522999144749966765053491586625,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.372s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"4.chip_sw_uart_rand_baudrate.113050943809483334305485179198088791933913382579285184857767944504640162005967","seed":113050943809483334305485179198088791933913382579285184857767944504640162005967,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.343s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"4.chip_sw_uart_tx_rx_alt_clk_freq.99392882319032054773366813930647042344514368604591306498506119241655714942786","seed":99392882319032054773366813930647042344514368604591306498506119241655714942786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.379s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"4.chip_sw_lc_ctrl_transition.12461603559519270521274204859460472604413565201982173968373418168123128448220","seed":12461603559519270521274204859460472604413565201982173968373418168123128448220,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.369s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.115662329238643213428770114398092451539834943037335574681652679115512491396640","seed":115662329238643213428770114398092451539834943037335574681652679115512491396640,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"5.chip_sw_data_integrity_escalation.45370053609001451470725991633666145651700636553795091936367345580957603434282","seed":45370053609001451470725991633666145651700636553795091936367345580957603434282,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.596s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"5.chip_sw_uart_rand_baudrate.55806663188414630113508601608094348551085065707337824864341519822683963276513","seed":55806663188414630113508601608094348551085065707337824864341519822683963276513,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.315s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"5.chip_sw_lc_ctrl_transition.81913157286690369788004557586968854445377487231285821538939358661252527240786","seed":81913157286690369788004557586968854445377487231285821538939358661252527240786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.589s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4239820093093831475123187659190131962977741787344540580469436221950527302072","seed":4239820093093831475123187659190131962977741787344540580469436221950527302072,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"6.chip_sw_uart_rand_baudrate.26631656040733828361827510468753715604958976418623986278925805246226549643528","seed":26631656040733828361827510468753715604958976418623986278925805246226549643528,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.431s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"6.chip_sw_lc_ctrl_transition.92789787200763400491680111658835927495951801667641752965144581803401948762485","seed":92789787200763400491680111658835927495951801667641752965144581803401948762485,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.204s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.109016018387133315722169896385871767688219832956312102102409914214047840641985","seed":109016018387133315722169896385871767688219832956312102102409914214047840641985,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"7.chip_sw_uart_rand_baudrate.55887407820174521994015697941000815511262804020500085540489583570964696721070","seed":55887407820174521994015697941000815511262804020500085540489583570964696721070,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.357s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"7.chip_sw_lc_ctrl_transition.87795246210196103939095597317985825761975579446813496578754295879207691659414","seed":87795246210196103939095597317985825761975579446813496578754295879207691659414,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.455s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.98702640710725419554376978143623186205365141206803295901432011416981939211689","seed":98702640710725419554376978143623186205365141206803295901432011416981939211689,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"8.chip_sw_uart_rand_baudrate.38465534125400140202278409852852986188775656654968678768786173412962577007312","seed":38465534125400140202278409852852986188775656654968678768786173412962577007312,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.394s, Critical Path: 0.00s\n","INFO: 0 processes.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"8.chip_sw_lc_ctrl_transition.33688759686030574911462216060981265137142701473929728753912488160837771258047","seed":33688759686030574911462216060981265137142701473929728753912488160837771258047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.412s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085316854802046153951883932439558979961573463299095941499898811264779287336","seed":3085316854802046153951883932439558979961573463299095941499898811264779287336,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"9.chip_sw_uart_rand_baudrate.90109732535221566144030676068018358807017928352095106014486857698443689024990","seed":90109732535221566144030676068018358807017928352095106014486857698443689024990,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.459s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"9.chip_sw_lc_ctrl_transition.55428126231502160132638097895605892199605973434615495116470172151131751484277","seed":55428126231502160132638097895605892199605973434615495116470172151131751484277,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.752s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.103205412802415546922109912395689002972874557503990122409856677299793188516947","seed":103205412802415546922109912395689002972874557503990122409856677299793188516947,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"10.chip_sw_uart_rand_baudrate.114262743402620405788670680791136370610816737780989426793176318692923367961456","seed":114262743402620405788670680791136370610816737780989426793176318692923367961456,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.298s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"10.chip_sw_lc_ctrl_transition.670371869514193166402196185872181098870484352000143166030466708516008823600","seed":670371869514193166402196185872181098870484352000143166030466708516008823600,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.741s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.95620565395944869970058604765457659227783637129230706241595424630419593986404","seed":95620565395944869970058604765457659227783637129230706241595424630419593986404,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=324217) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"11.chip_sw_uart_rand_baudrate.52824465669047209291319044719084714757332959169560223197916111299174803973503","seed":52824465669047209291319044719084714757332959169560223197916111299174803973503,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.289s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"11.chip_sw_lc_ctrl_transition.68938467911591760036983501049048012472600347199575470345715199527444282798441","seed":68938467911591760036983501049048012472600347199575470345715199527444282798441,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.564s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.60061890008051336677545127103981424397914364670309915131421720239924267483883","seed":60061890008051336677545127103981424397914364670309915131421720239924267483883,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=331872) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"12.chip_sw_uart_rand_baudrate.4993704603077268370094367868982388934647171792354691666754180055872822327383","seed":4993704603077268370094367868982388934647171792354691666754180055872822327383,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.563s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"12.chip_sw_lc_ctrl_transition.61647481768255007765829877405528896631397952234346926409698046415424860466293","seed":61647481768255007765829877405528896631397952234346926409698046415424860466293,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.494s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.62829824903244564057021238634004081524491916203043152175715113510891639574461","seed":62829824903244564057021238634004081524491916203043152175715113510891639574461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"13.chip_sw_uart_rand_baudrate.1750555178136357277672413321866239733672635046615868004282173584292679899847","seed":1750555178136357277672413321866239733672635046615868004282173584292679899847,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.336s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"13.chip_sw_lc_ctrl_transition.76073698302958470856520885571450909812604875412407044116487711305508371765208","seed":76073698302958470856520885571450909812604875412407044116487711305508371765208,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.401s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.62600543312517658715313320304160803254904752619931576096889807495594677434031","seed":62600543312517658715313320304160803254904752619931576096889807495594677434031,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"14.chip_sw_uart_rand_baudrate.109937763195734800206070264036321865327783553627698081774789509531514347677","seed":109937763195734800206070264036321865327783553627698081774789509531514347677,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.450s, Critical Path: 0.00s\n","INFO: 0 processes.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"14.chip_sw_lc_ctrl_transition.5562885181274031797086385830850794938044228376531178247466390537686812523252","seed":5562885181274031797086385830850794938044228376531178247466390537686812523252,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.408s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.51406540367426145059042701265766175407110166015437820575591132231480268252773","seed":51406540367426145059042701265766175407110166015437820575591132231480268252773,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"15.chip_sw_uart_rand_baudrate.90408274013693751621839865631663044378587461888091321705261716156527393505612","seed":90408274013693751621839865631663044378587461888091321705261716156527393505612,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.464s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.16018457680852771904597287680519683472632345210599379329556098426132494127818","seed":16018457680852771904597287680519683472632345210599379329556098426132494127818,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=333606) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"16.chip_sw_uart_rand_baudrate.70200850910433075505994664845167490434617706569053581321615955803879763277613","seed":70200850910433075505994664845167490434617706569053581321615955803879763277613,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.608s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.28838255950417329105906563328903120988340025125875892780088376138234182237215","seed":28838255950417329105906563328903120988340025125875892780088376138234182237215,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"17.chip_sw_uart_rand_baudrate.106030301434822297071328251659554784459284108807681407725220243032595417939745","seed":106030301434822297071328251659554784459284108807681407725220243032595417939745,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.367s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.99729693868684430048336168543929445554006977506438109370713509084289093095581","seed":99729693868684430048336168543929445554006977506438109370713509084289093095581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=335272) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"18.chip_sw_uart_rand_baudrate.18820743086785506486101800326750088569873070373074100071452886573950859823756","seed":18820743086785506486101800326750088569873070373074100071452886573950859823756,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.343s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.100877162497647312976545216597830081125217009379139491373946168271082638136024","seed":100877162497647312976545216597830081125217009379139491373946168271082638136024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"19.chip_sw_uart_rand_baudrate.26302742360746701889465499018890935747713201333254007849411495003756768104391","seed":26302742360746701889465499018890935747713201333254007849411495003756768104391,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.353s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.55381761104935180582751221019720948949917822070396708324112491630781412330986","seed":55381761104935180582751221019720948949917822070396708324112491630781412330986,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.99667841944086216742528964323267151724398628248226142077600876548871086998980","seed":99667841944086216742528964323267151724398628248226142077600876548871086998980,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=351118) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=349863) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=352182) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.9951086136167716231121709331709612844408440411932885279194525237577835491412","seed":9951086136167716231121709331709612844408440411932885279194525237577835491412,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=352182) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=350117) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.29882765893018954174557369455078494614930056509009624230994728216010319777641","seed":29882765893018954174557369455078494614930056509009624230994728216010319777641,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=352978) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=353166) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.93191482587896298461599364784360412440412955804545246544562185320839209822924","seed":93191482587896298461599364784360412440412955804545246544562185320839209822924,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=353166) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=354337) is running. Waiting for it to complete on the server (server_pid=207925)...\n","Another command (pid=355837) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.63688866061971444547745403612638617198304610085634043536031612246707268639373","seed":63688866061971444547745403612638617198304610085634043536031612246707268639373,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.70279394545371358090026281143651962231901455880008227472454593860324404744762","seed":70279394545371358090026281143651962231901455880008227472454593860324404744762,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.58211310328537386102691195005441310989745730683017984676408302011067640590787","seed":58211310328537386102691195005441310989745730683017984676408302011067640590787,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.50127612635022735040835425391436020517175561064740641505993090762760369253471","seed":50127612635022735040835425391436020517175561064740641505993090762760369253471,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.104935056942301161570955331714935355538685653559159797980235465801633783896678","seed":104935056942301161570955331714935355538685653559159797980235465801633783896678,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.80509810144103857338384304432692244868456827747489491513262606635872334324148","seed":80509810144103857338384304432692244868456827747489491513262606635872334324148,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.49304274032178027808416829521240003526899846206195515800352698312908768533898","seed":49304274032178027808416829521240003526899846206195515800352698312908768533898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.110024721026509976834968880788613249335640194551777753004062677117983200728455","seed":110024721026509976834968880788613249335640194551777753004062677117983200728455,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.6737672907854188229646899787028622868178226713145348181922431473073829606167","seed":6737672907854188229646899787028622868178226713145348181922431473073829606167,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.78278574692422411160203146682374307665138274282258347829833519889911893720500","seed":78278574692422411160203146682374307665138274282258347829833519889911893720500,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.55160030805152221670841490356236886683687819174986028004204702554436378318976","seed":55160030805152221670841490356236886683687819174986028004204702554436378318976,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.109541409804452079885236484237832025129715293916869519733713676922784208916667","seed":109541409804452079885236484237832025129715293916869519733713676922784208916667,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.9709229395109550108173988999817151041309300044458347083600532761954351156645","seed":9709229395109550108173988999817151041309300044458347083600532761954351156645,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=362246) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.52353498228014856536629123770863336281792248100815632922309704875984545553719","seed":52353498228014856536629123770863336281792248100815632922309704875984545553719,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.41649204507395370132843254204589374539071166092887912229453115994697406155032","seed":41649204507395370132843254204589374539071166092887912229453115994697406155032,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775958431967205264713958819954740004770576859205205909095915162550281147960","seed":1775958431967205264713958819954740004770576859205205909095915162550281147960,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.80608584034551554009955692545666750200845705168369880210480017107717910749408","seed":80608584034551554009955692545666750200845705168369880210480017107717910749408,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.81708178639949966514235434502338326145477432172492623205813050379763873169301","seed":81708178639949966514235434502338326145477432172492623205813050379763873169301,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.37341187459469005138665410393526190282553406602230217492044092753906465650724","seed":37341187459469005138665410393526190282553406602230217492044092753906465650724,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.96850188081101853310755950433154853301814936838866610950970707781020059946217","seed":96850188081101853310755950433154853301814936838866610950970707781020059946217,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.103143046094239860261263591994506003236535394037971874362150809878028942647607","seed":103143046094239860261263591994506003236535394037971874362150809878028942647607,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.33956997389735976609877818821088087566253084763103544178603526215827007143076","seed":33956997389735976609877818821088087566253084763103544178603526215827007143076,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.25016300803166605244945686311195120762740875739785579487356584458335166064919","seed":25016300803166605244945686311195120762740875739785579487356584458335166064919,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.14911129661910306795690366465730343609308125255077356197833511939649953777606","seed":14911129661910306795690366465730343609308125255077356197833511939649953777606,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=365668) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.71328698944479465426647656985545213310064789630956933070153756020550791832072","seed":71328698944479465426647656985545213310064789630956933070153756020550791832072,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.81235160569356226190536793861680655141589528108534778425712935864427079430637","seed":81235160569356226190536793861680655141589528108534778425712935864427079430637,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.66884327488280457803806799524084090625568191440893623914500805353271904819549","seed":66884327488280457803806799524084090625568191440893623914500805353271904819549,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.59380002730183647295025242080405796914697689591842440619317637897918315298086","seed":59380002730183647295025242080405796914697689591842440619317637897918315298086,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.89963099562193274448979399972591700069321894986156805299471085553716407104280","seed":89963099562193274448979399972591700069321894986156805299471085553716407104280,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.34714015418631829459103276067078125682555291130872418456103704295198000343292","seed":34714015418631829459103276067078125682555291130872418456103704295198000343292,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.68881905492063939942164961467008236234412029847234719471954597707344339015204","seed":68881905492063939942164961467008236234412029847234719471954597707344339015204,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680513105500724377931216499089072229003571072204158203072929100636922986025","seed":3680513105500724377931216499089072229003571072204158203072929100636922986025,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.39144941788271022473697571101723494559363822490321995586644607227019248893404","seed":39144941788271022473697571101723494559363822490321995586644607227019248893404,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.19732652043393549387344010790850636526347160986987547880828313095632729861344","seed":19732652043393549387344010790850636526347160986987547880828313095632729861344,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.65652891379888324744002307896839400639771528503521015557058444633953802526744","seed":65652891379888324744002307896839400639771528503521015557058444633953802526744,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.18140031647909054330219286606719456805399347622301104950854664380457307289388","seed":18140031647909054330219286606719456805399347622301104950854664380457307289388,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.13812512112344283640189288845977264102013937718458958411355472753690730893855","seed":13812512112344283640189288845977264102013937718458958411355472753690730893855,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.20203985586461497503754253972551387908700888400322128365954701085716821618537","seed":20203985586461497503754253972551387908700888400322128365954701085716821618537,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.79547872592786906059593815071441922770766440346254864440596586991843879294265","seed":79547872592786906059593815071441922770766440346254864440596586991843879294265,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.101006763445300158005768393799492438124499312585933146592531901029073154710964","seed":101006763445300158005768393799492438124499312585933146592531901029073154710964,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.97991953551198005544108501881042347443718894478026390415787445827405176704519","seed":97991953551198005544108501881042347443718894478026390415787445827405176704519,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.26431908315167211926435557074521419631337158192495104250100175734942496195961","seed":26431908315167211926435557074521419631337158192495104250100175734942496195961,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.73427108346183760375432742491352513506041002241992021655390822154944003847309","seed":73427108346183760375432742491352513506041002241992021655390822154944003847309,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510348230824391572404416620043700152615078405474431933897515316780916421216","seed":3510348230824391572404416620043700152615078405474431933897515316780916421216,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.82346530204167239176577846021754524460137297051007318855746746112392755842313","seed":82346530204167239176577846021754524460137297051007318855746746112392755842313,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.104977241016222456010757439959593602764327152775971419351093817134549606881566","seed":104977241016222456010757439959593602764327152775971419351093817134549606881566,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.110586763574549423581505404941814143732244653876541083627003464476219366690744","seed":110586763574549423581505404941814143732244653876541083627003464476219366690744,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.57596763268257737677422491122158550943674156980200705393168053675683565537897","seed":57596763268257737677422491122158550943674156980200705393168053675683565537897,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.98860648811217502216459877214452810974404940030719025900019237862480919607558","seed":98860648811217502216459877214452810974404940030719025900019237862480919607558,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.48327917915264245104545277056964487188693742428659396004328070242299085439048","seed":48327917915264245104545277056964487188693742428659396004328070242299085439048,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.26448500082758055046457050584231802423661504940233930297717397805883037490619","seed":26448500082758055046457050584231802423661504940233930297717397805883037490619,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.34278230002339793415486882893006644885347997828317503226556711062104070055444","seed":34278230002339793415486882893006644885347997828317503226556711062104070055444,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=374676) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.108893941728438585303289827484538971879253849502717745027431791828604426890541","seed":108893941728438585303289827484538971879253849502717745027431791828604426890541,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=374632) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.79509053565697692463897640996360072879719514243424113779848784171120967086264","seed":79509053565697692463897640996360072879719514243424113779848784171120967086264,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.79024937455866905118557860087551373579169992447602170306351335076066620782757","seed":79024937455866905118557860087551373579169992447602170306351335076066620782757,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.27949014252512495471471062720066711551707432616148395608659601263684194969681","seed":27949014252512495471471062720066711551707432616148395608659601263684194969681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.105589621493253093826840501955438875840421913838667982283997108126389117140521","seed":105589621493253093826840501955438875840421913838667982283997108126389117140521,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.75827753973329160767633120639024971279654259238765727272039940566494790487428","seed":75827753973329160767633120639024971279654259238765727272039940566494790487428,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=376897) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.24026811580698148722602648571143054980059556162019922172674491751843777964010","seed":24026811580698148722602648571143054980059556162019922172674491751843777964010,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.56446679122952055530192091369347540038965396532562413780251629651881201409259","seed":56446679122952055530192091369347540038965396532562413780251629651881201409259,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.43308184412893548452231925965314111798712544910994762622877406431025923651914","seed":43308184412893548452231925965314111798712544910994762622877406431025923651914,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.81715977361861125760700799473455546888724141504801279827661915281931556293437","seed":81715977361861125760700799473455546888724141504801279827661915281931556293437,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=378066) is running. Waiting for it to complete on the server (server_pid=207925)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.32005241746698504171333338369877551386129976429710680203229810139579747221710","seed":32005241746698504171333338369877551386129976429710680203229810139579747221710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.65761925175851561348074819487733340744412797707611773657102299028155614443587","seed":65761925175851561348074819487733340744412797707611773657102299028155614443587,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.101064822696906427436661822253180434323795643007282950862406227416310001542267","seed":101064822696906427436661822253180434323795643007282950862406227416310001542267,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.40046407356850910017238548235550192666452429893585952644328144258946388377696","seed":40046407356850910017238548235550192666452429893585952644328144258946388377696,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_all_escalation_resets","qual_name":"0.chip_sw_all_escalation_resets.27688829795644347422582950689690045886527426645183111762503106414808399874312","seed":27688829795644347422582950689690045886527426645183111762503106414808399874312,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.583000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"1.chip_sw_all_escalation_resets.37289986366256692739117979807892864858586392217815891588228124748473029952375","seed":37289986366256692739117979807892864858586392217815891588228124748473029952375,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.557000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"2.chip_sw_all_escalation_resets.60422620006355536858779948663539575290456713702668450574678547446055898792757","seed":60422620006355536858779948663539575290456713702668450574678547446055898792757,"line":363,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.519000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"3.chip_sw_all_escalation_resets.63355381083432709148660875335864528594639835092591768474411969461632231879565","seed":63355381083432709148660875335864528594639835092591768474411969461632231879565,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.698000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"4.chip_sw_all_escalation_resets.31449989379432439044408766413986434548244978755789658489330115975915377333539","seed":31449989379432439044408766413986434548244978755789658489330115975915377333539,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.776000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"5.chip_sw_all_escalation_resets.21157328394424339865833260275398332416505880927343701982532948644140002064296","seed":21157328394424339865833260275398332416505880927343701982532948644140002064296,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"6.chip_sw_all_escalation_resets.63474243377120438310863478678111354766794673226490196994241321574204133488407","seed":63474243377120438310863478678111354766794673226490196994241321574204133488407,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"7.chip_sw_all_escalation_resets.17827522199338515240871264977054238611152899418170706670152476180433716992888","seed":17827522199338515240871264977054238611152899418170706670152476180433716992888,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.718000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"8.chip_sw_all_escalation_resets.64357622787941522337063195003139723829767607492139162379898445826969439120558","seed":64357622787941522337063195003139723829767607492139162379898445826969439120558,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.605000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"9.chip_sw_all_escalation_resets.84526863471940093020206895799168433708779564628663710929057720850712339965428","seed":84526863471940093020206895799168433708779564628663710929057720850712339965428,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.661000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"10.chip_sw_all_escalation_resets.62980491875331682585458256614802380472609679838001752382243618063977859308226","seed":62980491875331682585458256614802380472609679838001752382243618063977859308226,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 944.222000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"11.chip_sw_all_escalation_resets.6901955343446029750779634239554469907723253206698332207620408135471349965275","seed":6901955343446029750779634239554469907723253206698332207620408135471349965275,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.818000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"12.chip_sw_all_escalation_resets.30391811740801831754234699980877019937441694863985669448122651660516685963899","seed":30391811740801831754234699980877019937441694863985669448122651660516685963899,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.608000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"13.chip_sw_all_escalation_resets.81464079339620925011448101721205982717089762649724016820147941980066642732661","seed":81464079339620925011448101721205982717089762649724016820147941980066642732661,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.642000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"14.chip_sw_all_escalation_resets.78888844234970560953347143083742423838987186102056655557636925235186510835897","seed":78888844234970560953347143083742423838987186102056655557636925235186510835897,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.778000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"15.chip_sw_all_escalation_resets.56223889524479596635342157210943354348224844568387278314033727610634381864305","seed":56223889524479596635342157210943354348224844568387278314033727610634381864305,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.515000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"16.chip_sw_all_escalation_resets.11400786047897228159522613359244915050695864921545364591304601749283589697323","seed":11400786047897228159522613359244915050695864921545364591304601749283589697323,"line":363,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.662000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"17.chip_sw_all_escalation_resets.112570344899321400329299352517553270130090300321217936383058962761448332288911","seed":112570344899321400329299352517553270130090300321217936383058962761448332288911,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.666000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"18.chip_sw_all_escalation_resets.84757145471936201441240978794850751057253896456735247655847081539556048044270","seed":84757145471936201441240978794850751057253896456735247655847081539556048044270,"line":365,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.842000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"20.chip_sw_all_escalation_resets.98569513119884972806042848474585356892893597290380096339190385846933838062167","seed":98569513119884972806042848474585356892893597290380096339190385846933838062167,"line":356,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"21.chip_sw_all_escalation_resets.102268396807847946122916846669221009308383311021659670523922253715658254671804","seed":102268396807847946122916846669221009308383311021659670523922253715658254671804,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 944.145000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"22.chip_sw_all_escalation_resets.614921087965070829162010529103522327145326833309349463269509539774766358166","seed":614921087965070829162010529103522327145326833309349463269509539774766358166,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.737000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"23.chip_sw_all_escalation_resets.26423097168360730586441204086914918907728345079218187113517731404241060601126","seed":26423097168360730586441204086914918907728345079218187113517731404241060601126,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"24.chip_sw_all_escalation_resets.12739491342468120987994009998426371316710973952693208924090922230006829607098","seed":12739491342468120987994009998426371316710973952693208924090922230006829607098,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.706000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"25.chip_sw_all_escalation_resets.9358949871268509822793546754281542887536466442446800320312536483135804391043","seed":9358949871268509822793546754281542887536466442446800320312536483135804391043,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.514000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"26.chip_sw_all_escalation_resets.38713961210445417221214697124393230123181144594794439414774587004599483447904","seed":38713961210445417221214697124393230123181144594794439414774587004599483447904,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.751000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"27.chip_sw_all_escalation_resets.45206976818230894878586652280581827612775973154211810603789294193565906668590","seed":45206976818230894878586652280581827612775973154211810603789294193565906668590,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.781000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"28.chip_sw_all_escalation_resets.47511657203573247541364695060850203791845549998452846442376597126210606289502","seed":47511657203573247541364695060850203791845549998452846442376597126210606289502,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.862000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"29.chip_sw_all_escalation_resets.9857321592603305008857624176873094021285012624541461657646879401774527636006","seed":9857321592603305008857624176873094021285012624541461657646879401774527636006,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.675000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"31.chip_sw_all_escalation_resets.82862749657371187744518777434382829891376576996928681129760659467859829458187","seed":82862749657371187744518777434382829891376576996928681129760659467859829458187,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.717000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"32.chip_sw_all_escalation_resets.63986765403864779774312999987956502102468479826746506343585944451095550482771","seed":63986765403864779774312999987956502102468479826746506343585944451095550482771,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.737000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"33.chip_sw_all_escalation_resets.51754924938254710971666384820715951547037808471132857869953425539946571255095","seed":51754924938254710971666384820715951547037808471132857869953425539946571255095,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.590000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"34.chip_sw_all_escalation_resets.61815171442234025664934791478536283104240331239406357593151788716644603119335","seed":61815171442234025664934791478536283104240331239406357593151788716644603119335,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"35.chip_sw_all_escalation_resets.43154519858928729893578365160585378058228522431559912778535681285797111108209","seed":43154519858928729893578365160585378058228522431559912778535681285797111108209,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.739000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"36.chip_sw_all_escalation_resets.55957644219408943116321256072479983199529763890628415845461495948395466363442","seed":55957644219408943116321256072479983199529763890628415845461495948395466363442,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.600000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"37.chip_sw_all_escalation_resets.38296716850721131936564271516249289800916835705988417782555902108712669412168","seed":38296716850721131936564271516249289800916835705988417782555902108712669412168,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.597000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"38.chip_sw_all_escalation_resets.87898882270988143853125690072402363942106393970064409140220187144431721013302","seed":87898882270988143853125690072402363942106393970064409140220187144431721013302,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.708000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"39.chip_sw_all_escalation_resets.79445151794278343721585808590023850547091788546673223913608760924016389599648","seed":79445151794278343721585808590023850547091788546673223913608760924016389599648,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.912000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"40.chip_sw_all_escalation_resets.98612775842633180230055478231340032427714918464094528888669787441435844202210","seed":98612775842633180230055478231340032427714918464094528888669787441435844202210,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.567000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"41.chip_sw_all_escalation_resets.112363705728822119990892212480596464771725504108699004737253589415478568924797","seed":112363705728822119990892212480596464771725504108699004737253589415478568924797,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.703000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"42.chip_sw_all_escalation_resets.53830916967143212974257729549753587714801595230333600850281820934529841390031","seed":53830916967143212974257729549753587714801595230333600850281820934529841390031,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.599000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"43.chip_sw_all_escalation_resets.5799810326383060426543371467156042943836151280151822913818139296505238281674","seed":5799810326383060426543371467156042943836151280151822913818139296505238281674,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.771000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"44.chip_sw_all_escalation_resets.36613839785443603323999375051931418853781857550323055257998460487863516058489","seed":36613839785443603323999375051931418853781857550323055257998460487863516058489,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.614000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"45.chip_sw_all_escalation_resets.45364256987340341650050725914760276253239452728556790541623341983366754258474","seed":45364256987340341650050725914760276253239452728556790541623341983366754258474,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.667000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"46.chip_sw_all_escalation_resets.94709971334195856699821430182451984794742735071520223678807914411640912761985","seed":94709971334195856699821430182451984794742735071520223678807914411640912761985,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.634000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"47.chip_sw_all_escalation_resets.50125892698407558930098161444412055666808866689024128825148896247017323377621","seed":50125892698407558930098161444412055666808866689024128825148896247017323377621,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.689000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"49.chip_sw_all_escalation_resets.2187171312547981324971202035791505299857354271407937436066504786937095191294","seed":2187171312547981324971202035791505299857354271407937436066504786937095191294,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.650000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"50.chip_sw_all_escalation_resets.69446603332248815261229108511238894021141110347723501361348236831150289923998","seed":69446603332248815261229108511238894021141110347723501361348236831150289923998,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.765000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"51.chip_sw_all_escalation_resets.15743934997431087025832001588116064266214186767340354414627030984181718717223","seed":15743934997431087025832001588116064266214186767340354414627030984181718717223,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.561000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"52.chip_sw_all_escalation_resets.3065161051434930967142830418310591482468726010275818023057640435580732395073","seed":3065161051434930967142830418310591482468726010275818023057640435580732395073,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.470000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"53.chip_sw_all_escalation_resets.59499216190558449313640218067552127929405441719145936403249291179741276794035","seed":59499216190558449313640218067552127929405441719145936403249291179741276794035,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.768000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"54.chip_sw_all_escalation_resets.77546612661342934561449657491586425035174174544045504382459443060981406336106","seed":77546612661342934561449657491586425035174174544045504382459443060981406336106,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.491000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"55.chip_sw_all_escalation_resets.83146417896958728158156098334346865643131847228997485508586226124106189183809","seed":83146417896958728158156098334346865643131847228997485508586226124106189183809,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"56.chip_sw_all_escalation_resets.9913167163623486927553390237067442038768876296922591074581034494071544044004","seed":9913167163623486927553390237067442038768876296922591074581034494071544044004,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.721000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"57.chip_sw_all_escalation_resets.61958322527032491481769054336790219344466799528132141449038486564917625814937","seed":61958322527032491481769054336790219344466799528132141449038486564917625814937,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.541000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"59.chip_sw_all_escalation_resets.1538749857560107050562617559531006908366480963341446501535988590198219300205","seed":1538749857560107050562617559531006908366480963341446501535988590198219300205,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.661000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"60.chip_sw_all_escalation_resets.78728108677102806075353772255065844821484431448296624732131990347067689143975","seed":78728108677102806075353772255065844821484431448296624732131990347067689143975,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.848000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"61.chip_sw_all_escalation_resets.24132312200701384901983414038661040716387835585906867039699650669863545956592","seed":24132312200701384901983414038661040716387835585906867039699650669863545956592,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.699000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"62.chip_sw_all_escalation_resets.68701207870403334605842464285647352399846561386372339099941110951698514513501","seed":68701207870403334605842464285647352399846561386372339099941110951698514513501,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.619000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"63.chip_sw_all_escalation_resets.83191722677879612225855687423295038794944205467000063155115131891620689099649","seed":83191722677879612225855687423295038794944205467000063155115131891620689099649,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.590000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"64.chip_sw_all_escalation_resets.93472591647406072026938761067014877869024857072418525690250820994346301293604","seed":93472591647406072026938761067014877869024857072418525690250820994346301293604,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.595000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"66.chip_sw_all_escalation_resets.60905208585765010697191161715269726891700371919629165057289048479246797158970","seed":60905208585765010697191161715269726891700371919629165057289048479246797158970,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"67.chip_sw_all_escalation_resets.91418662153448987626266106519834566890691245664007957856251134103920892696546","seed":91418662153448987626266106519834566890691245664007957856251134103920892696546,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.743000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"68.chip_sw_all_escalation_resets.3909348695042074518426035215112691849967405552812060300919687626424217169418","seed":3909348695042074518426035215112691849967405552812060300919687626424217169418,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.770000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"69.chip_sw_all_escalation_resets.1428002698573484257657953844168558437598854492552451983977341964923774029183","seed":1428002698573484257657953844168558437598854492552451983977341964923774029183,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.587000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"70.chip_sw_all_escalation_resets.26333022249067638186634021344097271867337689676855047694467450836852097068682","seed":26333022249067638186634021344097271867337689676855047694467450836852097068682,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.543000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"71.chip_sw_all_escalation_resets.67307109607333869723462412273450166352940364538210979275237808057081181579684","seed":67307109607333869723462412273450166352940364538210979275237808057081181579684,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.657000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"72.chip_sw_all_escalation_resets.111124265388418310940174552745195920253054550914245272390990753748020303258102","seed":111124265388418310940174552745195920253054550914245272390990753748020303258102,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.608000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"73.chip_sw_all_escalation_resets.77336217597486633516671236294701107808227100849660620763765262635315572954505","seed":77336217597486633516671236294701107808227100849660620763765262635315572954505,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"74.chip_sw_all_escalation_resets.61774974550495342428174570167520497594689636061222548164979447243804645528896","seed":61774974550495342428174570167520497594689636061222548164979447243804645528896,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.723000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"75.chip_sw_all_escalation_resets.6743038298053057790458676069837542446383786306391554664515626214088912365589","seed":6743038298053057790458676069837542446383786306391554664515626214088912365589,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.670000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"76.chip_sw_all_escalation_resets.12538331712619726004254493359410664964890983649312238659888584231357523351884","seed":12538331712619726004254493359410664964890983649312238659888584231357523351884,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"77.chip_sw_all_escalation_resets.99270817716242752333558731119497656802089235931278403443574245966531590154433","seed":99270817716242752333558731119497656802089235931278403443574245966531590154433,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.784000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"78.chip_sw_all_escalation_resets.77185285471560537786277838823228896005360294888283032669012264932873107676397","seed":77185285471560537786277838823228896005360294888283032669012264932873107676397,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.622000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"80.chip_sw_all_escalation_resets.89949150115932727579348798646297254864164905286910436630431101283522478702335","seed":89949150115932727579348798646297254864164905286910436630431101283522478702335,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.586000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"81.chip_sw_all_escalation_resets.65750268544253038042997848859169497219826325489537158330334724655567149264204","seed":65750268544253038042997848859169497219826325489537158330334724655567149264204,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.590000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"82.chip_sw_all_escalation_resets.69606131425370229454338544284094108277951694036091494979672588735764316569399","seed":69606131425370229454338544284094108277951694036091494979672588735764316569399,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.516000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"83.chip_sw_all_escalation_resets.90600458276015991963265342839636310251013970970612036333567345698174243751537","seed":90600458276015991963265342839636310251013970970612036333567345698174243751537,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.693000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"84.chip_sw_all_escalation_resets.12928687665906324337095231514889601024250687486407579727863120229666302349277","seed":12928687665906324337095231514889601024250687486407579727863120229666302349277,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"85.chip_sw_all_escalation_resets.40917528004103279076450957171514230666102228048681470930526414319151523214531","seed":40917528004103279076450957171514230666102228048681470930526414319151523214531,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.683000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"86.chip_sw_all_escalation_resets.113223072310430646616465880622710484297306382985272182752053990602845684474133","seed":113223072310430646616465880622710484297306382985272182752053990602845684474133,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.637000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"87.chip_sw_all_escalation_resets.49156321179905896902868428416300678567662249323017073501146586033184267055196","seed":49156321179905896902868428416300678567662249323017073501146586033184267055196,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.767000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"88.chip_sw_all_escalation_resets.6659106766420423975170036157932699960499104975000135742091912337735363715531","seed":6659106766420423975170036157932699960499104975000135742091912337735363715531,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.639000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"90.chip_sw_all_escalation_resets.67462064321342123110677963013171195985414293451113566518893268584897317997494","seed":67462064321342123110677963013171195985414293451113566518893268584897317997494,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.676000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"91.chip_sw_all_escalation_resets.79677938844839482794178609706772708037500327489267740039909485893588835216723","seed":79677938844839482794178609706772708037500327489267740039909485893588835216723,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.634000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"92.chip_sw_all_escalation_resets.69439863822921363613950893696645719134451810289185099369847086912998612475741","seed":69439863822921363613950893696645719134451810289185099369847086912998612475741,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.618000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"93.chip_sw_all_escalation_resets.44136760586117566200057437065696754339191473210054501212017097500261129964296","seed":44136760586117566200057437065696754339191473210054501212017097500261129964296,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 944.182000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"94.chip_sw_all_escalation_resets.85905868533512582356999575174642422279620361104215190076414015629427398343138","seed":85905868533512582356999575174642422279620361104215190076414015629427398343138,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"96.chip_sw_all_escalation_resets.104181120702189818121124866041126850861886883185273045601321193037254498738489","seed":104181120702189818121124866041126850861886883185273045601321193037254498738489,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.642000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"98.chip_sw_all_escalation_resets.4311739734836450661352448190485631610714111827990999535369483384427448917146","seed":4311739734836450661352448190485631610714111827990999535369483384427448917146,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.709000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"99.chip_sw_all_escalation_resets.108458975981374263006295362451260446348992334137706448645993385915451311271538","seed":108458975981374263006295362451260446348992334137706448645993385915451311271538,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.569000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.38192716020113745604962037807197969276665241021924930835034812002750715432169","seed":38192716020113745604962037807197969276665241021924930835034812002750715432169,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"1.chip_sw_rstmgr_rst_cnsty_escalation.82215205027382193224474829835821052381702269577459557480624793061130387519731","seed":82215205027382193224474829835821052381702269577459557480624793061130387519731,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"2.chip_sw_rstmgr_rst_cnsty_escalation.112586883832272348382719835785880480943522292250003170485299463591248746654050","seed":112586883832272348382719835785880480943522292250003170485299463591248746654050,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_spi_device_pass_through","qual_name":"0.chip_sw_spi_device_pass_through.65552619373685596741715063216117134428544028813523282537258763596233869790188","seed":65552619373685596741715063216117134428544028813523282537258763596233869790188,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.56158428249265636185018640566280205324749498525260915772160226079786667300916","seed":56158428249265636185018640566280205324749498525260915772160226079786667300916,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"chip_sw_spi_device_pass_through","qual_name":"1.chip_sw_spi_device_pass_through.106728588345273338935872512057102744301625819287518471128131610617792915775165","seed":106728588345273338935872512057102744301625819287518471128131610617792915775165,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"4.xbar_access_same_device_slow_rsp.87660752036692308601964882487481128603053316245135897367722414017128977038619","seed":87660752036692308601964882487481128603053316245135897367722414017128977038619,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"23.xbar_access_same_device_slow_rsp.84183279399827166571672691544718473099199080156530934026224087484840750071006","seed":84183279399827166571672691544718473099199080156530934026224087484840750071006,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"24.xbar_access_same_device_slow_rsp.48126649673968878395621370795963804205434971970908482062176072443660489348872","seed":48126649673968878395621370795963804205434971970908482062176072443660489348872,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"27.xbar_access_same_device_slow_rsp.107950339427691627141531847145552554225442128127038760960385405381978869098746","seed":107950339427691627141531847145552554225442128127038760960385405381978869098746,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"27.xbar_stress_all_with_rand_reset.26699190061607129902033930269952022610656518585590975747859925278404815860661","seed":26699190061607129902033930269952022610656518585590975747859925278404815860661,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"28.xbar_stress_all_with_rand_reset.42955291536289484344329466268189843703997562750816024278275407066319493441576","seed":42955291536289484344329466268189843703997562750816024278275407066319493441576,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"29.xbar_stress_all_with_rand_reset.103083470732937546081402182422346816258943604890785114680533755417088668421040","seed":103083470732937546081402182422346816258943604890785114680533755417088668421040,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"30.xbar_access_same_device_slow_rsp.79975024033281683784003074589716710169838304363940609180731026758791148363494","seed":79975024033281683784003074589716710169838304363940609180731026758791148363494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"43.xbar_access_same_device_slow_rsp.1881056788608001012759003800639240370301336434932374557821456316801549698700","seed":1881056788608001012759003800639240370301336434932374557821456316801549698700,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"44.xbar_access_same_device_slow_rsp.70807227877525588260966220921544542953843656979613477809639364794818812169275","seed":70807227877525588260966220921544542953843656979613477809639364794818812169275,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"45.xbar_access_same_device_slow_rsp.91619962278746217215979763670664162007965862541572978226160229229555567986890","seed":91619962278746217215979763670664162007965862541572978226160229229555567986890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"49.xbar_access_same_device_slow_rsp.30343209553873072092221913881604588882353576356756108043137046534161982607991","seed":30343209553873072092221913881604588882353576356756108043137046534161982607991,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.93595155393982825242211803691872976461717747657178652915026735759854253672638","seed":93595155393982825242211803691872976461717747657178652915026735759854253672638,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 245.992000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.53490238628519661533341593315883737479881416651323765626257209949710713450798","seed":53490238628519661533341593315883737479881416651323765626257209949710713450798,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 364.113000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.109989872634735296380321687667276446711082317091725578905271797757299735329793","seed":109989872634735296380321687667276446711082317091725578905271797757299735329793,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 226.080000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.77321197330707316472899750909689402419671645031344489396695918661192638185215","seed":77321197330707316472899750909689402419671645031344489396695918661192638185215,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 177.024000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 177.024000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"19.chip_sw_all_escalation_resets.12098325598963117150143554721962915181395825763713289446743032097898833680792","seed":12098325598963117150143554721962915181395825763713289446743032097898833680792,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 176.892000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 176.892000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"48.chip_sw_all_escalation_resets.40416943880611490373663586462530934417541304301260688920310185659009939368416","seed":40416943880611490373663586462530934417541304301260688920310185659009939368416,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 176.924000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 176.924000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"95.chip_sw_all_escalation_resets.95398491820955231566730830289182079274024303846889861931329247185090602277609","seed":95398491820955231566730830289182079274024303846889861931329247185090602277609,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 176.832000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 176.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"97.chip_sw_all_escalation_resets.50860280848251192426921660472246720625945432207260757495251422103020516284450","seed":50860280848251192426921660472246720625945432207260757495251422103020516284450,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 176.856000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 176.856000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_lc_ctrl_rma_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rma_to_scrap.29125404239326384035068636112410260116685314678667826061689814011133198129748","seed":29125404239326384035068636112410260116685314678667826061689814011133198129748,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 165.160000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 165.160000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_raw_to_scrap","qual_name":"0.chip_sw_lc_ctrl_raw_to_scrap.111931710786794244862333151701306143503655410688828200581535712872618026348768","seed":111931710786794244862333151701306143503655410688828200581535712872618026348768,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 174.488000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 174.488000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_test_locked0_to_scrap","qual_name":"0.chip_sw_lc_ctrl_test_locked0_to_scrap.42637585924278376716938877314262671020046409460170123901345712107774543873765","seed":42637585924278376716938877314262671020046409460170123901345712107774543873765,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 168.920000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 168.920000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rand_to_scrap.62288685791725478533633463184806077221537511356219348173657347214748942335375","seed":62288685791725478533633463184806077221537511356219348173657347214748942335375,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 170.328000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 170.328000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock.12112585616682321609560146689706828238017321028675382192188126835281267387112","seed":12112585616682321609560146689706828238017321028675382192188126835281267387112,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_ERROR @ 478.472000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 478.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.11227083418408093039101884262433381721665374194908450745323360771091144750402","seed":11227083418408093039101884262433381721665374194908450745323360771091144750402,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["UVM_ERROR @ 374.392000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 374.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.66946494281317946814122587663698391587614057773693346931957676477248030349075","seed":66946494281317946814122587663698391587614057773693346931957676477248030349075,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 118.472000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 118.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"0.chip_sw_rom_ctrl_integrity_check.938595892480087980280112532219726424597219321664768668524129873538800566103","seed":938595892480087980280112532219726424597219321664768668524129873538800566103,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["UVM_ERROR @ 157.240000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 157.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_prim_tl_access","qual_name":"0.chip_prim_tl_access.103775914231818127997126705666546954226001961640211166356021195251435757460140","seed":103775914231818127997126705666546954226001961640211166356021195251435757460140,"line":240,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log","log_context":["UVM_ERROR @ 117.288000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 117.288000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.38567674542370069778426199649481233701556161601660803228630945022282431840","seed":38567674542370069778426199649481233701556161601660803228630945022282431840,"line":223,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_ERROR @ 130.648000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 130.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"1.chip_sw_lc_ctrl_rand_to_scrap.110890965972527327564760533765787490391310632104452241992487067923766091268880","seed":110890965972527327564760533765787490391310632104452241992487067923766091268880,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 170.200000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 170.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"1.chip_sw_lc_ctrl_volatile_raw_unlock.25573090608112951420080944169057097606352769179211578825300040127714943210599","seed":25573090608112951420080944169057097606352769179211578825300040127714943210599,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_ERROR @ 549.832000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 549.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.13812596506253258173410973881726877725157806375282194131863499848683303221148","seed":13812596506253258173410973881726877725157806375282194131863499848683303221148,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["UVM_ERROR @ 372.728000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 372.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.79149297325351507396995001118437557746218635331228695347718716825961945741685","seed":79149297325351507396995001118437557746218635331228695347718716825961945741685,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 118.448000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 118.448000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"1.chip_sw_rom_ctrl_integrity_check.45644768306629839952584962239656805624556415082025227975482218807288712888602","seed":45644768306629839952584962239656805624556415082025227975482218807288712888602,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["UVM_ERROR @ 157.288000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 157.288000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_prim_tl_access","qual_name":"1.chip_prim_tl_access.80182079838703981942572392747358872259460119057323463213684277244074965697340","seed":80182079838703981942572392747358872259460119057323463213684277244074965697340,"line":240,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_prim_tl_access/latest/run.log","log_context":["UVM_ERROR @ 117.768000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 117.768000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.31338558336975116066920917401061130401967516326413303620567767927343613361163","seed":31338558336975116066920917401061130401967516326413303620567767927343613361163,"line":223,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_ERROR @ 122.760000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 122.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"2.chip_sw_lc_ctrl_rand_to_scrap.8333036341835322599950798776651134674964347907236510252008809141586761617056","seed":8333036341835322599950798776651134674964347907236510252008809141586761617056,"line":339,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 171.608000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 171.608000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"2.chip_sw_lc_ctrl_volatile_raw_unlock.72935869170460841264785270573177463377304190287385156582324653555197145504013","seed":72935869170460841264785270573177463377304190287385156582324653555197145504013,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_ERROR @ 448.744000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 448.744000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.13992598286514397269978910691053186244353499302797250752359069896062010216764","seed":13992598286514397269978910691053186244353499302797250752359069896062010216764,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["UVM_ERROR @ 336.904000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 336.904000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.45774456875998501559547669852892050448989597536853581812224046275445011290007","seed":45774456875998501559547669852892050448989597536853581812224046275445011290007,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 118.472000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 118.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"2.chip_sw_rom_ctrl_integrity_check.62351732916590042080720926581820923336097151641734091244290236240982454455886","seed":62351732916590042080720926581820923336097151641734091244290236240982454455886,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["UVM_ERROR @ 157.256000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 157.256000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_prim_tl_access","qual_name":"2.chip_prim_tl_access.55139049486278811206770720656981265055111420293541770197924319359301322469387","seed":55139049486278811206770720656981265055111420293541770197924319359301322469387,"line":245,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log","log_context":["UVM_ERROR @ 118.360000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 118.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_rstmgr_alert_info","qual_name":"0.chip_sw_rstmgr_alert_info.5805117977477463945781659069175559813697469746488525220235663339679658028640","seed":5805117977477463945781659069175559813697469746488525220235663339679658028640,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_INFO @ 331.119000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"1.chip_sw_rstmgr_alert_info.80635159938910280275129155449317068945133966203742525272716410904571074309496","seed":80635159938910280275129155449317068945133966203742525272716410904571074309496,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_INFO @ 331.203000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"2.chip_sw_rstmgr_alert_info.19868896956794286001140458358122290407812111548585043405500788157656967975446","seed":19868896956794286001140458358122290407812111548585043405500788157656967975446,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_INFO @ 331.221000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((!rstreqs[*]) && (reset_cause != HwReq))'":[{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.10455537601374065615510410096309562877934729803264714025771098828112270915309","seed":10455537601374065615510410096309562877934729803264714025771098828112270915309,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["UVM_ERROR @ 412.000000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 412.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"0.chip_sw_clkmgr_off_aes_trans.97003123124702940886357417239015202938795228779822878998490306665667558684522","seed":97003123124702940886357417239015202938795228779822878998490306665667558684522,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["UVM_ERROR @ 185.408000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.408000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"0.chip_sw_clkmgr_off_hmac_trans.96247355754275328413422065598031612621150041300230373935276349716223993502151","seed":96247355754275328413422065598031612621150041300230373935276349716223993502151,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.248000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"0.chip_sw_clkmgr_off_kmac_trans.42949552610245844808420745198653476609336290335623791700778894869979510294711","seed":42949552610245844808420745198653476609336290335623791700778894869979510294711,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"0.chip_sw_clkmgr_off_otbn_trans.114586798333961291773751216934933377909384954515593201342262539639815192804376","seed":114586798333961291773751216934933377909384954515593201342262539639815192804376,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["UVM_ERROR @ 185.360000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"1.chip_sw_rstmgr_cpu_info.17361770323363899120934287616765550038808268373131276497079028369672431040505","seed":17361770323363899120934287616765550038808268373131276497079028369672431040505,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["UVM_ERROR @ 411.856000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 411.856000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"1.chip_sw_clkmgr_off_aes_trans.41681483850142780144503533687008865423969991508599917428280594298247567535602","seed":41681483850142780144503533687008865423969991508599917428280594298247567535602,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["UVM_ERROR @ 185.248000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"1.chip_sw_clkmgr_off_hmac_trans.38200806421528849683639489697159410373342886038494669456476646837168915588159","seed":38200806421528849683639489697159410373342886038494669456476646837168915588159,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.264000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.264000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"1.chip_sw_clkmgr_off_kmac_trans.87465613535237600223175011160307145026231991224575578843232427427425146798077","seed":87465613535237600223175011160307145026231991224575578843232427427425146798077,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.328000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.328000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"1.chip_sw_clkmgr_off_otbn_trans.73794732435735094384453368245426009460368182804846246291692105279760682201358","seed":73794732435735094384453368245426009460368182804846246291692105279760682201358,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["UVM_ERROR @ 185.312000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"2.chip_sw_rstmgr_cpu_info.101293147609481137925443332497465796717332118862670514636390738589589700874296","seed":101293147609481137925443332497465796717332118862670514636390738589589700874296,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["UVM_ERROR @ 412.064000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 412.064000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"2.chip_sw_clkmgr_off_aes_trans.87960564002227469234395449562393517143432464404377210854996818641857546854731","seed":87960564002227469234395449562393517143432464404377210854996818641857546854731,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["UVM_ERROR @ 185.360000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"2.chip_sw_clkmgr_off_hmac_trans.23450986189461034857828990890373499960197131016665620242549519391609329182833","seed":23450986189461034857828990890373499960197131016665620242549519391609329182833,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.312000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"2.chip_sw_clkmgr_off_kmac_trans.105448441389740798956825058634453503748866872201464904441660591910422945303965","seed":105448441389740798956825058634453503748866872201464904441660591910422945303965,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.360000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"2.chip_sw_clkmgr_off_otbn_trans.23966911472380968789334440325188724253887002505430492540665871027096807120992","seed":23966911472380968789334440325188724253887002505430492540665871027096807120992,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["UVM_ERROR @ 185.392000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!":[{"name":"chip_sw_soc_proxy_smoketest","qual_name":"0.chip_sw_soc_proxy_smoketest.17949994395444925921348398626216570417174672372269306488558896724674031217992","seed":17949994395444925921348398626216570417174672372269306488558896724674031217992,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_INFO @ 156.272000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"1.chip_sw_soc_proxy_smoketest.110269107279505589017903155890136568360986790018487977146882691055733552517191","seed":110269107279505589017903155890136568360986790018487977146882691055733552517191,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_INFO @ 156.224000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"2.chip_sw_soc_proxy_smoketest.20324497807960245448398150131945184635839035986419286283589538913263378672038","seed":20324497807960245448398150131945184635839035986419286283589538913263378672038,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_INFO @ 156.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *":[{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"0.chip_sw_soc_proxy_external_wakeup.24809334975795155284044984073588225959149004681184948570250865823566432623479","seed":24809334975795155284044984073588225959149004681184948570250865823566432623479,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_INFO @ 157.809000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"1.chip_sw_soc_proxy_external_wakeup.44791045706557586756036023706534436601330303149133344441550559795180416439266","seed":44791045706557586756036023706534436601330303149133344441550559795180416439266,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_INFO @ 157.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"2.chip_sw_soc_proxy_external_wakeup.27368847114097936160797602868421135965357133441827642134190209454103628881255","seed":27368847114097936160797602868421135965357133441827642134190209454103628881255,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_INFO @ 157.901000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec":[{"name":"chip_sw_aon_timer_irq","qual_name":"0.chip_sw_aon_timer_irq.30182751290292797144183616827187585337379225229264273359446885369683673127409","seed":30182751290292797144183616827187585337379225229264273359446885369683673127409,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_INFO @ 607.346000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"1.chip_sw_aon_timer_irq.115212079834020847700967984347133908413047013056603166438308993110274611937596","seed":115212079834020847700967984347133908413047013056603166438308993110274611937596,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_INFO @ 616.353000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"2.chip_sw_aon_timer_irq.85496247893793285488553404430802459508477542228772328881006347564074482638926","seed":85496247893793285488553404430802459508477542228772328881006347564074482638926,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_INFO @ 515.286000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds":[{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.22165377899018194946713303501490250537227427853455093673382050244533154238277","seed":22165377899018194946713303501490250537227427853455093673382050244533154238277,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_INFO @ 182.572000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.41317144887156018836938623223788697223176542394596958173924416867914054851289","seed":41317144887156018836938623223788697223176542394596958173924416867914054851289,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_INFO @ 182.584000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.69660120398353225645140370401084493280393120123922915458614116299828959937140","seed":69660120398353225645140370401084493280393120123922915458614116299828959937140,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_INFO @ 182.515000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (dv_utils_pkg.sv:253) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\"":[{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en.89865531058544577538547043460747627036046238535211709460631551568972771242658","seed":89865531058544577538547043460747627036046238535211709460631551568972771242658,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"0.chip_sw_aes_enc_jitter_en.21586842110347576635240378627844228012744336700957461983792320043190883140004","seed":21586842110347576635240378627844228012744336700957461983792320043190883140004,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"0.chip_sw_hmac_enc_jitter_en.50526788275401303710784438999291392966016928933682444014423561808283843182186","seed":50526788275401303710784438999291392966016928933682444014423561808283843182186,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en.66610122868954136550828729920461600236088230142203230790314243185209084886632","seed":66610122868954136550828729920461600236088230142203230790314243185209084886632,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en.71659884900901111677266126732173265727097372179889878425027821502221152691988","seed":71659884900901111677266126732173265727097372179889878425027821502221152691988,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.96496963547079550859740611731122338377951167196723462150847816491686255488496","seed":96496963547079550859740611731122338377951167196723462150847816491686255488496,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_aes_enc_jitter_en_reduced_freq.71769931585075259980146544194981069056427312462314009794944733147104470466366","seed":71769931585075259980146544194981069056427312462314009794944733147104470466366,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_hmac_enc_jitter_en_reduced_freq.30849045284491961768735278066296241825995714809730598589737037778460128937241","seed":30849045284491961768735278066296241825995714809730598589737037778460128937241,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.14633151168330555044194180958959549623041399198665689829003077805773246486432","seed":14633151168330555044194180958959549623041399198665689829003077805773246486432,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.95810641481408172191068826486316799344641963288760971991232251187937840250232","seed":95810641481408172191068826486316799344641963288760971991232251187937840250232,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2814732238377770199021593646347309386654382039585477176589655083481306727481","seed":2814732238377770199021593646347309386654382039585477176589655083481306727481,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"0.chip_sw_csrng_edn_concurrency_reduced_freq.57757205084377572204996571351868521522925789700475779405098036051934410261086","seed":57757205084377572204996571351868521522925789700475779405098036051934410261086,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"1.chip_sw_otbn_ecdsa_op_irq_jitter_en.111726810467617991111226151151818678672681713300484476622255462554919717745618","seed":111726810467617991111226151151818678672681713300484476622255462554919717745618,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"1.chip_sw_aes_enc_jitter_en.74261959509175113401675790757560649318982582038939340962938982519885710906759","seed":74261959509175113401675790757560649318982582038939340962938982519885710906759,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"1.chip_sw_hmac_enc_jitter_en.49958337461309256730615757403111322966554048388291211500106816478257786329365","seed":49958337461309256730615757403111322966554048388291211500106816478257786329365,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"1.chip_sw_keymgr_dpe_key_derivation_jitter_en.22566798179672023072364147656386225358367644228544226367600602375991224133379","seed":22566798179672023072364147656386225358367644228544226367600602375991224133379,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"1.chip_sw_kmac_mode_kmac_jitter_en.80084544158450960703609255224822534223352053014328843748951256967442591754545","seed":80084544158450960703609255224822534223352053014328843748951256967442591754545,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.35468680588337542960739788518280739671599954962555185074623117476189955846731","seed":35468680588337542960739788518280739671599954962555185074623117476189955846731,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"1.chip_sw_aes_enc_jitter_en_reduced_freq.53205913533640460001718841722330302722568033355001902727325936274038764288361","seed":53205913533640460001718841722330302722568033355001902727325936274038764288361,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"1.chip_sw_hmac_enc_jitter_en_reduced_freq.22453774081250190113179673217505044404712488246616231951056691198903783869480","seed":22453774081250190113179673217505044404712488246616231951056691198903783869480,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"1.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.2548010786064632749691685161547250094476055504749572620307523721533332497292","seed":2548010786064632749691685161547250094476055504749572620307523721533332497292,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.55238058387133064358316481049702977759429308413306636992105093117570395955005","seed":55238058387133064358316481049702977759429308413306636992105093117570395955005,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.92230832195757374380818789489869552243596890405663876331042398579633993294235","seed":92230832195757374380818789489869552243596890405663876331042398579633993294235,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"1.chip_sw_csrng_edn_concurrency_reduced_freq.90776779557961299100159858078414921999798430661886986885889173690926584157423","seed":90776779557961299100159858078414921999798430661886986885889173690926584157423,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2415605459709270591229158498608666832672828625901079969629033441753092290703","seed":2415605459709270591229158498608666832672828625901079969629033441753092290703,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"2.chip_sw_aes_enc_jitter_en.41452274257184813760497330103171888877618863935479493885582283152526107750152","seed":41452274257184813760497330103171888877618863935479493885582283152526107750152,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"2.chip_sw_hmac_enc_jitter_en.112277554303524250498035211437849307974109655985347128529577285888697714101751","seed":112277554303524250498035211437849307974109655985347128529577285888697714101751,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"2.chip_sw_keymgr_dpe_key_derivation_jitter_en.36914922526745475369935152815103878359547835071986467161533994904209487303773","seed":36914922526745475369935152815103878359547835071986467161533994904209487303773,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"2.chip_sw_kmac_mode_kmac_jitter_en.107369543918543101775246747564253163337513080838083483954454356753404231922885","seed":107369543918543101775246747564253163337513080838083483954454356753404231922885,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.82475179544442158490836830341323792212969642236595983683925936373905654727918","seed":82475179544442158490836830341323792212969642236595983683925936373905654727918,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"2.chip_sw_aes_enc_jitter_en_reduced_freq.110486838842500599739546995396633678972409114354362850757963901667419323256146","seed":110486838842500599739546995396633678972409114354362850757963901667419323256146,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"2.chip_sw_hmac_enc_jitter_en_reduced_freq.69059238744343847718361798125910544050763341549008156446430901984496643435152","seed":69059238744343847718361798125910544050763341549008156446430901984496643435152,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"2.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.83379720291103347368413994147396992738887543531350436955730689073147097996667","seed":83379720291103347368413994147396992738887543531350436955730689073147097996667,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1848263837228291344109843580397584831748188698364904361672042209126302329395","seed":1848263837228291344109843580397584831748188698364904361672042209126302329395,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.114789879289643613394712089066134732689125672313229457892744173522426393491154","seed":114789879289643613394712089066134732689125672313229457892744173522426393491154,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"2.chip_sw_csrng_edn_concurrency_reduced_freq.49315186059469641462552781672912185398855959785546598137393707136368924541915","seed":49315186059469641462552781672912185398855959785546598137393707136368924541915,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired":[{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"0.chip_sw_rv_core_ibex_nmi_irq.38057785724838440432454269966222991031122891274766005375031100645921325647258","seed":38057785724838440432454269966222991031122891274766005375031100645921325647258,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_INFO @ 269.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"1.chip_sw_rv_core_ibex_nmi_irq.115769377696400109722892115405204179435726199288259208901126069085702007909965","seed":115769377696400109722892115405204179435726199288259208901126069085702007909965,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_INFO @ 269.444000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"2.chip_sw_rv_core_ibex_nmi_irq.90829842468862297471709410078862914562543693201168645356896875586227882021384","seed":90829842468862297471709410078862914562543693201168645356896875586227882021384,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_INFO @ 269.337000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:618) scoreboard [scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.27553323161771650931367265519558473019658046572378756036597977958926205230438","seed":27553323161771650931367265519558473019658046572378756036597977958926205230438,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32075) { a_addr: 'h1465310  a_data: 'ha7898990  a_mask: 'h8  a_size: 'h2  a_param: 'h0  a_source: 'hdb  a_opcode: 'h1  a_user: 'h26adc  d_param: 'h0  d_source: 'hdb  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.772000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.233219937401039572591467812697286092404007813058939316801702339753883754449","seed":233219937401039572591467812697286092404007813058939316801702339753883754449,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32205) { a_addr: 'h1465010  a_data: 'h3eba37a5  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'hc9  a_opcode: 'h1  a_user: 'h26339  d_param: 'h0  d_source: 'hc9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.093000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.73415562184557805790772869768735102395724460688848226739962863872727628016415","seed":73415562184557805790772869768735102395724460688848226739962863872727628016415,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32453) { a_addr: 'h1465414  a_data: 'hd9e16364  a_mask: 'h2  a_size: 'h1  a_param: 'h0  a_source: 'h8  a_opcode: 'h1  a_user: 'h26d40  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.156000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.34132372294243759750338169466358975914412215511748058638485206263920625396217","seed":34132372294243759750338169466358975914412215511748058638485206263920625396217,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31293) { a_addr: 'h1465310  a_data: 'hcbcaec86  a_mask: 'h1  a_size: 'h1  a_param: 'h0  a_source: 'hd4  a_opcode: 'h1  a_user: 'h278bf  d_param: 'h0  d_source: 'hd4  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.773000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.98948775325200668939873989268680899105509540400125129704336882835392303679083","seed":98948775325200668939873989268680899105509540400125129704336882835392303679083,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32019) { a_addr: 'h1460114  a_data: 'h47bfba83  a_mask: 'hd  a_size: 'h2  a_param: 'h0  a_source: 'he7  a_opcode: 'h1  a_user: 'h24f1d  d_param: 'h0  d_source: 'he7  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.110000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.89183501129101032169666105644685943595755659876656552001727356803108279150755","seed":89183501129101032169666105644685943595755659876656552001727356803108279150755,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31687) { a_addr: 'h1496010  a_data: 'hd9d3134f  a_mask: 'h3  a_size: 'h2  a_param: 'h0  a_source: 'hee  a_opcode: 'h1  a_user: 'h26967  d_param: 'h0  d_source: 'hee  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.756000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.4311880202111161531036610579507880106861304586886686422703668666840093705020","seed":4311880202111161531036610579507880106861304586886686422703668666840093705020,"line":242,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31705) { a_addr: 'h1465314  a_data: 'h34805adb  a_mask: 'h3  a_size: 'h1  a_param: 'h0  a_source: 'h4c  a_opcode: 'h1  a_user: 'h271d1  d_param: 'h0  d_source: 'h4c  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.722000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.80196923340304348668978337655723983134116785338694921043079286852832981378041","seed":80196923340304348668978337655723983134116785338694921043079286852832981378041,"line":242,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31673) { a_addr: 'h1460114  a_data: 'hdb5a81e6  a_mask: 'h2  a_size: 'h1  a_param: 'h0  a_source: 'h1f  a_opcode: 'h1  a_user: 'h25166  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.796000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.24546839877952668330185126535599272819826766288017462823640798616098649684101","seed":24546839877952668330185126535599272819826766288017462823640798616098649684101,"line":242,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32381) { a_addr: 'h1465114  a_data: 'hf8b5905c  a_mask: 'h6  a_size: 'h2  a_param: 'h0  a_source: 'h50  a_opcode: 'h1  a_user: 'h2709f  d_param: 'h0  d_source: 'h50  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.181000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.69517587975584158738362300044570442955640910474713254095814919759818515747254","seed":69517587975584158738362300044570442955640910474713254095814919759818515747254,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31977) { a_addr: 'h1465010  a_data: 'h42d6b092  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'haa  a_opcode: 'h1  a_user: 'h27760  d_param: 'h0  d_source: 'haa  d_data: 'h0  d_size: 'h0  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h152a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.778000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.24943483726121915353690732219935146475486656993803085323853145825851275474356","seed":24943483726121915353690732219935146475486656993803085323853145825851275474356,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31919) { a_addr: 'h1465214  a_data: 'h9eb143fc  a_mask: 'hd  a_size: 'h2  a_param: 'h0  a_source: 'had  a_opcode: 'h1  a_user: 'h26b2f  d_param: 'h0  d_source: 'had  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.111000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.46372136120289913132497986192427079242579139190031630522120797129184451931055","seed":46372136120289913132497986192427079242579139190031630522120797129184451931055,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31913) { a_addr: 'h1465214  a_data: 'h25e91193  a_mask: 'h4  a_size: 'h2  a_param: 'h0  a_source: 'hcd  a_opcode: 'h1  a_user: 'h27975  d_param: 'h0  d_source: 'hcd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.761000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.79261896145109573402795491794163227077593374146887459566757525605066316175915","seed":79261896145109573402795491794163227077593374146887459566757525605066316175915,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31433) { a_addr: 'h1460110  a_data: 'h59ce2120  a_mask: 'h1  a_size: 'h0  a_param: 'h0  a_source: 'h20  a_opcode: 'h0  a_user: 'h27a13  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h0  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h152a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (jtag_riscv_driver.sv:221) [jtag_riscv_agent_pkg] Check failed sbcs_val[SbAccess32] == * (* [*] vs * [*]) expect SBA width to be * bits!":[{"name":"chip_jtag_csr_rw","qual_name":"0.chip_jtag_csr_rw.114320325149738882214248107184591827682749465365422516934436506046820600512440","seed":114320325149738882214248107184591827682749465365422516934436506046820600512440,"line":5962,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_INFO @ 131.815000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_mem_access","qual_name":"0.chip_jtag_mem_access.40222946547321713048358443709286989977716437849055329038055563318521786672163","seed":40222946547321713048358443709286989977716437849055329038055563318521786672163,"line":5962,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log","log_context":["UVM_INFO @ 132.656000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_csr_rw","qual_name":"1.chip_jtag_csr_rw.1928233721375510842442119925078245573321239670428462919365192063553618250613","seed":1928233721375510842442119925078245573321239670428462919365192063553618250613,"line":5962,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_INFO @ 131.626000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_mem_access","qual_name":"1.chip_jtag_mem_access.52095219145858726585777606664930641451266896846779129978860922251531497934312","seed":52095219145858726585777606664930641451266896846779129978860922251531497934312,"line":5962,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log","log_context":["UVM_INFO @ 132.418000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_csr_rw","qual_name":"2.chip_jtag_csr_rw.69376518568422694230715035306203113971192058263656022102182627019783592638311","seed":69376518568422694230715035306203113971192058263656022102182627019783592638311,"line":5967,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_INFO @ 131.144000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_mem_access","qual_name":"2.chip_jtag_mem_access.101019211394784698380771184509043220331053477264953516122690840521488618226834","seed":101019211394784698380771184509043220331053477264953516122690840521488618226834,"line":5967,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest/run.log","log_context":["UVM_INFO @ 131.839000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[CNST-CIF] Constraints inconsistency failure":[{"name":"chip_padctrl_attributes","qual_name":"0.chip_padctrl_attributes.79021870666550919382347091610792946357667303620134540963816791536724062026088","seed":79021870666550919382347091610792946357667303620134540963816791536724062026088,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"1.chip_padctrl_attributes.86589355411203487555226697166070866535507845249435821643971542030365213536163","seed":86589355411203487555226697166070866535507845249435821643971542030365213536163,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"2.chip_padctrl_attributes.5555289635586799410908369535344080694510856603808132545405043120365165667660","seed":5555289635586799410908369535344080694510856603808132545405043120365165667660,"line":292,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"3.chip_padctrl_attributes.4820345411655695139544025370754358979161388991784794519718721599674639148202","seed":4820345411655695139544025370754358979161388991784794519718721599674639148202,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"4.chip_padctrl_attributes.43149442509223030850470269366281323663461950373319411465787839177554302234465","seed":43149442509223030850470269366281323663461950373319411465787839177554302234465,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"5.chip_padctrl_attributes.30578749137773097878671829778092135152047345944650342614222602029465844486342","seed":30578749137773097878671829778092135152047345944650342614222602029465844486342,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"6.chip_padctrl_attributes.13907351623931224375985641561588978450601286891087860496031325503717784419901","seed":13907351623931224375985641561588978450601286891087860496031325503717784419901,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"7.chip_padctrl_attributes.83947803606373613392466341093607970905978203314173032722224901260544542958898","seed":83947803606373613392466341093607970905978203314173032722224901260544542958898,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"8.chip_padctrl_attributes.104572943183688953024905106089164733412720986972078959026704526015605307987387","seed":104572943183688953024905106089164733412720986972078959026704526015605307987387,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"9.chip_padctrl_attributes.59580649202743760104896425522780312403157281472767448250374610978373235218176","seed":59580649202743760104896425522780312403157281472767448250374610978373235218176,"line":287,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == *":[{"name":"chip_sw_dma_abort","qual_name":"0.chip_sw_dma_abort.113748324075853759445765412466423706492023635082220062114384048260748723507441","seed":113748324075853759445765412466423706492023635082220062114384048260748723507441,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log","log_context":["UVM_INFO @ 211.836000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_dma_abort","qual_name":"1.chip_sw_dma_abort.59705772499139172994923012352409867384355962341726066888339831988680487825414","seed":59705772499139172994923012352409867384355962341726066888339831988680487825414,"line":331,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log","log_context":["UVM_INFO @ 211.779000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == *":[{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"1.chip_sw_rv_core_ibex_rnd.95778080727832440592477088352736340511769613672401734860363303262681334784075","seed":95778080727832440592477088352736340511769613672401734860363303262681334784075,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["UVM_INFO @ 198.250000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"2.chip_sw_rv_core_ibex_rnd.115171664976184899716799181533340480074423740124819088286982203846716135609397","seed":115171664976184899716799181533340480074423740124819088286982203846716135609397,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["UVM_INFO @ 179.807000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:618) scoreboard [scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.83446029929006979060384981422455470122374198810394259964073934365961928490459","seed":83446029929006979060384981422455470122374198810394259964073934365961928490459,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31783) { a_addr: 'h2214  a_data: 'h3484026d  a_mask: 'hd  a_size: 'h2  a_param: 'h0  a_source: 'hfe  a_opcode: 'h1  a_user: 'h25f36  d_param: 'h0  d_source: 'hfe  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.093000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.15657027527280335897577028629484138614116118024539179542017786809190565710588","seed":15657027527280335897577028629484138614116118024539179542017786809190565710588,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32295) { a_addr: 'h2214  a_data: 'h10c67913  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'hef  a_opcode: 'h1  a_user: 'h2509b  d_param: 'h0  d_source: 'hef  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.87604985189776116350605753290934285679168058134564935038175446808767293976699","seed":87604985189776116350605753290934285679168058134564935038175446808767293976699,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31507) { a_addr: 'h2214  a_data: 'he86688cb  a_mask: 'hb  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h1  a_user: 'h25360  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.758000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.18245822016536918684835519647434278997289105651109705980125182206770774688242","seed":18245822016536918684835519647434278997289105651109705980125182206770774688242,"line":237,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31593) { a_addr: 'h2214  a_data: 'h7ba612f8  a_mask: 'h3  a_size: 'h1  a_param: 'h0  a_source: 'he0  a_opcode: 'h0  a_user: 'h26324  d_param: 'h0  d_source: 'he0  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.970000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)'":[{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.11855590549892529749214250153403566675136777684230592662458015980100547606357","seed":11855590549892529749214250153403566675136777684230592662458015980100547606357,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.053000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.053000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.20886440116773037998617063974109171793078563205441336460920747147892071437070","seed":20886440116773037998617063974109171793078563205441336460920747147892071437070,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.017000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.017000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.98840429581531993843972441316438906230270006095574549369454778104407981704907","seed":98840429581531993843972441316438906230270006095574549369454778104407981704907,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.033000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.033000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.57335566918635380500985225863560832411979320454860950453658972069695608554575","seed":57335566918635380500985225863560832411979320454860950453658972069695608554575,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.068000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.12385617963070979585135133403316223909456794832243657103565882699611590006417","seed":12385617963070979585135133403316223909456794832243657103565882699611590006417,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.081000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.081000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.37034440830195976853516472929957610053433741646406935537641121851362605626775","seed":37034440830195976853516472929957610053433741646406935537641121851362605626775,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.035000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.035000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.48645280855723983502272839621585374950062745742045715594176892166241487129149","seed":48645280855723983502272839621585374950062745742045715594176892166241487129149,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.963000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.963000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.105020973014425110960455807829645202783335106006582860045936338658024759938013","seed":105020973014425110960455807829645202783335106006582860045936338658024759938013,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.103000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.103000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.94189790316552789468056313411467940154626390417360509963304519699218332521988","seed":94189790316552789468056313411467940154626390417360509963304519699218332521988,"line":243,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.104000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.104000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.71075665069932223000575238753215972898966308616826773899471488892032326780837","seed":71075665069932223000575238753215972898966308616826773899471488892032326780837,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.988000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.96075358367620851354871119688448212343963350721349284185166808359465024929751","seed":96075358367620851354871119688448212343963350721349284185166808359465024929751,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.787000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.787000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.47543535571500825141778681840327515130211684955230886132175880265433643494471","seed":47543535571500825141778681840327515130211684955230886132175880265433643494471,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.091000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.091000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.66442123936992446193197780999397460564378447314844462765186499755636695915317","seed":66442123936992446193197780999397460564378447314844462765186499755636695915317,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.056000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.056000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.83188697321069904319173257522008263795909429214946185870123106844338817030281","seed":83188697321069904319173257522008263795909429214946185870123106844338817030281,"line":222,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 123.185000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().":[{"name":"chip_sw_dma_abort","qual_name":"2.chip_sw_dma_abort.42687933067028870034655633147391164980716509676954736301373248415818066134935","seed":42687933067028870034655633147391164980716509676954736301373248415818066134935,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log","log_context":["UVM_INFO @ 173.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"30.chip_sw_all_escalation_resets.112500974999120284943813656638832161215778261713604761340442003850897349797867","seed":112500974999120284943813656638832161215778261713604761340442003850897349797867,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 177.511000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"65.chip_sw_all_escalation_resets.94010844195722751251416751158699431987832446950127103818870346107448603006548","seed":94010844195722751251416751158699431987832446950127103818870346107448603006548,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 177.588000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"79.chip_sw_all_escalation_resets.69171045264023765443024184276474062966516475193008528610177555554856378740566","seed":69171045264023765443024184276474062966516475193008528610177555554856378740566,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 177.544000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:933) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert uart0_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"58.chip_sw_all_escalation_resets.84638375894937442739408987208450223122216858760523008920525743631260516253128","seed":84638375894937442739408987208450223122216858760523008920525743631260516253128,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 178.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"89.chip_sw_all_escalation_resets.85374977617389521174550821838814903919841943237193526697411240063343032068835","seed":85374977617389521174550821838814903919841943237193526697411240063343032068835,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 179.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1062,"total":1742,"percent":60.96440872560276}