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(uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_same_csr_outstanding","qual_name":"0.chip_same_csr_outstanding.39284011781780301442480842684913653253902290725333100131612244681896297155673","seed":39284011781780301442480842684913653253902290725333100131612244681896297155673,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest run_opts='+test_timeout_ns=120_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790102617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1790102617' seed=39284011781780301442480842684913653253902290725333100131612244681896297155673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39284011781780301442480842684913653253902290725333100131612244681896297155673 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_rom","qual_name":"0.chip_sw_example_rom.106113920653864739666617950830894155444689144347509021756789728603024360413163","seed":106113920653864739666617950830894155444689144347509021756789728603024360413163,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3053131755 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.3053131755' seed=106113920653864739666617950830894155444689144347509021756789728603024360413163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:example_test_from_rom:0:test_in_rom'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106113920653864739666617950830894155444689144347509021756789728603024360413163 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images=//sw/device/tests:example_test_from_rom:0:test_in_rom uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"0.chip_sw_example_manufacturer.44338212737328544055004877700518511656444479560499985247762709368998971235312","seed":44338212737328544055004877700518511656444479560499985247762709368998971235312,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1533205488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1533205488' seed=44338212737328544055004877700518511656444479560499985247762709368998971235312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44338212737328544055004877700518511656444479560499985247762709368998971235312 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_concurrency","qual_name":"0.chip_sw_example_concurrency.34177476592678312205442394559689672667957659989761021870325528806028218763052","seed":34177476592678312205442394559689672667957659989761021870325528806028218763052,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest run_opts='+sw_build_device=sim_dv +sw_images=example_concurrency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=499418924 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.499418924' seed=34177476592678312205442394559689672667957659989761021870325528806028218763052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34177476592678312205442394559689672667957659989761021870325528806028218763052 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"0.chip_sw_all_escalation_resets.64825319412485414189865704192953940295725548150009008428668862339208830942172","seed":64825319412485414189865704192953940295725548150009008428668862339208830942172,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3065150428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3065150428' seed=64825319412485414189865704192953940295725548150009008428668862339208830942172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64825319412485414189865704192953940295725548150009008428668862339208830942172 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.36878032924896273061107046872137215330863794752283202952660064060363973826985","seed":36878032924896273061107046872137215330863794752283202952660064060363973826985,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3114768809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3114768809' seed=36878032924896273061107046872137215330863794752283202952660064060363973826985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36878032924896273061107046872137215330863794752283202952660064060363973826985 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rstmgr_cnsty_fault_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"0.chip_sw_data_integrity_escalation.55228158018625947866984441186053371938730657624344006426980390800921154587482","seed":55228158018625947866984441186053371938730657624344006426980390800921154587482,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395324762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3395324762' seed=55228158018625947866984441186053371938730657624344006426980390800921154587482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55228158018625947866984441186053371938730657624344006426980390800921154587482 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_data_integrity_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.49629513062786089896578018707151707288989887116694907529951912786174069130099","seed":49629513062786089896578018707151707288989887116694907529951912786174069130099,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest run_opts='+use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2774745971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2774745971' seed=49629513062786089896578018707151707288989887116694907529951912786174069130099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sleep_pin_wake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49629513062786089896578018707151707288989887116694907529951912786174069130099 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sleep_pin_wake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sleep_pin_wake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"0.chip_sw_sleep_pin_retention.108866924368318123477064215795386588547742406932492461673652865123946720322602","seed":108866924368318123477064215795386588547742406932492461673652865123946720322602,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest run_opts='+sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175277610 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.3175277610' seed=108866924368318123477064215795386588547742406932492461673652865123946720322602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sleep_pin_retention_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108866924368318123477064215795386588547742406932492461673652865123946720322602 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sleep_pin_retention_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sleep_pin_retention_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"0.chip_sw_uart_tx_rx.26032131600708601683634338749395750266120161826417923085773458219289936982147","seed":26032131600708601683634338749395750266120161826417923085773458219289936982147,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest run_opts='+uart_idx=0 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1962995843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1962995843' seed=26032131600708601683634338749395750266120161826417923085773458219289936982147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26032131600708601683634338749395750266120161826417923085773458219289936982147 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"0.chip_sw_uart_tx_rx_bootstrap.39740135371030347344556301534719652769593437903583486607932614445220584374817","seed":39740135371030347344556301534719652769593437903583486607932614445220584374817,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.664s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"0.chip_sw_inject_scramble_seed.76144214270944989382530046217072245244108665224813875767584925096702033819825","seed":76144214270944989382530046217072245244108665224813875767584925096702033819825,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.195s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"0.chip_sw_exit_test_unlocked_bootstrap.15122206513252369286362354161159936224330876267217289529000927409412770261302","seed":15122206513252369286362354161159936224330876267217289529000927409412770261302,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.468s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"0.chip_sw_uart_rand_baudrate.110796254785278512016358441403889098132881238426847510415236304856877255470252","seed":110796254785278512016358441403889098132881238426847510415236304856877255470252,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4290096300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.4290096300' seed=110796254785278512016358441403889098132881238426847510415236304856877255470252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110796254785278512016358441403889098132881238426847510415236304856877255470252 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"0.chip_sw_uart_tx_rx_alt_clk_freq.31999676972520327924607883288447277185152783153766468404071874436504241387484","seed":31999676972520327924607883288447277185152783153766468404071874436504241387484,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest run_opts='+sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2737649628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq.2737649628' seed=31999676972520327924607883288447277185152783153766468404071874436504241387484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31999676972520327924607883288447277185152783153766468404071874436504241387484 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"0.chip_sw_i2c_host_tx_rx.102328398055936444059100902845581039238171542806830347216162346836042513165750","seed":102328398055936444059100902845581039238171542806830347216162346836042513165750,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest run_opts='+i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3029642678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3029642678' seed=102328398055936444059100902845581039238171542806830347216162346836042513165750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:i2c_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102328398055936444059100902845581039238171542806830347216162346836042513165750 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:i2c_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_i2c_host_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"0.chip_sw_i2c_device_tx_rx.51437036083322067830456119194577026843431876059090147837080156565161058843859","seed":51437036083322067830456119194577026843431876059090147837080156565161058843859,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest run_opts='+sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=746405075 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.746405075' seed=51437036083322067830456119194577026843431876059090147837080156565161058843859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:i2c_device_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51437036083322067830456119194577026843431876059090147837080156565161058843859 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:i2c_device_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_i2c_device_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"0.chip_sw_spi_device_tpm.70447038763821070316941849614692494934306559191220593756178516157543782936006","seed":70447038763821070316941849614692494934306559191220593756178516157543782936006,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=173665734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.173665734' seed=70447038763821070316941849614692494934306559191220593756178516157543782936006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:spi_device_tpm_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70447038763821070316941849614692494934306559191220593756178516157543782936006 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:spi_device_tpm_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_device_tpm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"0.chip_sw_spi_host_tx_rx.101286923786048048826333033221711558015914904018446671601396780363971875747494","seed":101286923786048048826333033221711558015914904018446671601396780363971875747494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=511358630 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.511358630' seed=101286923786048048826333033221711558015914904018446671601396780363971875747494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101286923786048048826333033221711558015914904018446671601396780363971875747494 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_host_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_pass_through","qual_name":"0.chip_sw_spi_device_pass_through.73292070937172001829214653411918255015839530043685423785677197505634600788854","seed":73292070937172001829214653411918255015839530043685423785677197505634600788854,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_passthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3935871862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3935871862' seed=73292070937172001829214653411918255015839530043685423785677197505634600788854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73292070937172001829214653411918255015839530043685423785677197505634600788854 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_passthrough_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.34606565323527968139230275455305453597865541634700261106269188843822572153432","seed":34606565323527968139230275455305453597865541634700261106269188843822572153432,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_passthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653544536 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3653544536' seed=34606565323527968139230275455305453597865541634700261106269188843822572153432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34606565323527968139230275455305453597865541634700261106269188843822572153432 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_passthrough_collision_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_gpio","qual_name":"0.chip_sw_gpio.83217236670848083889845015080139433021615038598526378182616167464918193358717","seed":83217236670848083889845015080139433021615038598526378182616167464918193358717,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio/latest run_opts='+sw_build_device=sim_dv +sw_images=gpio_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2845919101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio.2845919101' seed=83217236670848083889845015080139433021615038598526378182616167464918193358717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:gpio_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83217236670848083889845015080139433021615038598526378182616167464918193358717 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:gpio_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_gpio_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_entropy","qual_name":"0.chip_sw_kmac_entropy.43574698922835444092730271688674826670425346791264127960637284599051273109970","seed":43574698922835444092730271688674826670425346791264127960637284599051273109970,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_entropy/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237661650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_entropy.2237661650' seed=43574698922835444092730271688674826670425346791264127960637284599051273109970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43574698922835444092730271688674826670425346791264127960637284599051273109970 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"0.chip_sw_lc_ctrl_otp_hw_cfg.105918058261006921658234460581550411270003281969134917167481319811376955415784","seed":105918058261006921658234460581550411270003281969134917167481319811376955415784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771882728 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg.3771882728' seed=105918058261006921658234460581550411270003281969134917167481319811376955415784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:lc_ctrl_otp_hw_cfg_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105918058261006921658234460581550411270003281969134917167481319811376955415784 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:lc_ctrl_otp_hw_cfg_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.26638421229576382233174329761254062464539581089809327306930869911626930956640","seed":26638421229576382233174329761254062464539581089809327306930869911626930956640,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest run_opts='+use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220258144 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1220258144' seed=26638421229576382233174329761254062464539581089809327306930869911626930956640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26638421229576382233174329761254062464539581089809327306930869911626930956640 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"0.chip_sw_otp_ctrl_lc_signals_dev.19044400041372501562720854154521436438714541230950941581186761320885334122937","seed":19044400041372501562720854154521436438714541230950941581186761320885334122937,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest run_opts='+use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744801209 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3744801209' seed=19044400041372501562720854154521436438714541230950941581186761320885334122937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19044400041372501562720854154521436438714541230950941581186761320885334122937 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"0.chip_sw_otp_ctrl_lc_signals_prod.82157476834321247062751712626229234763318236356766077492802986115423057881834","seed":82157476834321247062751712626229234763318236356766077492802986115423057881834,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest run_opts='+use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2326670058 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.2326670058' seed=82157476834321247062751712626229234763318236356766077492802986115423057881834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82157476834321247062751712626229234763318236356766077492802986115423057881834 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.94378222729570669912024902304164035734224822265816258536955839886868381329133","seed":94378222729570669912024902304164035734224822265816258536955839886868381329133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest run_opts='+use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3161351917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3161351917' seed=94378222729570669912024902304164035734224822265816258536955839886868381329133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94378222729570669912024902304164035734224822265816258536955839886868381329133 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"0.chip_sw_otp_ctrl_vendor_test_csr_access.33078515342505763669395553328936356994533318952696292967513404947742397889782","seed":33078515342505763669395553328936356994533318952696292967513404947742397889782,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest run_opts='+sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1140653302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1140653302' seed=33078515342505763669395553328936356994533318952696292967513404947742397889782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33078515342505763669395553328936356994533318952696292967513404947742397889782 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_otp_ctrl_vendor_test_csr_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.113466195070526512750205249534582408838987511649303417208652933343131610793866","seed":113466195070526512750205249534582408838987511649303417208652933343131610793866,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659258762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1659258762' seed=113466195070526512750205249534582408838987511649303417208652933343131610793866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113466195070526512750205249534582408838987511649303417208652933343131610793866 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_otp_ctrl_escalation_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_nvm_cnt","qual_name":"0.chip_sw_otp_ctrl_nvm_cnt.68689012400460399844162387443481853024434824696789720836239893897989045103597","seed":68689012400460399844162387443481853024434824696789720836239893897989045103597,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_nvm_cnt/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_sw_parts","qual_name":"0.chip_sw_otp_ctrl_sw_parts.61877878292145250861249343490853361482879736688251856924072709788585893765990","seed":61877878292145250861249343490853361482879736688251856924072709788585893765990,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_sw_parts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=384658) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"0.chip_sw_lc_ctrl_transition.94747559204093656586748736318711558970390375403267374978890986586467710070603","seed":94747559204093656586748736318711558970390375403267374978890986586467710070603,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868440907 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2868440907' seed=94747559204093656586748736318711558970390375403267374978890986586467710070603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94747559204093656586748736318711558970390375403267374978890986586467710070603 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_rma_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rma_to_scrap.83011072644344611310791097728317138957284172815698402838960556721255841817063","seed":83011072644344611310791097728317138957284172815698402838960556721255841817063,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest run_opts='+bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3994837479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3994837479' seed=83011072644344611310791097728317138957284172815698402838960556721255841817063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83011072644344611310791097728317138957284172815698402838960556721255841817063 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_scrap_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_raw_to_scrap","qual_name":"0.chip_sw_lc_ctrl_raw_to_scrap.67694017897305817207324642227868907151851073935315682477355699653337121537499","seed":67694017897305817207324642227868907151851073935315682477355699653337121537499,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest run_opts='+bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3805789659 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.3805789659' seed=67694017897305817207324642227868907151851073935315682477355699653337121537499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67694017897305817207324642227868907151851073935315682477355699653337121537499 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_scrap_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_test_locked0_to_scrap","qual_name":"0.chip_sw_lc_ctrl_test_locked0_to_scrap.16690545817512065640621097696594638672395011435502990293746067501652687811742","seed":16690545817512065640621097696594638672395011435502990293746067501652687811742,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest run_opts='+bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=582841502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.582841502' seed=16690545817512065640621097696594638672395011435502990293746067501652687811742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16690545817512065640621097696594638672395011435502990293746067501652687811742 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_scrap_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rand_to_scrap.99606524449532056701188937917867677053975307674200363704236954213011368363970","seed":99606524449532056701188937917867677053975307674200363704236954213011368363970,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=836421570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.836421570' seed=99606524449532056701188937917867677053975307674200363704236954213011368363970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99606524449532056701188937917867677053975307674200363704236954213011368363970 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_scrap_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.75258453287259622498274741773765882451809691283477754192713812415463833346715","seed":75258453287259622498274741773765882451809691283477754192713812415463833346715,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.501s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.44844236702065545933282489026582401394658632034027526459129523169602249314432","seed":44844236702065545933282489026582401394658632034027526459129523169602249314432,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.658s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"0.chip_sw_lc_walkthrough_prodend.34863490792512834557721950965889384074417484576175317877812507369033996812372","seed":34863490792512834557721950965889384074417484576175317877812507369033996812372,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest run_opts='+flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371127892 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1371127892' seed=34863490792512834557721950965889384074417484576175317877812507369033996812372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_walkthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34863490792512834557721950965889384074417484576175317877812507369033996812372 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_walkthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_walkthrough_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock.39585825812761180856443607819342587673412462279931639338559020355516644838083","seed":39585825812761180856443607819342587673412462279931639338559020355516644838083,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest run_opts='+use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3564227267 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3564227267' seed=39585825812761180856443607819342587673412462279931639338559020355516644838083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39585825812761180856443607819342587673412462279931639338559020355516644838083 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_volatile_raw_unlock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.5113007932985714786631804863186943614883626184395270335470402580874198801588","seed":5113007932985714786631804863186943614883626184395270335470402580874198801588,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest run_opts='+use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2062834868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2062834868' seed=5113007932985714786631804863186943614883626184395270335470402580874198801588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5113007932985714786631804863186943614883626184395270335470402580874198801588 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_volatile_raw_unlock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.111798498728900739061779848341019467486910042250242802270746190061211799872343","seed":111798498728900739061779848341019467486910042250242802270746190061211799872343,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.538s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.115106570627627920907445293217762065215422769539717280414610330553317173185337","seed":115106570627627920907445293217762065215422769539717280414610330553317173185337,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest run_opts='+use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=477580089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunlocks.477580089' seed=115106570627627920907445293217762065215422769539717280414610330553317173185337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=115106570627627920907445293217762065215422769539717280414610330553317173185337 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_walkthrough_testunlocks_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_sw_req","qual_name":"0.chip_sw_rstmgr_sw_req.103416556985470452252760467785597985480852035877341207350167656827706346094247","seed":103416556985470452252760467785597985480852035877341207350167656827706346094247,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2875244199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_req.2875244199' seed=103416556985470452252760467785597985480852035877341207350167656827706346094247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_sw_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103416556985470452252760467785597985480852035877341207350167656827706346094247 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_sw_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_sw_rst","qual_name":"0.chip_sw_rstmgr_sw_rst.100133172105829779434180062949031823778299161218909706395195049279437426306299","seed":100133172105829779434180062949031823778299161218909706395195049279437426306299,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1855106299 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1855106299' seed=100133172105829779434180062949031823778299161218909706395195049279437426306299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_sw_rst_ctrl_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100133172105829779434180062949031823778299161218909706395195049279437426306299 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_sw_rst_ctrl_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"0.chip_sw_rstmgr_alert_info.31071834887318994610693083985700122001900127610884227844835173682919857686591","seed":31071834887318994610693083985700122001900127610884227844835173682919857686591,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest run_opts='+sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1532463167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1532463167' seed=31071834887318994610693083985700122001900127610884227844835173682919857686591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_alert_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31071834887318994610693083985700122001900127610884227844835173682919857686591 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_alert_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.30217948739236114724819606867285987569140916083681940965419546985741467810121","seed":30217948739236114724819606867285987569140916083681940965419546985741467810121,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest run_opts='+sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2133883209 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2133883209' seed=30217948739236114724819606867285987569140916083681940965419546985741467810121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_cpu_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30217948739236114724819606867285987569140916083681940965419546985741467810121 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_cpu_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.73296549967750706085809378462939343039330108731216747298123051102254357195149","seed":73296549967750706085809378462939343039330108731216747298123051102254357195149,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2759502221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2759502221' seed=73296549967750706085809378462939343039330108731216747298123051102254357195149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73296549967750706085809378462939343039330108731216747298123051102254357195149 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_full_aon_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_main_power_glitch_reset.22506270356281073058423381225736351098502806181377048752891614370400744742211","seed":22506270356281073058423381225736351098502806181377048752891614370400744742211,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2146671939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2146671939' seed=22506270356281073058423381225736351098502806181377048752891614370400744742211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22506270356281073058423381225736351098502806181377048752891614370400744742211 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_main_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.829647778001363126088836864982236014382832305785816219244407277745917348983","seed":829647778001363126088836864982236014382832305785816219244407277745917348983,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2424523895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2424523895' seed=829647778001363126088836864982236014382832305785816219244407277745917348983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=829647778001363126088836864982236014382832305785816219244407277745917348983 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_main_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.49265161506411519184513925278177499878226522040935282341378717928279982829433","seed":49265161506411519184513925278177499878226522040935282341378717928279982829433,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982323577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3982323577' seed=49265161506411519184513925278177499878226522040935282341378717928279982829433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49265161506411519184513925278177499878226522040935282341378717928279982829433 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_deep_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.95981846435660886413399970586107189534227185788640322685568395699271733552841","seed":95981846435660886413399970586107189534227185788640322685568395699271733552841,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3146720969 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3146720969' seed=95981846435660886413399970586107189534227185788640322685568395699271733552841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95981846435660886413399970586107189534227185788640322685568395699271733552841 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_random_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"0.chip_sw_pwrmgr_sleep_disabled.68266855083926299911979029137003312330835046045224469459781677141724813228679","seed":68266855083926299911979029137003312330835046045224469459781677141724813228679,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest run_opts='+sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2886367879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2886367879' seed=68266855083926299911979029137003312330835046045224469459781677141724813228679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:pwrmgr_sleep_disabled_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68266855083926299911979029137003312330835046045224469459781677141724813228679 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:pwrmgr_sleep_disabled_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_timer_irq","qual_name":"0.chip_sw_rv_timer_irq.2174849113728032655075246664858999344797997161588193364659895190709200104278","seed":2174849113728032655075246664858999344797997161588193364659895190709200104278,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4144376662 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_timer_irq.4144376662' seed=2174849113728032655075246664858999344797997161588193364659895190709200104278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2174849113728032655075246664858999344797997161588193364659895190709200104278 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"0.chip_sw_soc_proxy_smoketest.94542024966257521850775203523869086781717245854572232657648722441710110474813","seed":94542024966257521850775203523869086781717245854572232657648722441710110474813,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869237309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_soc_proxy_smoketest.869237309' seed=94542024966257521850775203523869086781717245854572232657648722441710110474813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94542024966257521850775203523869086781717245854572232657648722441710110474813 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"0.chip_sw_soc_proxy_external_wakeup.24817143615854960422916790042775438526464434197672814890419740042914497130265","seed":24817143615854960422916790042775438526464434197672814890419740042914497130265,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_external_wakeup:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1007775513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_external_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_soc_proxy_external_wakeup.1007775513' seed=24817143615854960422916790042775438526464434197672814890419740042914497130265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_external_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24817143615854960422916790042775438526464434197672814890419740042914497130265 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_external_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_external_wakeup_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_gpios","qual_name":"0.chip_sw_soc_proxy_gpios.90574612690819066172427024434739778620715635654540275527482370052219518941492","seed":90574612690819066172427024434739778620715635654540275527482370052219518941492,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_gpios:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3178068276 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_soc_proxy_gpios.3178068276' seed=90574612690819066172427024434739778620715635654540275527482370052219518941492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_gpios:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90574612690819066172427024434739778620715635654540275527482370052219518941492 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_gpios:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_gpio_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"0.chip_sw_aon_timer_irq.53849652534478482207036421921447279045092963755267584870314940941780622619195","seed":53849652534478482207036421921447279045092963755267584870314940941780622619195,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1354609211 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1354609211' seed=53849652534478482207036421921447279045092963755267584870314940941780622619195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53849652534478482207036421921447279045092963755267584870314940941780622619195 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_sleep_wdog_sleep_pause","qual_name":"0.chip_sw_aon_timer_sleep_wdog_sleep_pause.5765137150257745979702417639046152581807689271414229821713432625536042362454","seed":5765137150257745979702417639046152581807689271414229821713432625536042362454,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641033814 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.641033814' seed=5765137150257745979702417639046152581807689271414229821713432625536042362454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5765137150257745979702417639046152581807689271414229821713432625536042362454 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.81575829924571882775132449335176906284175834567668682981536501807685206539652","seed":81575829924571882775132449335176906284175834567668682981536501807685206539652,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest run_opts='+sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4107009412 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.4107009412' seed=81575829924571882775132449335176906284175834567668682981536501807685206539652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_wdog_bite_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81575829924571882775132449335176906284175834567668682981536501807685206539652 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_wdog_bite_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"0.chip_sw_pwrmgr_wdog_reset.20832203414830762002404771079634714543180074815174143415813838535328217414252","seed":20832203414830762002404771079634714543180074815174143415813838535328217414252,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251116140 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.251116140' seed=20832203414830762002404771079634714543180074815174143415813838535328217414252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:pwrmgr_wdog_reset_reqs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20832203414830762002404771079634714543180074815174143415813838535328217414252 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:pwrmgr_wdog_reset_reqs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_wdog_lc_escalate","qual_name":"0.chip_sw_aon_timer_wdog_lc_escalate.93502930291895025190084714630498001996178151122834699433662872825128509416802","seed":93502930291895025190084714630498001996178151122834699433662872825128509416802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423511906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3423511906' seed=93502930291895025190084714630498001996178151122834699433662872825128509416802 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_wdog_lc_escalate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93502930291895025190084714630498001996178151122834699433662872825128509416802 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_wdog_lc_escalate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_randomness","qual_name":"0.chip_sw_otbn_randomness.92357373477628670228705071775937740077870621982374376613171437771957065395786","seed":92357373477628670228705071775937740077870621982374376613171437771957065395786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_randomness/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_randomness/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_randomness/latest run_opts='+sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1450094154 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1450094154' seed=92357373477628670228705071775937740077870621982374376613171437771957065395786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_randomness_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92357373477628670228705071775937740077870621982374376613171437771957065395786 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_randomness/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_randomness_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_mem_scramble","qual_name":"0.chip_sw_otbn_mem_scramble.66447323187393116676801105471140239396411524789645530095468578237552867860353","seed":66447323187393116676801105471140239396411524789645530095468578237552867860353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest run_opts='+sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1487593345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1487593345' seed=66447323187393116676801105471140239396411524789645530095468578237552867860353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_mem_scramble_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66447323187393116676801105471140239396411524789645530095468578237552867860353 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_mem_scramble_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"0.chip_sw_rv_core_ibex_rnd.45857199830170849224007107740407969739601231873454665744520080652396342403210","seed":45857199830170849224007107740407969739601231873454665744520080652396342403210,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest run_opts='+sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197858954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1197858954' seed=45857199830170849224007107740407969739601231873454665744520080652396342403210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_rnd_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45857199830170849224007107740407969739601231873454665744520080652396342403210 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_rnd_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"0.chip_sw_rv_core_ibex_nmi_irq.51736646085525580807480550178753677161928330026072559970923408246530355906274","seed":51736646085525580807480550178753677161928330026072559970923408246530355906274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest run_opts='+sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446818530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3446818530' seed=51736646085525580807480550178753677161928330026072559970923408246530355906274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_nmi_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51736646085525580807480550178753677161928330026072559970923408246530355906274 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_nmi_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc","qual_name":"0.chip_sw_aes_enc.111561105567998870945616737545079079725307469024374870800568357842407834768749","seed":111561105567998870945616737545079079725307469024374870800568357842407834768749,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc/latest run_opts='+sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1416615277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1416615277' seed=111561105567998870945616737545079079725307469024374870800568357842407834768749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111561105567998870945616737545079079725307469024374870800568357842407834768749 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"0.chip_sw_aes_enc_jitter_en.60410734166865976552355391946139957141584865078779862783385177712742917416485","seed":60410734166865976552355391946139957141584865078779862783385177712742917416485,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest run_opts='+sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422941221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2422941221' seed=60410734166865976552355391946139957141584865078779862783385177712742917416485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60410734166865976552355391946139957141584865078779862783385177712742917416485 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_gcm","qual_name":"0.chip_sw_aes_gcm.96568435965356854402080025083897448482719984650705235777347022074966733574689","seed":96568435965356854402080025083897448482719984650705235777347022074966733574689,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_gcm/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_gcm/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_gcm/latest run_opts='+sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_gcm_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176930337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_gcm.2176930337' seed=96568435965356854402080025083897448482719984650705235777347022074966733574689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_gcm_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96568435965356854402080025083897448482719984650705235777347022074966733574689 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_gcm/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_gcm_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_idle","qual_name":"0.chip_sw_aes_idle.26851117439505659535404577052878677855760113849527429056132051160125302502351","seed":26851117439505659535404577052878677855760113849527429056132051160125302502351,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_idle/latest run_opts='+sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2397172687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2397172687' seed=26851117439505659535404577052878677855760113849527429056132051160125302502351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26851117439505659535404577052878677855760113849527429056132051160125302502351 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_masking_off","qual_name":"0.chip_sw_aes_masking_off.111698838841336324481779789384618076956654667991127709760985020525771284450377","seed":111698838841336324481779789384618076956654667991127709760985020525771284450377,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_masking_off/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_masking_off/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_masking_off/latest run_opts='+sw_build_device=sim_dv +sw_images=aes_masking_off_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1105890377 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.1105890377' seed=111698838841336324481779789384618076956654667991127709760985020525771284450377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_masking_off_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111698838841336324481779789384618076956654667991127709760985020525771284450377 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_masking_off/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_masking_off_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_aes_masking_off_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.86521874079203906355279127919540892701625635982843966505403281648576798357961","seed":86521874079203906355279127919540892701625635982843966505403281648576798357961,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest run_opts='+sw_build_device=sim_dv +sw_images=alert_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362510793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_test.362510793' seed=86521874079203906355279127919540892701625635982843966505403281648576798357961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/autogen/top_darjeeling:alert_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86521874079203906355279127919540892701625635982843966505403281648576798357961 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/autogen/top_darjeeling:alert_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"0.chip_sw_alert_handler_escalation.44712688807503389695540676038382138406315470613612991098146319459312620091468","seed":44712688807503389695540676038382138406315470613612991098146319459312620091468,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=808532044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.808532044' seed=44712688807503389695540676038382138406315470613612991098146319459312620091468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44712688807503389695540676038382138406315470613612991098146319459312620091468 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_alert_handler_escalation_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_ping_timeout","qual_name":"0.chip_sw_alert_handler_ping_timeout.8157445719735150003112347721220582769724287796165412130310723143235738982675","seed":8157445719735150003112347721220582769724287796165412130310723143235738982675,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest run_opts='+en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1816844563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1816844563' seed=8157445719735150003112347721220582769724287796165412130310723143235738982675 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_ping_timeout_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8157445719735150003112347721220582769724287796165412130310723143235738982675 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_ping_timeout_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.98390946236940815162407583945232349889425098920516524704563063630542010916983","seed":98390946236940815162407583945232349889425098920516524704563063630542010916983,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.166s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.11152696137072420869141616265289133369780408297702944769995822305296647090683","seed":11152696137072420869141616265289133369780408297702944769995822305296647090683,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=287194) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.19866406191848530221881062764938610393195599774397349729846698156881965925667","seed":19866406191848530221881062764938610393195599774397349729846698156881965925667,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.177s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"0.chip_sw_alert_handler_lpg_clkoff.24684074532113251688359176006911501734243041958851260389889941761069877604528","seed":24684074532113251688359176006911501734243041958851260389889941761069877604528,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.656s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"0.chip_sw_alert_handler_lpg_reset_toggle.109816285209613616617151389786795396902585520353401866308187984988842401062720","seed":109816285209613616617151389786795396902585520353401866308187984988842401062720,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.226s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.10177584066277973361795100904700510186525981130224071505421827204673056963235","seed":10177584066277973361795100904700510186525981130224071505421827204673056963235,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=237927075 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.237927075' seed=10177584066277973361795100904700510186525981130224071505421827204673056963235 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:alert_handler_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10177584066277973361795100904700510186525981130224071505421827204673056963235 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:alert_handler_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_alert_handler_entropy_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_entropy","qual_name":"0.chip_sw_aes_entropy.55890137422885823130332601556634668719826630772610242505483320075076666276547","seed":55890137422885823130332601556634668719826630772610242505483320075076666276547,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=460470979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.460470979' seed=55890137422885823130332601556634668719826630772610242505483320075076666276547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55890137422885823130332601556634668719826630772610242505483320075076666276547 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_kat_test","qual_name":"0.chip_sw_csrng_kat_test.1860585049921566549777212446558350023335549742215233875974509084198458378821","seed":1860585049921566549777212446558350023335549742215233875974509084198458378821,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1178094149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1178094149' seed=1860585049921566549777212446558350023335549742215233875974509084198458378821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:csrng_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1860585049921566549777212446558350023335549742215233875974509084198458378821 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:csrng_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.5616680493589209256492937021929189741073134883275378476786079105535845568278","seed":5616680493589209256492937021929189741073134883275378476786079105535845568278,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1751093014 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1751093014' seed=5616680493589209256492937021929189741073134883275378476786079105535845568278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5616680493589209256492937021929189741073134883275378476786079105535845568278 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_csrng","qual_name":"0.chip_sw_entropy_src_csrng.34076493575963664943876709522032800128306943197561286134431521142627318983066","seed":34076493575963664943876709522032800128306943197561286134431521142627318983066,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest run_opts='+sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=969238938 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.969238938' seed=34076493575963664943876709522032800128306943197561286134431521142627318983066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_csrng_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34076493575963664943876709522032800128306943197561286134431521142627318983066 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_csrng_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_kat_test","qual_name":"0.chip_sw_entropy_src_kat_test.77447198508322060825025790585420747761641439857612192853688747580393849715755","seed":77447198508322060825025790585420747761641439857612192853688747580393849715755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2421521451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2421521451' seed=77447198508322060825025790585420747761641439857612192853688747580393849715755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77447198508322060825025790585420747761641439857612192853688747580393849715755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_ast_rng_req","qual_name":"0.chip_sw_entropy_src_ast_rng_req.50330557299742313265901936613497828673561963011349014873571927865713501545193","seed":50330557299742313265901936613497828673561963011349014873571927865713501545193,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2922521321 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2922521321' seed=50330557299742313265901936613497828673561963011349014873571927865713501545193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_ast_rng_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50330557299742313265901936613497828673561963011349014873571927865713501545193 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_ast_rng_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc","qual_name":"0.chip_sw_hmac_enc.14851410815469750461244546311718917787677425779217973049582665588676293333407","seed":14851410815469750461244546311718917787677425779217973049582665588676293333407,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1744081311 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1744081311' seed=14851410815469750461244546311718917787677425779217973049582665588676293333407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14851410815469750461244546311718917787677425779217973049582665588676293333407 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"0.chip_sw_hmac_enc_jitter_en.84947600497982412158472075902374521130733599909413865929269650927677375090939","seed":84947600497982412158472075902374521130733599909413865929269650927677375090939,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest run_opts='+en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1746768123 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1746768123' seed=84947600497982412158472075902374521130733599909413865929269650927677375090939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84947600497982412158472075902374521130733599909413865929269650927677375090939 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_idle","qual_name":"0.chip_sw_hmac_enc_idle.97160749688207373194435012173411418254619526685179306898249175605595806032725","seed":97160749688207373194435012173411418254619526685179306898249175605595806032725,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2384126805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_idle.2384126805' seed=97160749688207373194435012173411418254619526685179306898249175605595806032725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97160749688207373194435012173411418254619526685179306898249175605595806032725 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_cshake","qual_name":"0.chip_sw_kmac_mode_cshake.85636460670835611684909644850322969231849446748406929663719406701658850925449","seed":85636460670835611684909644850322969231849446748406929663719406701658850925449,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835370377 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3835370377' seed=85636460670835611684909644850322969231849446748406929663719406701658850925449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_cshake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85636460670835611684909644850322969231849446748406929663719406701658850925449 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_cshake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac","qual_name":"0.chip_sw_kmac_mode_kmac.94161304330093839608611933010351628924125924100978638626831101441184662972228","seed":94161304330093839608611933010351628924125924100978638626831101441184662972228,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2689230660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac.2689230660' seed=94161304330093839608611933010351628924125924100978638626831101441184662972228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94161304330093839608611933010351628924125924100978638626831101441184662972228 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en.114324862397666482678794067226909727344778079878887459060994422242065428547499","seed":114324862397666482678794067226909727344778079878887459060994422242065428547499,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest run_opts='+en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31492011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.31492011' seed=114324862397666482678794067226909727344778079878887459060994422242065428547499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114324862397666482678794067226909727344778079878887459060994422242065428547499 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"0.chip_sw_kmac_app_rom.74705422385777013652179845960624878469523532586042409470097559510412765584985","seed":74705422385777013652179845960624878469523532586042409470097559510412765584985,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_app_rom_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2024431193 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_app_rom.2024431193' seed=74705422385777013652179845960624878469523532586042409470097559510412765584985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_app_rom_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74705422385777013652179845960624878469523532586042409470097559510412765584985 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_app_rom_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_idle","qual_name":"0.chip_sw_kmac_idle.97841664985489039544897584357649813447159451254717659679791970930315376945312","seed":97841664985489039544897584357649813447159451254717659679791970930315376945312,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_idle/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2970577056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_idle.2970577056' seed=97841664985489039544897584357649813447159451254717659679791970930315376945312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97841664985489039544897584357649813447159451254717659679791970930315376945312 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"0.chip_sw_rom_ctrl_integrity_check.51478161440799872974152498672064945449103935150965134912851959158838256925805","seed":51478161440799872974152498672064945449103935150965134912851959158838256925805,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest run_opts='+sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263284845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2263284845' seed=51478161440799872974152498672064945449103935150965134912851959158838256925805 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51478161440799872974152498672064945449103935150965134912851959158838256925805 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_ctrl_integrity_check_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access","qual_name":"0.chip_sw_sram_ctrl_scrambled_access.67641249439601940825760082354942356711194960357327771147503263992968019220733","seed":67641249439601940825760082354942356711194960357327771147503263992968019220733,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest run_opts='+sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3763902717 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access.3763902717' seed=67641249439601940825760082354942356711194960357327771147503263992968019220733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67641249439601940825760082354942356711194960357327771147503263992968019220733 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en.59882105780309453750758327765607344628146958676543993385046401128741947918036","seed":59882105780309453750758327765607344628146958676543993385046401128741947918036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest run_opts='+sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2828617428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2828617428' seed=59882105780309453750758327765607344628146958676543993385046401128741947918036 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59882105780309453750758327765607344628146958676543993385046401128741947918036 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"0.chip_sw_sram_ctrl_execution_main.70351877704206574018684122330350769842644082348135997000562564159105190221087","seed":70351877704206574018684122330350769842644082348135997000562564159105190221087,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest run_opts='+sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1815237919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1815237919' seed=70351877704206574018684122330350769842644082348135997000562564159105190221087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70351877704206574018684122330350769842644082348135997000562564159105190221087 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_execution_main_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_coremark","qual_name":"0.chip_sw_coremark.97687336813846031684352199310385476452194393407671104561848949987936711742008","seed":97687336813846031684352199310385476452194393407671104561848949987936711742008,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_coremark/latest/run.log","log_context":["---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.77293377404688939744661253943036943005247863892855010716532150639522607502621","seed":77293377404688939744661253943036943005247863892855010716532150639522607502621,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809632029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2809632029' seed=77293377404688939744661253943036943005247863892855010716532150639522607502621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77293377404688939744661253943036943005247863892855010716532150639522607502621 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_prim_tl_access","qual_name":"0.chip_prim_tl_access.82729642206930652884740397957285803752577172942211925730624602067494667403420","seed":82729642206930652884740397957285803752577172942211925730624602067494667403420,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest run_opts='+en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608185500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2608185500' seed=82729642206930652884740397957285803752577172942211925730624602067494667403420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82729642206930652884740397957285803752577172942211925730624602067494667403420 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_prim_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_plic_all_irqs_0","qual_name":"0.chip_plic_all_irqs_0.56161759528310783734924421943258657059272314321140114555536523030098562252346","seed":56161759528310783734924421943258657059272314321140114555536523030098562252346,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_0/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1877212730 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_plic_all_irqs_0.1877212730' seed=56161759528310783734924421943258657059272314321140114555536523030098562252346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_0:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56161759528310783734924421943258657059272314321140114555536523030098562252346 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_0:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_plic_all_irqs_10","qual_name":"0.chip_plic_all_irqs_10.18718714889559717216347190815112550504569560518117783928762325693453194160993","seed":18718714889559717216347190815112550504569560518117783928762325693453194160993,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_10/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_10/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_10/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448878433 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_plic_all_irqs_10.2448878433' seed=18718714889559717216347190815112550504569560518117783928762325693453194160993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_10:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18718714889559717216347190815112550504569560518117783928762325693453194160993 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_plic_all_irqs_10/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_10:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_plic_sw_irq","qual_name":"0.chip_sw_plic_sw_irq.1683442189520828633290462589825681782570746260698290517142840601166539136808","seed":1683442189520828633290462589825681782570746260698290517142840601166539136808,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_sw_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=233840424 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_plic_sw_irq.233840424' seed=1683442189520828633290462589825681782570746260698290517142840601166539136808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:plic_sw_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1683442189520828633290462589825681782570746260698290517142840601166539136808 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:plic_sw_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"0.chip_sw_clkmgr_off_aes_trans.95331906708959156510296676682310085643640399850908258852784983106281451006875","seed":95331906708959156510296676682310085643640399850908258852784983106281451006875,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2065148827 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2065148827' seed=95331906708959156510296676682310085643640399850908258852784983106281451006875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_aes_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95331906708959156510296676682310085643640399850908258852784983106281451006875 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_aes_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"0.chip_sw_clkmgr_off_hmac_trans.22398064521190482776584118735442314591553630823453309080557570881438902205986","seed":22398064521190482776584118735442314591553630823453309080557570881438902205986,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1110785570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1110785570' seed=22398064521190482776584118735442314591553630823453309080557570881438902205986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_hmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22398064521190482776584118735442314591553630823453309080557570881438902205986 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_hmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"0.chip_sw_clkmgr_off_kmac_trans.37260122397351185874980838413601388002711219762865830137446953722343597622326","seed":37260122397351185874980838413601388002711219762865830137446953722343597622326,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1247102006 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1247102006' seed=37260122397351185874980838413601388002711219762865830137446953722343597622326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_kmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37260122397351185874980838413601388002711219762865830137446953722343597622326 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_kmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"0.chip_sw_clkmgr_off_otbn_trans.85072495934225360067960220153541087969821257020651055987344087499858661557342","seed":85072495934225360067960220153541087969821257020651055987344087499858661557342,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=967525470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.967525470' seed=85072495934225360067960220153541087969821257020651055987344087499858661557342 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85072495934225360067960220153541087969821257020651055987344087499858661557342 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.16565957198446719541327486029383827171439739981093724008868235771925371757077","seed":16565957198446719541327486029383827171439739981093724008868235771925371757077,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212176405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2212176405' seed=16565957198446719541327486029383827171439739981093724008868235771925371757077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:clkmgr_reset_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16565957198446719541327486029383827171439739981093724008868235771925371757077 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:clkmgr_reset_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_jitter","qual_name":"0.chip_sw_clkmgr_jitter.68140891955681859049070402119745111360174232270725438841162500890799040680851","seed":68140891955681859049070402119745111360174232270725438841162500890799040680851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1794954131 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter.1794954131' seed=68140891955681859049070402119745111360174232270725438841162500890799040680851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68140891955681859049070402119745111360174232270725438841162500890799040680851 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.10689399758256929205273700386259492159171701795859930533917663268823739640107","seed":10689399758256929205273700386259492159171701795859930533917663268823739640107,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1542170923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1542170923' seed=10689399758256929205273700386259492159171701795859930533917663268823739640107 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:clkmgr_sleep_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10689399758256929205273700386259492159171701795859930533917663268823739640107 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:clkmgr_sleep_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_jtag_csr_rw","qual_name":"0.chip_jtag_csr_rw.67493438991043614467140111178031139039524725176460707301050927196792091374808","seed":67493438991043614467140111178031139039524725176460707301050927196792091374808,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest run_opts='+en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693409496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.3693409496' seed=67493438991043614467140111178031139039524725176460707301050927196792091374808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67493438991043614467140111178031139039524725176460707301050927196792091374808 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_jtag_csr_rw_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_jtag_mem_access","qual_name":"0.chip_jtag_mem_access.36877455804500018175928991919329943649822784711020975256559324022897481586940","seed":36877455804500018175928991919329943649822784711020975256559324022897481586940,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest run_opts='+create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4191656188 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.4191656188' seed=36877455804500018175928991919329943649822784711020975256559324022897481586940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36877455804500018175928991919329943649822784711020975256559324022897481586940 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_jtag_mem_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"0.chip_sw_ast_clk_outputs.111846685998184175437347979952784874849203176012365326283863852465126435247728","seed":111846685998184175437347979952784874849203176012365326283863852465126435247728,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest run_opts='+sw_build_device=sim_dv +sw_images=ast_clk_outs_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1200674416 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1200674416' seed=111846685998184175437347979952784874849203176012365326283863852465126435247728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:ast_clk_outs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111846685998184175437347979952784874849203176012365326283863852465126435247728 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:ast_clk_outs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"0.chip_sw_lc_ctrl_program_error.52513592902567031630172384681544852059608630572367159286442559032653555959085","seed":52513592902567031630172384681544852059608630572367159286442559032653555959085,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3715368237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.3715368237' seed=52513592902567031630172384681544852059608630572367159286442559032653555959085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests/sim_dv:lc_ctrl_program_error:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52513592902567031630172384681544852059608630572367159286442559032653555959085 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests/sim_dv:lc_ctrl_program_error:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_program_error_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_rv_dm_ndm_reset_req","qual_name":"0.chip_rv_dm_ndm_reset_req.72537020719702079330161968006019899952626476622755512793666630883432585152276","seed":72537020719702079330161968006019899952626476622755512793666630883432585152276,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest run_opts='+en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_dev:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2108868372 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2108868372' seed=72537020719702079330161968006019899952626476622755512793666630883432585152276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_ndm_reset_req_dev:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72537020719702079330161968006019899952626476622755512793666630883432585152276 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_ndm_reset_req_dev:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_rv_dm_ndm_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.62500592453729995588807630979091574385515242795930098227114352857889472776431","seed":62500592453729995588807630979091574385515242795930098227114352857889472776431,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2862614767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2862614767' seed=62500592453729995588807630979091574385515242795930098227114352857889472776431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62500592453729995588807630979091574385515242795930098227114352857889472776431 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.24430499082940542917604633713672370362062065681294662283136031029565819782134","seed":24430499082940542917604633713672370362062065681294662283136031029565819782134,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594060790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3594060790' seed=24430499082940542917604633713672370362062065681294662283136031029565819782134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_access_after_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24430499082940542917604633713672370362062065681294662283136031029565819782134 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_access_after_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_access_after_wakeup_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"0.chip_sw_rv_dm_access_after_escalation_reset.57493239560280296270822705619803285338367571259862063046012275396820853947936","seed":57493239560280296270822705619803285338367571259862063046012275396820853947936,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2008383008 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2008383008' seed=57493239560280296270822705619803285338367571259862063046012275396820853947936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57493239560280296270822705619803285338367571259862063046012275396820853947936 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_access_after_escalation_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.37256604724497533811427486101457557666999435015738441917667108350416497318001","seed":37256604724497533811427486101457557666999435015738441917667108350416497318001,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest run_opts='+en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3024263281 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.3024263281' seed=37256604724497533811427486101457557666999435015738441917667108350416497318001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37256604724497533811427486101457557666999435015738441917667108350416497318001 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_rv_dm_lc_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_address_translation","qual_name":"0.chip_sw_rv_core_ibex_address_translation.89480103745356677834320799253762661595373057637103518555008409461652199186364","seed":89480103745356677834320799253762661595373057637103518555008409461652199186364,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest run_opts='+sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182408636 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1182408636' seed=89480103745356677834320799253762661595373057637103518555008409461652199186364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_address_translation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89480103745356677834320799253762661595373057637103518555008409461652199186364 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_address_translation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"0.chip_sw_rv_core_ibex_lockstep_glitch.100466286498989240538044625003952941357161720745389254381535196070352545502331","seed":100466286498989240538044625003952941357161720745389254381535196070352545502331,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest run_opts='+disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244438139 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.244438139' seed=100466286498989240538044625003952941357161720745389254381535196070352545502331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100466286498989240538044625003952941357161720745389254381535196070352545502331 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_core_ibex_lockstep_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_icache_invalidate","qual_name":"0.chip_sw_rv_core_ibex_icache_invalidate.63658206644399598161461114124414487907168334206725406440093739003910861148378","seed":63658206644399598161461114124414487907168334206725406440093739003910861148378,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2329202906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2329202906' seed=63658206644399598161461114124414487907168334206725406440093739003910861148378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_core_ibex_icache_invalidate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63658206644399598161461114124414487907168334206725406440093739003910861148378 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_core_ibex_icache_invalidate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_core_ibex_icache_invalidate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"0.chip_padctrl_attributes.17423207706904537840372381300828614876327593651822776823027573977393890078951","seed":17423207706904537840372381300828614876327593651822776823027573977393890078951,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=601370855 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_padctrl_attributes.601370855' seed=17423207706904537840372381300828614876327593651822776823027573977393890078951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17423207706904537840372381300828614876327593651822776823027573977393890078951 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_jitter_reduced_freq","qual_name":"0.chip_sw_clkmgr_jitter_reduced_freq.102322672221024683337330105199478531270793112351295556276509830210923867462709","seed":102322672221024683337330105199478531270793112351295556276509830210923867462709,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest run_opts='+cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1612241973 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1612241973' seed=102322672221024683337330105199478531270793112351295556276509830210923867462709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102322672221024683337330105199478531270793112351295556276509830210923867462709 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_aes_enc_jitter_en_reduced_freq.56792228791997273075379473026872998264464084935220393583466861031793194403260","seed":56792228791997273075379473026872998264464084935220393583466861031793194403260,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest run_opts='+sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2568193468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2568193468' seed=56792228791997273075379473026872998264464084935220393583466861031793194403260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56792228791997273075379473026872998264464084935220393583466861031793194403260 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_hmac_enc_jitter_en_reduced_freq.86209769695468379908279641038227696053582115559174990581279788383838385083635","seed":86209769695468379908279641038227696053582115559174990581279788383838385083635,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest run_opts='+en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1186338035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1186338035' seed=86209769695468379908279641038227696053582115559174990581279788383838385083635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86209769695468379908279641038227696053582115559174990581279788383838385083635 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.12992600666791163138543653921791054179167935530848573799849108127102075927801","seed":12992600666791163138543653921791054179167935530848573799849108127102075927801,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest run_opts='+en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=450362617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.450362617' seed=12992600666791163138543653921791054179167935530848573799849108127102075927801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12992600666791163138543653921791054179167935530848573799849108127102075927801 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.40989240217777972861925329487035692742263395882707411407827557690953913029011","seed":40989240217777972861925329487035692742263395882707411407827557690953913029011,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest run_opts='+mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=635130259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.635130259' seed=40989240217777972861925329487035692742263395882707411407827557690953913029011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40989240217777972861925329487035692742263395882707411407827557690953913029011 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_power_virus","qual_name":"0.chip_sw_power_virus.6988282400685389010188604856896208703066387555911411954214342386969219695879","seed":6988282400685389010188604856896208703066387555911411954214342386969219695879,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.096s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_dma_inline_hashing","qual_name":"0.chip_sw_dma_inline_hashing.68478694346083593024910886163759017142930339418736603256927485703942883302919","seed":68478694346083593024910886163759017142930339418736603256927485703942883302919,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_inline_hashing/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_inline_hashing/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_inline_hashing/latest run_opts='+sw_test_timeout_ns=22_000_000 +abort=0 +sw_build_device=sim_dv +sw_images=dma_inline_hashing:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=598531591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_dma_spi_hw_handshake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_dma_inline_hashing.598531591' seed=68478694346083593024910886163759017142930339418736603256927485703942883302919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:dma_inline_hashing:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68478694346083593024910886163759017142930339418736603256927485703942883302919 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_inline_hashing/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:dma_inline_hashing:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_dma_spi_hw_handshake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_dma_abort","qual_name":"0.chip_sw_dma_abort.75715248991729101822009168562788183924093208645211398381891671460671528982268","seed":75715248991729101822009168562788183924093208645211398381891671460671528982268,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest run_opts='+sw_test_timeout_ns=22_000_000 +abort=1 +sw_build_device=sim_dv +sw_images=dma_abort:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172840700 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_dma_spi_hw_handshake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_dma_abort.172840700' seed=75715248991729101822009168562788183924093208645211398381891671460671528982268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:dma_abort:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75715248991729101822009168562788183924093208645211398381891671460671528982268 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:dma_abort:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_dma_spi_hw_handshake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"base_rom_e2e_smoke","qual_name":"0.base_rom_e2e_smoke.78641938236427994102709878444583319793720833896258826533107832723905276476738","seed":78641938236427994102709878444583319793720833896258826533107832723905276476738,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=base_rom_e2e_smoke:7:test_in_second_rom,base_rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2649161026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.base_rom_e2e_smoke.2649161026' seed=78641938236427994102709878444583319793720833896258826533107832723905276476738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom //sw/device/silicon_creator/rom:base_rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78641938236427994102709878444583319793720833896258826533107832723905276476738 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom //sw/device/silicon_creator/rom:base_rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_smoke","qual_name":"0.rom_e2e_smoke.72213680699825243152977112717852894541882618250657208388703182875636269453569","seed":72213680699825243152977112717852894541882618250657208388703182875636269453569,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3892711681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3892711681' seed=72213680699825243152977112717852894541882618250657208388703182875636269453569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72213680699825243152977112717852894541882618250657208388703182875636269453569 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.74294647625133100020384319414898465423654393212684963936957492949328992969878","seed":74294647625133100020384319414898465423654393212684963936957492949328992969878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3417875606 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.3417875606' seed=74294647625133100020384319414898465423654393212684963936957492949328992969878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74294647625133100020384319414898465423654393212684963936957492949328992969878 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_shutdown_exception_c_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.100286952034789056417412128593557206573777144761724535517659655808760872271425","seed":100286952034789056417412128593557206573777144761724535517659655808760872271425,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest run_opts='+sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:6:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1055751745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1055751745' seed=100286952034789056417412128593557206573777144761724535517659655808760872271425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_shutdown_output_test_unlocked0:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100286952034789056417412128593557206573777144761724535517659655808760872271425 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_shutdown_output_test_unlocked0:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_shutdown_output_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.50411428284512703931490403673379598137755594880796811149358255342473081182093","seed":50411428284512703931490403673379598137755594880796811149358255342473081182093,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=208811) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.9199227815092612695079424234846684997686572743710419120219920587494995119205","seed":9199227815092612695079424234846684997686572743710419120219920587494995119205,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.111249651892008858734357804924412130090430842801573825495640965042693936841358","seed":111249651892008858734357804924412130090430842801573825495640965042693936841358,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.85968171125108988314156578238134229234130981319458966809209541281420995521336","seed":85968171125108988314156578238134229234130981319458966809209541281420995521336,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.62934846228698590635646809498377922467007268122688565142665411246303324197202","seed":62934846228698590635646809498377922467007268122688565142665411246303324197202,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.13122130621008691383847000706003683429821931736199313629517458385226262952832","seed":13122130621008691383847000706003683429821931736199313629517458385226262952832,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["Another command (pid=234537) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=222996) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=235356) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.112383510357487968434279518794061936281105396233823538412483817791819410406653","seed":112383510357487968434279518794061936281105396233823538412483817791819410406653,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["cwd=/nightly/current_run/opentitan\n","\n","Waiting for it to complete...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.90244674368882280232839282239705046940513083812857609413055960310107208684718","seed":90244674368882280232839282239705046940513083812857609413055960310107208684718,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.92088201158831198762841938649025622370077800806515664284448359637338259622551","seed":92088201158831198762841938649025622370077800806515664284448359637338259622551,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.41751338830992901000007614767782609399261744598785078817848999120439921935645","seed":41751338830992901000007614767782609399261744598785078817848999120439921935645,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.36450122452369734242971170510771112453049640363709842773437272223110405507418","seed":36450122452369734242971170510771112453049640363709842773437272223110405507418,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=209540) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.79244698041156852591922064915539348890709103000562660396908014736924959362325","seed":79244698041156852591922064915539348890709103000562660396908014736924959362325,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=387372) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.19507891743766295628677910058148014472585943533860344262264044989024175796045","seed":19507891743766295628677910058148014472585943533860344262264044989024175796045,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=387551) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.28921987832497418144571910754478442841295265787525994524077015009006096227955","seed":28921987832497418144571910754478442841295265787525994524077015009006096227955,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.49512710961059487745617497983384979905358119245242630391788790243143015822671","seed":49512710961059487745617497983384979905358119245242630391788790243143015822671,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.47034933635488610447133774421529607728296599089091444522321066763413607355050","seed":47034933635488610447133774421529607728296599089091444522321066763413607355050,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=235356) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.97274769344252327726128556466463226007551043612054235205820198995266989926051","seed":97274769344252327726128556466463226007551043612054235205820198995266989926051,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_dev_key_0,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1180378787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1180378787' seed=97274769344252327726128556466463226007551043612054235205820198995266989926051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97274769344252327726128556466463226007551043612054235205820198995266989926051 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.61864844837545264629084910798782003500781453651944321641395502259623195000651","seed":61864844837545264629084910798782003500781453651944321641395502259623195000651,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=813383499 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.813383499' seed=61864844837545264629084910798782003500781453651944321641395502259623195000651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61864844837545264629084910798782003500781453651944321641395502259623195000651 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.40348689023374000760892477043219218039841150072825948354715988800721980308689","seed":40348689023374000760892477043219218039841150072825948354715988800721980308689,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3302309073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3302309073' seed=40348689023374000760892477043219218039841150072825948354715988800721980308689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40348689023374000760892477043219218039841150072825948354715988800721980308689 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.75024844318081786054604064479797094867756929684610666194672539723981709323912","seed":75024844318081786054604064479797094867756929684610666194672539723981709323912,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3561696904 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3561696904' seed=75024844318081786054604064479797094867756929684610666194672539723981709323912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75024844318081786054604064479797094867756929684610666194672539723981709323912 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.17078857478375225201474267998384330871363975470759637065130113906156047169227","seed":17078857478375225201474267998384330871363975470759637065130113906156047169227,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=215087) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.31444818248939007244976094097615254189893061026619651372487149128359068868605","seed":31444818248939007244976094097615254189893061026619651372487149128359068868605,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2801311741 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2801311741' seed=31444818248939007244976094097615254189893061026619651372487149128359068868605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31444818248939007244976094097615254189893061026619651372487149128359068868605 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.34841008436672581482985693124996392870444441474362702507684307548990651429614","seed":34841008436672581482985693124996392870444441474362702507684307548990651429614,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799629038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2799629038' seed=34841008436672581482985693124996392870444441474362702507684307548990651429614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34841008436672581482985693124996392870444441474362702507684307548990651429614 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.85649513357872925483000620546432292803141905463265791605429076850965724381712","seed":85649513357872925483000620546432292803141905463265791605429076850965724381712,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3529097744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3529097744' seed=85649513357872925483000620546432292803141905463265791605429076850965724381712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85649513357872925483000620546432292803141905463265791605429076850965724381712 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.92893971567528674908899744575934201688195879570840318272550665814084409221197","seed":92893971567528674908899744575934201688195879570840318272550665814084409221197,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162628173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3162628173' seed=92893971567528674908899744575934201688195879570840318272550665814084409221197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92893971567528674908899744575934201688195879570840318272550665814084409221197 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.38071295267029372650631396668854417329854358969433096332476682432112829218115","seed":38071295267029372650631396668854417329854358969433096332476682432112829218115,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=223051) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.32332111495456779217908162835017422046277702981782781285607969607820845112744","seed":32332111495456779217908162835017422046277702981782781285607969607820845112744,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760577960 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3760577960' seed=32332111495456779217908162835017422046277702981782781285607969607820845112744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32332111495456779217908162835017422046277702981782781285607969607820845112744 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_dev_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.8353201289009030377851071382643461759359207529048045645731558491199964055162","seed":8353201289009030377851071382643461759359207529048045645731558491199964055162,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2159412858 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2159412858' seed=8353201289009030377851071382643461759359207529048045645731558491199964055162 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8353201289009030377851071382643461759359207529048045645731558491199964055162 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.19626283200784676681795879279873378947832533440024650065577179559730223680104","seed":19626283200784676681795879279873378947832533440024650065577179559730223680104,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3908471400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3908471400' seed=19626283200784676681795879279873378947832533440024650065577179559730223680104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19626283200784676681795879279873378947832533440024650065577179559730223680104 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.35091258281805683090622443173144431122965845377802976969679990145809212929214","seed":35091258281805683090622443173144431122965845377802976969679990145809212929214,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest run_opts='+sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2547414206 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2547414206' seed=35091258281805683090622443173144431122965845377802976969679990145809212929214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35091258281805683090622443173144431122965845377802976969679990145809212929214 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.87366146706853918630559907752923629398270233242590805346288642277188509700283","seed":87366146706853918630559907752923629398270233242590805346288642277188509700283,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=208811) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=211626) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=210404) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.49404637475417145332104258023667376253892808235554234655396448755309123663354","seed":49404637475417145332104258023667376253892808235554234655396448755309123663354,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.76849404572261367221991298606445496463042830069577389943965458799614647556461","seed":76849404572261367221991298606445496463042830069577389943965458799614647556461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.23872436444128235743453676863745043810454665840968950208258531270953581328890","seed":23872436444128235743453676863745043810454665840968950208258531270953581328890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.10327884318347796335244401360198751832292740636119710765464244711301974091216","seed":10327884318347796335244401360198751832292740636119710765464244711301974091216,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.77431434703926648493424904286084877608401517414712026632386533290750548340559","seed":77431434703926648493424904286084877608401517414712026632386533290750548340559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest run_opts='+use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3459739471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3459739471' seed=77431434703926648493424904286084877608401517414712026632386533290750548340559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77431434703926648493424904286084877608401517414712026632386533290750548340559 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_jtag_debug_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.75316815933294274304646683401752851734901441620603273375110477471841258800156","seed":75316815933294274304646683401752851734901441620603273375110477471841258800156,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest run_opts='+use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389593628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1389593628' seed=75316815933294274304646683401752851734901441620603273375110477471841258800156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75316815933294274304646683401752851734901441620603273375110477471841258800156 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_jtag_debug_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.95552605846616891146698000011527391766171257756799256026972821472228689439258","seed":95552605846616891146698000011527391766171257756799256026972821472228689439258,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest run_opts='+use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=64088602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.64088602' seed=95552605846616891146698000011527391766171257756799256026972821472228689439258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95552605846616891146698000011527391766171257756799256026972821472228689439258 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_jtag_debug_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.96071892352478299726220426060275008772394637776033273742271243324780069216437","seed":96071892352478299726220426060275008772394637776033273742271243324780069216437,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.106730453545196029506545293679123600422631046692884771587649457603632731827394","seed":106730453545196029506545293679123600422631046692884771587649457603632731827394,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=381867) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.11450960248050028328663648928843884853524392842605856581897106451785573120644","seed":11450960248050028328663648928843884853524392842605856581897106451785573120644,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=381867) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"0.rom_e2e_static_critical.38119721549529923738027263546130663166398641919288968138229903588780044322210","seed":38119721549529923738027263546130663166398641919288968138229903588780044322210,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:6:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286290338 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2286290338' seed=38119721549529923738027263546130663166398641919288968138229903588780044322210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38119721549529923738027263546130663166398641919288968138229903588780044322210 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_dpe_init_rom_ext_meas.68191219378312538087938495275937192739930088875593770718889757530589100406790","seed":68191219378312538087938495275937192739930088875593770718889757530589100406790,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3201726470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_dpe_init_rom_ext_meas.3201726470' seed=68191219378312538087938495275937192739930088875593770718889757530589100406790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68191219378312538087938495275937192739930088875593770718889757530589100406790 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_dpe_init_rom_ext_no_meas.21028690148528665106452913063866502272445857762501741304298443588812693432214","seed":21028690148528665106452913063866502272445857762501741304298443588812693432214,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_no_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354440086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_dpe_init_rom_ext_no_meas.2354440086' seed=21028690148528665106452913063866502272445857762501741304298443588812693432214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_no_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21028690148528665106452913063866502272445857762501741304298443588812693432214 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_no_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas","qual_name":"0.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas.66841662149949202262126310285876860775096140890827988640790395528327320502746","seed":66841662149949202262126310285876860775096140890827988640790395528327320502746,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_invalid_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2065891802 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas.2065891802' seed=66841662149949202262126310285876860775096140890827988640790395528327320502746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_invalid_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66841662149949202262126310285876860775096140890827988640790395528327320502746 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_invalid_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.101633845265432856318172598151844806269768727756128078116008798395780505991766","seed":101633845265432856318172598151844806269768727756128078116008798395780505991766,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["Another command (pid=232335) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=234537) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=222996) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.82567972157297284713935375641020105366127909731935673446873695303550557745773","seed":82567972157297284713935375641020105366127909731935673446873695303550557745773,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=245985) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_otbn.24701086081287595596419502031039332404338885895172997426572754351639745701598","seed":24701086081287595596419502031039332404338885895172997426572754351639745701598,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_dev_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4051085022 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_dev_otbn.4051085022' seed=24701086081287595596419502031039332404338885895172997426572754351639745701598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24701086081287595596419502031039332404338885895172997426572754351639745701598 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_sw.51327097704316469337166911377954132114847422470559008957887766021856940333710","seed":51327097704316469337166911377954132114847422470559008957887766021856940333710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_dev_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1488525966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_dev_sw.1488525966' seed=51327097704316469337166911377954132114847422470559008957887766021856940333710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51327097704316469337166911377954132114847422470559008957887766021856940333710 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_otbn.8586830829890849660304365779003691760023257062758145560740978048725754449022","seed":8586830829890849660304365779003691760023257062758145560740978048725754449022,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3551399038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_prod_otbn.3551399038' seed=8586830829890849660304365779003691760023257062758145560740978048725754449022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8586830829890849660304365779003691760023257062758145560740978048725754449022 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_sw.90361383220990852656145805139762095778442900912295577142297952351543755881190","seed":90361383220990852656145805139762095778442900912295577142297952351543755881190,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3550558950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_prod_sw.3550558950' seed=90361383220990852656145805139762095778442900912295577142297952351543755881190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90361383220990852656145805139762095778442900912295577142297952351543755881190 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_otbn.38590912256973717839374298768379490849458234340458861506745146772209187417279","seed":38590912256973717839374298768379490849458234340458861506745146772209187417279,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_end_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798120127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_prod_end_otbn.2798120127' seed=38590912256973717839374298768379490849458234340458861506745146772209187417279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38590912256973717839374298768379490849458234340458861506745146772209187417279 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_sw.102266625845666745977995740451907578235199100033862758485266294154788348395288","seed":102266625845666745977995740451907578235199100033862758485266294154788348395288,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_end_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2374270744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_prod_end_sw.2374270744' seed=102266625845666745977995740451907578235199100033862758485266294154788348395288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102266625845666745977995740451907578235199100033862758485266294154788348395288 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_otbn.43530851004978040053246345714037569907189157330230071482820634037099094884178","seed":43530851004978040053246345714037569907189157330230071482820634037099094884178,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_rma_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465035602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_rma_otbn.3465035602' seed=43530851004978040053246345714037569907189157330230071482820634037099094884178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43530851004978040053246345714037569907189157330230071482820634037099094884178 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_sw.11306125646443636557465590489803930636005041280163965438715636020207135447966","seed":11306125646443636557465590489803930636005041280163965438715636020207135447966,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_rma_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=995318686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_mod_exp_rma_sw.995318686' seed=11306125646443636557465590489803930636005041280163965438715636020207135447966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11306125646443636557465590489803930636005041280163965438715636020207135447966 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.82411000251442421336564861051447192251780398544140054739028004791950892537486","seed":82411000251442421336564861051447192251780398544140054739028004791950892537486,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.43530695759302137908685600947360653634112232736707199979196714239507692077709","seed":43530695759302137908685600947360653634112232736707199979196714239507692077709,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.71646560432926569506133957633874222146785771257719883696751819903272337257256","seed":71646560432926569506133957633874222146785771257719883696751819903272337257256,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=214559) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=215284) is running. Waiting for it to complete on the server (server_pid=208841)...\n","Another command (pid=222039) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"0.chip_sw_uart_smoketest_signed.103253525355956479742665018655279119609181361476303721964105944461001816508186","seed":103253525355956479742665018655279119609181361476303721964105944461001816508186,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=384658) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_dpe_functest","qual_name":"0.rom_keymgr_dpe_functest.43583474137191608705328363344310018405582921595728970779469516320310685130762","seed":43583474137191608705328363344310018405582921595728970779469516320310685130762,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_dpe_functest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_dpe_functest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_dpe_functest/latest run_opts='+sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_dpe_functest:6,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3922255882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_dpe_functest.3922255882' seed=43583474137191608705328363344310018405582921595728970779469516320310685130762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest:6 //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43583474137191608705328363344310018405582921595728970779469516320310685130762 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_dpe_functest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest:6 //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_smoketest","qual_name":"0.chip_sw_aes_smoketest.69588528854831731792945385319081441508481769712123733579370968818124773701045","seed":69588528854831731792945385319081441508481769712123733579370968818124773701045,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2055255477 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2055255477' seed=69588528854831731792945385319081441508481769712123733579370968818124773701045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69588528854831731792945385319081441508481769712123733579370968818124773701045 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_smoketest","qual_name":"0.chip_sw_aon_timer_smoketest.27806896687660179726517584863106587846549627135300349736875194407071627835878","seed":27806896687660179726517584863106587846549627135300349736875194407071627835878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=aon_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3925834214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_smoketest.3925834214' seed=27806896687660179726517584863106587846549627135300349736875194407071627835878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27806896687660179726517584863106587846549627135300349736875194407071627835878 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_smoketest","qual_name":"0.chip_sw_clkmgr_smoketest.54944015862910884332275248565032675802754411565030083115163504032500209141512","seed":54944015862910884332275248565032675802754411565030083115163504032500209141512,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881734408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_smoketest.2881734408' seed=54944015862910884332275248565032675802754411565030083115163504032500209141512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54944015862910884332275248565032675802754411565030083115163504032500209141512 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_smoketest","qual_name":"0.chip_sw_csrng_smoketest.104490749193019731499544259074938424940588031208540831702215115153567801751436","seed":104490749193019731499544259074938424940588031208540831702215115153567801751436,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=csrng_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1580021644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_smoketest.1580021644' seed=104490749193019731499544259074938424940588031208540831702215115153567801751436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:csrng_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104490749193019731499544259074938424940588031208540831702215115153567801751436 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:csrng_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_smoketest","qual_name":"0.chip_sw_entropy_src_smoketest.75350272289994587902392476155130243715539076104368976215724061480621241655509","seed":75350272289994587902392476155130243715539076104368976215724061480621241655509,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest run_opts='+rng_srate_value_min=3 +rng_srate_value_max=10 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1289609429 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1289609429' seed=75350272289994587902392476155130243715539076104368976215724061480621241655509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75350272289994587902392476155130243715539076104368976215724061480621241655509 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_gpio_smoketest","qual_name":"0.chip_sw_gpio_smoketest.57580572966970865619403491264885988714116661914027518168057548041505712662107","seed":57580572966970865619403491264885988714116661914027518168057548041505712662107,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=gpio_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725275227 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio_smoketest.2725275227' seed=57580572966970865619403491264885988714116661914027518168057548041505712662107 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:gpio_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57580572966970865619403491264885988714116661914027518168057548041505712662107 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:gpio_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_gpio_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_smoketest","qual_name":"0.chip_sw_hmac_smoketest.109162541886598191354376761653038261521232723628621896313486948049896167274917","seed":109162541886598191354376761653038261521232723628621896313486948049896167274917,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3420289445 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_smoketest.3420289445' seed=109162541886598191354376761653038261521232723628621896313486948049896167274917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109162541886598191354376761653038261521232723628621896313486948049896167274917 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_smoketest","qual_name":"0.chip_sw_kmac_smoketest.34868445927838251513665011041923122496027177084765358660605800094175018364162","seed":34868445927838251513665011041923122496027177084765358660605800094175018364162,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3131583746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.3131583746' seed=34868445927838251513665011041923122496027177084765358660605800094175018364162 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34868445927838251513665011041923122496027177084765358660605800094175018364162 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_mbx_smoketest","qual_name":"0.chip_sw_mbx_smoketest.44392265035270733800960201202426250154439016615655069322407474390167800358638","seed":44392265035270733800960201202426250154439016615655069322407474390167800358638,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_mbx_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_mbx_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_mbx_smoketest/latest run_opts='+use_mbx_if=1 +sw_build_device=sim_dv +sw_images=mbx_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4276725486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mbx_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_mbx_smoketest.4276725486' seed=44392265035270733800960201202426250154439016615655069322407474390167800358638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:mbx_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44392265035270733800960201202426250154439016615655069322407474390167800358638 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_mbx_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:mbx_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_mbx_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_smoketest","qual_name":"0.chip_sw_otbn_smoketest.26741279294643949675631325941534526450798752689418748940881390841366637426413","seed":26741279294643949675631325941534526450798752689418748940881390841366637426413,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=otbn_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4103583469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.4103583469' seed=26741279294643949675631325941534526450798752689418748940881390841366637426413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26741279294643949675631325941534526450798752689418748940881390841366637426413 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_smoketest","qual_name":"0.chip_sw_otp_ctrl_smoketest.82288155780696913768970954735523551251422957629282995437405248506826274964875","seed":82288155780696913768970954735523551251422957629282995437405248506826274964875,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3149202827 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_smoketest.3149202827' seed=82288155780696913768970954735523551251422957629282995437405248506826274964875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otp_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82288155780696913768970954735523551251422957629282995437405248506826274964875 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otp_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_plic_smoketest","qual_name":"0.chip_sw_rv_plic_smoketest.97675965054315542506433910306836652550072417237538005369977486901531877939878","seed":97675965054315542506433910306836652550072417237538005369977486901531877939878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_plic_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3195116198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_plic_smoketest.3195116198' seed=97675965054315542506433910306836652550072417237538005369977486901531877939878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_plic_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97675965054315542506433910306836652550072417237538005369977486901531877939878 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_plic_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_timer_smoketest","qual_name":"0.chip_sw_rv_timer_smoketest.67980183457023787851848578793350487860936065584171483347440240105054201832070","seed":67980183457023787851848578793350487860936065584171483347440240105054201832070,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184831622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_timer_smoketest.2184831622' seed=67980183457023787851848578793350487860936065584171483347440240105054201832070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67980183457023787851848578793350487860936065584171483347440240105054201832070 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_smoketest","qual_name":"0.chip_sw_rstmgr_smoketest.34103035855803687761685197061178270149504948216898241083243900203202439945945","seed":34103035855803687761685197061178270149504948216898241083243900203202439945945,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2112233177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_smoketest.2112233177' seed=34103035855803687761685197061178270149504948216898241083243900203202439945945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34103035855803687761685197061178270149504948216898241083243900203202439945945 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_smoketest","qual_name":"0.chip_sw_sram_ctrl_smoketest.78323863875221835044809787862265194493153320674494441788148422954346832299019","seed":78323863875221835044809787862265194493153320674494441788148422954346832299019,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1651868683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1651868683' seed=78323863875221835044809787862265194493153320674494441788148422954346832299019 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78323863875221835044809787862265194493153320674494441788148422954346832299019 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_smoketest","qual_name":"0.chip_sw_uart_smoketest.66044082952846321381246074924811356845689502046715321358632755021642169661737","seed":66044082952846321381246074924811356845689502046715321358632755021642169661737,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=uart_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3605084457 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_smoketest.3605084457' seed=66044082952846321381246074924811356845689502046715321358632755021642169661737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66044082952846321381246074924811356845689502046715321358632755021642169661737 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"0.xbar_smoke.103882669607291022362536870203301564233067838173505936734122636669483848162625","seed":103882669607291022362536870203301564233067838173505936734122636669483848162625,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1552014657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1552014657' seed=103882669607291022362536870203301564233067838173505936734122636669483848162625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103882669607291022362536870203301564233067838173505936734122636669483848162625 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"0.xbar_smoke_zero_delays.57423303778806264563596454155350565923590487123559308126369078181459330580229","seed":57423303778806264563596454155350565923590487123559308126369078181459330580229,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1699725061 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1699725061' seed=57423303778806264563596454155350565923590487123559308126369078181459330580229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57423303778806264563596454155350565923590487123559308126369078181459330580229 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"0.xbar_smoke_large_delays.30779761685447547746114588004525776719975497924603442828579253618653193064433","seed":30779761685447547746114588004525776719975497924603442828579253618653193064433,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1520979953 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1520979953' seed=30779761685447547746114588004525776719975497924603442828579253618653193064433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30779761685447547746114588004525776719975497924603442828579253618653193064433 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"0.xbar_smoke_slow_rsp.85683670705472075817212778574044769082114336707929778577211385378482627392249","seed":85683670705472075817212778574044769082114336707929778577211385378482627392249,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3642864377 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3642864377' seed=85683670705472075817212778574044769082114336707929778577211385378482627392249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85683670705472075817212778574044769082114336707929778577211385378482627392249 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"0.xbar_random.77201941040832305381662875767649202746531308080548082237635185081788045725550","seed":77201941040832305381662875767649202746531308080548082237635185081788045725550,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1476923246 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1476923246' seed=77201941040832305381662875767649202746531308080548082237635185081788045725550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77201941040832305381662875767649202746531308080548082237635185081788045725550 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"0.xbar_random_zero_delays.88983725677143678338749768783633869249992888715513208010299565695068699372727","seed":88983725677143678338749768783633869249992888715513208010299565695068699372727,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702191799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2702191799' seed=88983725677143678338749768783633869249992888715513208010299565695068699372727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88983725677143678338749768783633869249992888715513208010299565695068699372727 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"0.xbar_random_large_delays.91767114791112912525785065922341062923026954604316595159320982283235096038802","seed":91767114791112912525785065922341062923026954604316595159320982283235096038802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4128804242 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4128804242' seed=91767114791112912525785065922341062923026954604316595159320982283235096038802 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91767114791112912525785065922341062923026954604316595159320982283235096038802 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"0.xbar_random_slow_rsp.93190388563478299688333879797539941224407579514188293993950391998848460242384","seed":93190388563478299688333879797539941224407579514188293993950391998848460242384,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=260947408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.260947408' seed=93190388563478299688333879797539941224407579514188293993950391998848460242384 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93190388563478299688333879797539941224407579514188293993950391998848460242384 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"0.xbar_access_same_device.30863373728167624609600270356082059444689275091897234695353918387536031609234","seed":30863373728167624609600270356082059444689275091897234695353918387536031609234,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=714305938 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.714305938' seed=30863373728167624609600270356082059444689275091897234695353918387536031609234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30863373728167624609600270356082059444689275091897234695353918387536031609234 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.24106442333728553898644190658311689516818191396449764009503154298854877634757","seed":24106442333728553898644190658311689516818191396449764009503154298854877634757,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3478593733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3478593733' seed=24106442333728553898644190658311689516818191396449764009503154298854877634757 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24106442333728553898644190658311689516818191396449764009503154298854877634757 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"0.xbar_same_source.19435342435153674321647443480976800213486278649596258906318604617633105535255","seed":19435342435153674321647443480976800213486278649596258906318604617633105535255,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=547971351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.547971351' seed=19435342435153674321647443480976800213486278649596258906318604617633105535255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19435342435153674321647443480976800213486278649596258906318604617633105535255 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"0.xbar_error_random.81058631546781342370684535906671306359677756318963887043573000342835698924470","seed":81058631546781342370684535906671306359677756318963887043573000342835698924470,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334536118 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3334536118' seed=81058631546781342370684535906671306359677756318963887043573000342835698924470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81058631546781342370684535906671306359677756318963887043573000342835698924470 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"0.xbar_unmapped_addr.67159041688990004601020073763647266251971756092401860502939099154918814710630","seed":67159041688990004601020073763647266251971756092401860502939099154918814710630,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597700966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1597700966' seed=67159041688990004601020073763647266251971756092401860502939099154918814710630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67159041688990004601020073763647266251971756092401860502939099154918814710630 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"0.xbar_error_and_unmapped_addr.70228098001495039135004662927554593226331404975798414798096620628348992794095","seed":70228098001495039135004662927554593226331404975798414798096620628348992794095,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25210351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.25210351' seed=70228098001495039135004662927554593226331404975798414798096620628348992794095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70228098001495039135004662927554593226331404975798414798096620628348992794095 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"0.xbar_stress_all.96125682245627602573993228307998509770148283636393295102759086020789089058794","seed":96125682245627602573993228307998509770148283636393295102759086020789089058794,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1563410410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1563410410' seed=96125682245627602573993228307998509770148283636393295102759086020789089058794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96125682245627602573993228307998509770148283636393295102759086020789089058794 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"0.xbar_stress_all_with_rand_reset.86408427521905383841058677985389578778785240538704276134938531749018909646213","seed":86408427521905383841058677985389578778785240538704276134938531749018909646213,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1173200261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1173200261' seed=86408427521905383841058677985389578778785240538704276134938531749018909646213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86408427521905383841058677985389578778785240538704276134938531749018909646213 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"0.xbar_stress_all_with_error.91320023198859129798329313699207814944254913059804243472254790783913702294330","seed":91320023198859129798329313699207814944254913059804243472254790783913702294330,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569293114 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1569293114' seed=91320023198859129798329313699207814944254913059804243472254790783913702294330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91320023198859129798329313699207814944254913059804243472254790783913702294330 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"0.xbar_stress_all_with_reset_error.5622298681225391665201041442983353195465283810892258373124824512199487052018","seed":5622298681225391665201041442983353195465283810892258373124824512199487052018,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2968967410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2968967410' seed=5622298681225391665201041442983353195465283810892258373124824512199487052018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5622298681225391665201041442983353195465283810892258373124824512199487052018 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_same_csr_outstanding","qual_name":"1.chip_same_csr_outstanding.30558711074943332507947010237558634801088802943742326909700880503888857672091","seed":30558711074943332507947010237558634801088802943742326909700880503888857672091,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest run_opts='+test_timeout_ns=120_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2554735003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2554735003' seed=30558711074943332507947010237558634801088802943742326909700880503888857672091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30558711074943332507947010237558634801088802943742326909700880503888857672091 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_rom","qual_name":"1.chip_sw_example_rom.96783886465354692628594453265283578859895937069308428174994888931068349966186","seed":96783886465354692628594453265283578859895937069308428174994888931068349966186,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2648106858 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.2648106858' seed=96783886465354692628594453265283578859895937069308428174994888931068349966186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:example_test_from_rom:0:test_in_rom'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96783886465354692628594453265283578859895937069308428174994888931068349966186 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images=//sw/device/tests:example_test_from_rom:0:test_in_rom uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"1.chip_sw_example_manufacturer.68217510022293640256853241334682720722355182490296275284050072615323240994389","seed":68217510022293640256853241334682720722355182490296275284050072615323240994389,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507459669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3507459669' seed=68217510022293640256853241334682720722355182490296275284050072615323240994389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68217510022293640256853241334682720722355182490296275284050072615323240994389 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_concurrency","qual_name":"1.chip_sw_example_concurrency.35351603993330295185517174507972503168183565903546905178796944108810750377884","seed":35351603993330295185517174507972503168183565903546905178796944108810750377884,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_concurrency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_concurrency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_concurrency/latest run_opts='+sw_build_device=sim_dv +sw_images=example_concurrency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=357023644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.357023644' seed=35351603993330295185517174507972503168183565903546905178796944108810750377884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35351603993330295185517174507972503168183565903546905178796944108810750377884 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_concurrency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"1.chip_sw_all_escalation_resets.43632344466668324450645512649884670365350294365445595732975176840973870182058","seed":43632344466668324450645512649884670365350294365445595732975176840973870182058,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2543857322 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2543857322' seed=43632344466668324450645512649884670365350294365445595732975176840973870182058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43632344466668324450645512649884670365350294365445595732975176840973870182058 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"1.chip_sw_rstmgr_rst_cnsty_escalation.80193178811742994626080691968735241035329281442182456172714071497008149625998","seed":80193178811742994626080691968735241035329281442182456172714071497008149625998,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363527310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.363527310' seed=80193178811742994626080691968735241035329281442182456172714071497008149625998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80193178811742994626080691968735241035329281442182456172714071497008149625998 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rstmgr_cnsty_fault_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"1.chip_sw_data_integrity_escalation.57067061487878398204596245851175853356125210054116011235287102834913117175884","seed":57067061487878398204596245851175853356125210054116011235287102834913117175884,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2480373836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2480373836' seed=57067061487878398204596245851175853356125210054116011235287102834913117175884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57067061487878398204596245851175853356125210054116011235287102834913117175884 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_data_integrity_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.68776536222997229412060679173731230162086347091081875328313895761894758467365","seed":68776536222997229412060679173731230162086347091081875328313895761894758467365,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest run_opts='+use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3719087909 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3719087909' seed=68776536222997229412060679173731230162086347091081875328313895761894758467365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sleep_pin_wake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68776536222997229412060679173731230162086347091081875328313895761894758467365 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sleep_pin_wake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sleep_pin_wake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"1.chip_sw_sleep_pin_retention.1214939330056244608667427256494414243530712731751064199794548504500080327372","seed":1214939330056244608667427256494414243530712731751064199794548504500080327372,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest run_opts='+sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676341452 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.2676341452' seed=1214939330056244608667427256494414243530712731751064199794548504500080327372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sleep_pin_retention_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1214939330056244608667427256494414243530712731751064199794548504500080327372 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sleep_pin_retention_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sleep_pin_retention_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"1.chip_sw_uart_tx_rx.103997514703943726266274301732202735266609575256984511094305595654941423256060","seed":103997514703943726266274301732202735266609575256984511094305595654941423256060,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest run_opts='+uart_idx=0 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3022078460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.3022078460' seed=103997514703943726266274301732202735266609575256984511094305595654941423256060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103997514703943726266274301732202735266609575256984511094305595654941423256060 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"1.chip_sw_uart_tx_rx_bootstrap.55253066275816209489307140177680149297204689395715492338260952049978334764199","seed":55253066275816209489307140177680149297204689395715492338260952049978334764199,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.164s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"1.chip_sw_inject_scramble_seed.15604456239227791478840632674148068528874928923144469232108982431707973139739","seed":15604456239227791478840632674148068528874928923144469232108982431707973139739,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.132s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"1.chip_sw_exit_test_unlocked_bootstrap.87656510900963244342991805950743247078281311843620761297690484318813338497447","seed":87656510900963244342991805950743247078281311843620761297690484318813338497447,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.569s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"1.chip_sw_uart_rand_baudrate.40777560199727224178061132689290339635533764373245036798025726744452737770559","seed":40777560199727224178061132689290339635533764373245036798025726744452737770559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4017071167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4017071167' seed=40777560199727224178061132689290339635533764373245036798025726744452737770559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40777560199727224178061132689290339635533764373245036798025726744452737770559 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"1.chip_sw_uart_tx_rx_alt_clk_freq.26606253401797538771955036873818861738306637314353244698689213424811149858422","seed":26606253401797538771955036873818861738306637314353244698689213424811149858422,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest run_opts='+sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268829302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq.2268829302' seed=26606253401797538771955036873818861738306637314353244698689213424811149858422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26606253401797538771955036873818861738306637314353244698689213424811149858422 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"1.chip_sw_i2c_host_tx_rx.29400920340779755338883882367184741084207514224121740391878387328898169948516","seed":29400920340779755338883882367184741084207514224121740391878387328898169948516,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest run_opts='+i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590441316 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3590441316' seed=29400920340779755338883882367184741084207514224121740391878387328898169948516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:i2c_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29400920340779755338883882367184741084207514224121740391878387328898169948516 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:i2c_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_i2c_host_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"1.chip_sw_i2c_device_tx_rx.7048439532141684669273838863922337845371462847279295371876111462810126281014","seed":7048439532141684669273838863922337845371462847279295371876111462810126281014,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest run_opts='+sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1582197046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1582197046' seed=7048439532141684669273838863922337845371462847279295371876111462810126281014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:i2c_device_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7048439532141684669273838863922337845371462847279295371876111462810126281014 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:i2c_device_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_i2c_device_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"1.chip_sw_spi_device_tpm.89646263413399151503871325958866302316635889895810685870684854592967054163222","seed":89646263413399151503871325958866302316635889895810685870684854592967054163222,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79658262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.79658262' seed=89646263413399151503871325958866302316635889895810685870684854592967054163222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:spi_device_tpm_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89646263413399151503871325958866302316635889895810685870684854592967054163222 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:spi_device_tpm_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_device_tpm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"1.chip_sw_spi_host_tx_rx.68346345564450847789498666360811522982248975882324610983852698954222059253536","seed":68346345564450847789498666360811522982248975882324610983852698954222059253536,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457830176 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.457830176' seed=68346345564450847789498666360811522982248975882324610983852698954222059253536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68346345564450847789498666360811522982248975882324610983852698954222059253536 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_host_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_pass_through","qual_name":"1.chip_sw_spi_device_pass_through.82973032846983684117339860207112823681555815180098245693001034311433847217857","seed":82973032846983684117339860207112823681555815180098245693001034311433847217857,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_passthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840684737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1840684737' seed=82973032846983684117339860207112823681555815180098245693001034311433847217857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82973032846983684117339860207112823681555815180098245693001034311433847217857 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_passthrough_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.74860880006185276541084911863869538075614901119929271310291838461867326406204","seed":74860880006185276541084911863869538075614901119929271310291838461867326406204,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_passthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=857701948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.857701948' seed=74860880006185276541084911863869538075614901119929271310291838461867326406204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74860880006185276541084911863869538075614901119929271310291838461867326406204 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_passthrough_collision_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_gpio","qual_name":"1.chip_sw_gpio.15703806309925083125679238833636107551253689690159130105622016170639071159753","seed":15703806309925083125679238833636107551253689690159130105622016170639071159753,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio/latest run_opts='+sw_build_device=sim_dv +sw_images=gpio_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2889393609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio.2889393609' seed=15703806309925083125679238833636107551253689690159130105622016170639071159753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:gpio_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15703806309925083125679238833636107551253689690159130105622016170639071159753 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:gpio_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_gpio_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_entropy","qual_name":"1.chip_sw_kmac_entropy.51518633305035793079214897414288451118384792181040554213753871995662567459614","seed":51518633305035793079214897414288451118384792181040554213753871995662567459614,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_entropy/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3813133086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_entropy.3813133086' seed=51518633305035793079214897414288451118384792181040554213753871995662567459614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51518633305035793079214897414288451118384792181040554213753871995662567459614 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"1.chip_sw_lc_ctrl_otp_hw_cfg.24081070540707100584141980197835012654601272258738738299642538594626650717693","seed":24081070540707100584141980197835012654601272258738738299642538594626650717693,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608886781 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg.3608886781' seed=24081070540707100584141980197835012654601272258738738299642538594626650717693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:lc_ctrl_otp_hw_cfg_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24081070540707100584141980197835012654601272258738738299642538594626650717693 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:lc_ctrl_otp_hw_cfg_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.40493686541801529859658252061945466801142263950418712754968350240288073876394","seed":40493686541801529859658252061945466801142263950418712754968350240288073876394,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest run_opts='+use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1913422762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1913422762' seed=40493686541801529859658252061945466801142263950418712754968350240288073876394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40493686541801529859658252061945466801142263950418712754968350240288073876394 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"1.chip_sw_otp_ctrl_lc_signals_dev.107550855429153455384390007570417897056162227200457179294649920549163988127563","seed":107550855429153455384390007570417897056162227200457179294649920549163988127563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest run_opts='+use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=554667851 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.554667851' seed=107550855429153455384390007570417897056162227200457179294649920549163988127563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107550855429153455384390007570417897056162227200457179294649920549163988127563 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"1.chip_sw_otp_ctrl_lc_signals_prod.26491769719998473788605048733602335585848217129307567296331990636717122194098","seed":26491769719998473788605048733602335585848217129307567296331990636717122194098,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest run_opts='+use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1607666354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1607666354' seed=26491769719998473788605048733602335585848217129307567296331990636717122194098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26491769719998473788605048733602335585848217129307567296331990636717122194098 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.2232906148519180787450896125593320777521668493319753281227540740204492879701","seed":2232906148519180787450896125593320777521668493319753281227540740204492879701,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest run_opts='+use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430465877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2430465877' seed=2232906148519180787450896125593320777521668493319753281227540740204492879701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2232906148519180787450896125593320777521668493319753281227540740204492879701 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"1.chip_sw_otp_ctrl_vendor_test_csr_access.62454283871492141742990602627708479130754978155899292826488163938999911327358","seed":62454283871492141742990602627708479130754978155899292826488163938999911327358,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest run_opts='+sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1634477694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1634477694' seed=62454283871492141742990602627708479130754978155899292826488163938999911327358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62454283871492141742990602627708479130754978155899292826488163938999911327358 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_otp_ctrl_vendor_test_csr_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"1.chip_sw_lc_ctrl_transition.3264529821871302633008964056248516528596652650412218774415167555332674986994","seed":3264529821871302633008964056248516528596652650412218774415167555332674986994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1630315506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1630315506' seed=3264529821871302633008964056248516528596652650412218774415167555332674986994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3264529821871302633008964056248516528596652650412218774415167555332674986994 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"1.chip_sw_lc_ctrl_rand_to_scrap.49227882237785789316910008267209921123765443535248340501535896644466547220755","seed":49227882237785789316910008267209921123765443535248340501535896644466547220755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=460972307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.460972307' seed=49227882237785789316910008267209921123765443535248340501535896644466547220755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49227882237785789316910008267209921123765443535248340501535896644466547220755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_scrap_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.56444418261683781652822245515603296211648441018044266338762714496469536594426","seed":56444418261683781652822245515603296211648441018044266338762714496469536594426,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.976s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.14442350662386556737649623251233521030594924219938452585551825639461623453419","seed":14442350662386556737649623251233521030594924219938452585551825639461623453419,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.194s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"1.chip_sw_lc_walkthrough_prodend.53329253986149950692332651034105290592901250969715839949907826511099936525561","seed":53329253986149950692332651034105290592901250969715839949907826511099936525561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest run_opts='+flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2551074041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.2551074041' seed=53329253986149950692332651034105290592901250969715839949907826511099936525561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_walkthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53329253986149950692332651034105290592901250969715839949907826511099936525561 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_walkthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_walkthrough_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"1.chip_sw_lc_ctrl_volatile_raw_unlock.12267407624658674912345840491938028556748227874931763620726181365746953875241","seed":12267407624658674912345840491938028556748227874931763620726181365746953875241,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest run_opts='+use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2377379625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2377379625' seed=12267407624658674912345840491938028556748227874931763620726181365746953875241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12267407624658674912345840491938028556748227874931763620726181365746953875241 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_volatile_raw_unlock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.75140479039685535119507544695863834838714215353850380419359021649284947780785","seed":75140479039685535119507544695863834838714215353850380419359021649284947780785,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest run_opts='+use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618303665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2618303665' seed=75140479039685535119507544695863834838714215353850380419359021649284947780785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75140479039685535119507544695863834838714215353850380419359021649284947780785 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_volatile_raw_unlock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.21528967506403250320012245087311342100866425213918209872353099439954603917811","seed":21528967506403250320012245087311342100866425213918209872353099439954603917811,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.168s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"1.chip_sw_lc_walkthrough_testunlocks.89987065610709694069858775178653042479058353139171601581858518109237512882677","seed":89987065610709694069858775178653042479058353139171601581858518109237512882677,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest run_opts='+use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=940952053 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.940952053' seed=89987065610709694069858775178653042479058353139171601581858518109237512882677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89987065610709694069858775178653042479058353139171601581858518109237512882677 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_walkthrough_testunlocks_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_sw_req","qual_name":"1.chip_sw_rstmgr_sw_req.59357812478662675940438232670219293558632214522786931554243819842599199097106","seed":59357812478662675940438232670219293558632214522786931554243819842599199097106,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=237682962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_req.237682962' seed=59357812478662675940438232670219293558632214522786931554243819842599199097106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_sw_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59357812478662675940438232670219293558632214522786931554243819842599199097106 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_sw_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_sw_rst","qual_name":"1.chip_sw_rstmgr_sw_rst.33920130468401026865674278343777068771302877828304680443069984464457541003322","seed":33920130468401026865674278343777068771302877828304680443069984464457541003322,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3532564538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3532564538' seed=33920130468401026865674278343777068771302877828304680443069984464457541003322 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_sw_rst_ctrl_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33920130468401026865674278343777068771302877828304680443069984464457541003322 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_sw_rst_ctrl_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"1.chip_sw_rstmgr_alert_info.39464739265240114449179353570361682169712256837639284834118487034203202713498","seed":39464739265240114449179353570361682169712256837639284834118487034203202713498,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest run_opts='+sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1689581466 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1689581466' seed=39464739265240114449179353570361682169712256837639284834118487034203202713498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_alert_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39464739265240114449179353570361682169712256837639284834118487034203202713498 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_alert_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"1.chip_sw_rstmgr_cpu_info.60250009313670713165654556837176596359750787029405931654589054948212801666966","seed":60250009313670713165654556837176596359750787029405931654589054948212801666966,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest run_opts='+sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1776942998 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1776942998' seed=60250009313670713165654556837176596359750787029405931654589054948212801666966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_cpu_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60250009313670713165654556837176596359750787029405931654589054948212801666966 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_cpu_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.59442404470182886591328607761319784135063291782546671074221763685755264530210","seed":59442404470182886591328607761319784135063291782546671074221763685755264530210,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=488994594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.488994594' seed=59442404470182886591328607761319784135063291782546671074221763685755264530210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59442404470182886591328607761319784135063291782546671074221763685755264530210 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_full_aon_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_main_power_glitch_reset.95888347373169820827056476473133687751487716467524985668283478817702980605286","seed":95888347373169820827056476473133687751487716467524985668283478817702980605286,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140498278 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.140498278' seed=95888347373169820827056476473133687751487716467524985668283478817702980605286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95888347373169820827056476473133687751487716467524985668283478817702980605286 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_main_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.107317901658148293809096497458145840554406279404253287294504923699586287484874","seed":107317901658148293809096497458145840554406279404253287294504923699586287484874,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=930561994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.930561994' seed=107317901658148293809096497458145840554406279404253287294504923699586287484874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107317901658148293809096497458145840554406279404253287294504923699586287484874 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_main_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.20129556508486652239258678407053948628681784761699173601613680799553841968130","seed":20129556508486652239258678407053948628681784761699173601613680799553841968130,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1326625794 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1326625794' seed=20129556508486652239258678407053948628681784761699173601613680799553841968130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20129556508486652239258678407053948628681784761699173601613680799553841968130 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_deep_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.46191376750378722165667928031911722224228724932843227135491111959238603705862","seed":46191376750378722165667928031911722224228724932843227135491111959238603705862,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3296202246 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3296202246' seed=46191376750378722165667928031911722224228724932843227135491111959238603705862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46191376750378722165667928031911722224228724932843227135491111959238603705862 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_random_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"1.chip_sw_pwrmgr_sleep_disabled.112028925313347148353130887395055018327738623640960963378172627923156846169582","seed":112028925313347148353130887395055018327738623640960963378172627923156846169582,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest run_opts='+sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2558447086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2558447086' seed=112028925313347148353130887395055018327738623640960963378172627923156846169582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:pwrmgr_sleep_disabled_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112028925313347148353130887395055018327738623640960963378172627923156846169582 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:pwrmgr_sleep_disabled_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_timer_irq","qual_name":"1.chip_sw_rv_timer_irq.43945302967795655889222010654213469057741678235591850768471645250337566617544","seed":43945302967795655889222010654213469057741678235591850768471645250337566617544,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=752349128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_timer_irq.752349128' seed=43945302967795655889222010654213469057741678235591850768471645250337566617544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43945302967795655889222010654213469057741678235591850768471645250337566617544 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"1.chip_sw_soc_proxy_smoketest.13572918087624690209158520492053594853807037008738082676756758022027740084831","seed":13572918087624690209158520492053594853807037008738082676756758022027740084831,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=858683999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_soc_proxy_smoketest.858683999' seed=13572918087624690209158520492053594853807037008738082676756758022027740084831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13572918087624690209158520492053594853807037008738082676756758022027740084831 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"1.chip_sw_soc_proxy_external_wakeup.18872635901937615123142863163223490454997151507253380657717116462533665691175","seed":18872635901937615123142863163223490454997151507253380657717116462533665691175,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_external_wakeup:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3699185191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_external_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_soc_proxy_external_wakeup.3699185191' seed=18872635901937615123142863163223490454997151507253380657717116462533665691175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_external_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18872635901937615123142863163223490454997151507253380657717116462533665691175 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_external_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_external_wakeup_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_gpios","qual_name":"1.chip_sw_soc_proxy_gpios.75518689527156013639997975951581526082241857277782442585752895475029195882021","seed":75518689527156013639997975951581526082241857277782442585752895475029195882021,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_gpios:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3352559141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_soc_proxy_gpios.3352559141' seed=75518689527156013639997975951581526082241857277782442585752895475029195882021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_gpios:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75518689527156013639997975951581526082241857277782442585752895475029195882021 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_gpios:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_gpio_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"1.chip_sw_aon_timer_irq.24629635750638010798103991753620585756501869630927354919136345383819789531077","seed":24629635750638010798103991753620585756501869630927354919136345383819789531077,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1765341125 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1765341125' seed=24629635750638010798103991753620585756501869630927354919136345383819789531077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24629635750638010798103991753620585756501869630927354919136345383819789531077 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_sleep_wdog_sleep_pause","qual_name":"1.chip_sw_aon_timer_sleep_wdog_sleep_pause.7772429148398953861389456739965156633701283572744906179433616799489437427299","seed":7772429148398953861389456739965156633701283572744906179433616799489437427299,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4120077923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4120077923' seed=7772429148398953861389456739965156633701283572744906179433616799489437427299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7772429148398953861389456739965156633701283572744906179433616799489437427299 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.30660920206446056876512970751096077244064859193990906265771756346832067962920","seed":30660920206446056876512970751096077244064859193990906265771756346832067962920,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest run_opts='+sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2352162856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2352162856' seed=30660920206446056876512970751096077244064859193990906265771756346832067962920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_wdog_bite_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30660920206446056876512970751096077244064859193990906265771756346832067962920 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_wdog_bite_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"1.chip_sw_pwrmgr_wdog_reset.86524609298705108042900891679801445465292443111046502497170538974992424617004","seed":86524609298705108042900891679801445465292443111046502497170538974992424617004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914449964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.3914449964' seed=86524609298705108042900891679801445465292443111046502497170538974992424617004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:pwrmgr_wdog_reset_reqs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86524609298705108042900891679801445465292443111046502497170538974992424617004 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:pwrmgr_wdog_reset_reqs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_wdog_lc_escalate","qual_name":"1.chip_sw_aon_timer_wdog_lc_escalate.44397846092662610928895825563322529088814610096285887922932582176668824049500","seed":44397846092662610928895825563322529088814610096285887922932582176668824049500,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3642169180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3642169180' seed=44397846092662610928895825563322529088814610096285887922932582176668824049500 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_wdog_lc_escalate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44397846092662610928895825563322529088814610096285887922932582176668824049500 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_wdog_lc_escalate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_randomness","qual_name":"1.chip_sw_otbn_randomness.73253473924232468910739766199961993984796445933355312428357758710090215190091","seed":73253473924232468910739766199961993984796445933355312428357758710090215190091,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_randomness/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_randomness/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_randomness/latest run_opts='+sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025582155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2025582155' seed=73253473924232468910739766199961993984796445933355312428357758710090215190091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_randomness_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73253473924232468910739766199961993984796445933355312428357758710090215190091 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_randomness/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_randomness_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_mem_scramble","qual_name":"1.chip_sw_otbn_mem_scramble.100864552763210796613266569550355427856442247076874542040873966896265298818961","seed":100864552763210796613266569550355427856442247076874542040873966896265298818961,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest run_opts='+sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1456322449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.1456322449' seed=100864552763210796613266569550355427856442247076874542040873966896265298818961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_mem_scramble_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100864552763210796613266569550355427856442247076874542040873966896265298818961 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_mem_scramble_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"1.chip_sw_rv_core_ibex_rnd.79616205480018824875032987766854024501639879989387955876195370250211026075007","seed":79616205480018824875032987766854024501639879989387955876195370250211026075007,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest run_opts='+sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3521445247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3521445247' seed=79616205480018824875032987766854024501639879989387955876195370250211026075007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_rnd_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79616205480018824875032987766854024501639879989387955876195370250211026075007 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_rnd_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"1.chip_sw_rv_core_ibex_nmi_irq.50483867970210720237660470315796182706750907939775628479571761677744744031173","seed":50483867970210720237660470315796182706750907939775628479571761677744744031173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest run_opts='+sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2251678661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2251678661' seed=50483867970210720237660470315796182706750907939775628479571761677744744031173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_nmi_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50483867970210720237660470315796182706750907939775628479571761677744744031173 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_nmi_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc","qual_name":"1.chip_sw_aes_enc.86922897371962573838681509700900228748250778159276709413877771970278697251802","seed":86922897371962573838681509700900228748250778159276709413877771970278697251802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc/latest run_opts='+sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1033679834 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.1033679834' seed=86922897371962573838681509700900228748250778159276709413877771970278697251802 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86922897371962573838681509700900228748250778159276709413877771970278697251802 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"1.chip_sw_aes_enc_jitter_en.108901731581244540508553159074412550283375971004583660055392881868796784357140","seed":108901731581244540508553159074412550283375971004583660055392881868796784357140,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest run_opts='+sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=609562388 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.609562388' seed=108901731581244540508553159074412550283375971004583660055392881868796784357140 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108901731581244540508553159074412550283375971004583660055392881868796784357140 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_gcm","qual_name":"1.chip_sw_aes_gcm.23089242488291724222733176672566655634048248231172065252265852220026694994360","seed":23089242488291724222733176672566655634048248231172065252265852220026694994360,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_gcm/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_gcm/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_gcm/latest run_opts='+sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_gcm_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1185221048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_gcm.1185221048' seed=23089242488291724222733176672566655634048248231172065252265852220026694994360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_gcm_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23089242488291724222733176672566655634048248231172065252265852220026694994360 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_gcm/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_gcm_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_idle","qual_name":"1.chip_sw_aes_idle.74361054870438016111387016527789911348374098296207534197496059999683803712082","seed":74361054870438016111387016527789911348374098296207534197496059999683803712082,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_idle/latest run_opts='+sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279022162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.279022162' seed=74361054870438016111387016527789911348374098296207534197496059999683803712082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74361054870438016111387016527789911348374098296207534197496059999683803712082 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_masking_off","qual_name":"1.chip_sw_aes_masking_off.28331132204988443661816798047645934280324980386808883483541728076421167876005","seed":28331132204988443661816798047645934280324980386808883483541728076421167876005,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_masking_off/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_masking_off/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_masking_off/latest run_opts='+sw_build_device=sim_dv +sw_images=aes_masking_off_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2655029157 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.2655029157' seed=28331132204988443661816798047645934280324980386808883483541728076421167876005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_masking_off_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28331132204988443661816798047645934280324980386808883483541728076421167876005 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_masking_off/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_masking_off_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_aes_masking_off_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.57812672022638751739402982909077798432557742108373097520680708337971500876486","seed":57812672022638751739402982909077798432557742108373097520680708337971500876486,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_test/latest run_opts='+sw_build_device=sim_dv +sw_images=alert_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3017474758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_test.3017474758' seed=57812672022638751739402982909077798432557742108373097520680708337971500876486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/autogen/top_darjeeling:alert_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57812672022638751739402982909077798432557742108373097520680708337971500876486 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/autogen/top_darjeeling:alert_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"1.chip_sw_alert_handler_escalation.3036770512881079321630094361168244435978795749540700828752211854253728140764","seed":3036770512881079321630094361168244435978795749540700828752211854253728140764,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772714460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3772714460' seed=3036770512881079321630094361168244435978795749540700828752211854253728140764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3036770512881079321630094361168244435978795749540700828752211854253728140764 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_alert_handler_escalation_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_ping_timeout","qual_name":"1.chip_sw_alert_handler_ping_timeout.89227931359185061941250619472499397244961534062096910716811795364325144813676","seed":89227931359185061941250619472499397244961534062096910716811795364325144813676,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest run_opts='+en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2190631020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.2190631020' seed=89227931359185061941250619472499397244961534062096910716811795364325144813676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_ping_timeout_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89227931359185061941250619472499397244961534062096910716811795364325144813676 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_ping_timeout_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.93698598964732056471264312465237787239729198226066108219968675139262457961297","seed":93698598964732056471264312465237787239729198226066108219968675139262457961297,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.158s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.95365280138238786971440060118148190448087743353128282139481417498468792460698","seed":95365280138238786971440060118148190448087743353128282139481417498468792460698,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.19198300663253697668066999020026507388053580280155372724760466574074667016514","seed":19198300663253697668066999020026507388053580280155372724760466574074667016514,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.155s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"1.chip_sw_alert_handler_lpg_clkoff.64715531199619837488969050199442316749745668634014632124541516272912525286128","seed":64715531199619837488969050199442316749745668634014632124541516272912525286128,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.166s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"1.chip_sw_alert_handler_lpg_reset_toggle.38245323651974054478799800644520638622070701784647016146736437160448004512797","seed":38245323651974054478799800644520638622070701784647016146736437160448004512797,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.200s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"1.chip_sw_alert_handler_entropy.105101697862590461371916079915123564734349506775998315059417617153344921981254","seed":105101697862590461371916079915123564734349506775998315059417617153344921981254,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3418935622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3418935622' seed=105101697862590461371916079915123564734349506775998315059417617153344921981254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:alert_handler_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105101697862590461371916079915123564734349506775998315059417617153344921981254 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:alert_handler_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_alert_handler_entropy_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_entropy","qual_name":"1.chip_sw_aes_entropy.55775175908405202966467805789378452494215635895306697266339011731991789176142","seed":55775175908405202966467805789378452494215635895306697266339011731991789176142,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_entropy/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2546337102 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2546337102' seed=55775175908405202966467805789378452494215635895306697266339011731991789176142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55775175908405202966467805789378452494215635895306697266339011731991789176142 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_kat_test","qual_name":"1.chip_sw_csrng_kat_test.82508084646546047630004723603514910558284302367780023141797068407872210192989","seed":82508084646546047630004723603514910558284302367780023141797068407872210192989,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261188701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3261188701' seed=82508084646546047630004723603514910558284302367780023141797068407872210192989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:csrng_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82508084646546047630004723603514910558284302367780023141797068407872210192989 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:csrng_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"1.chip_sw_csrng_fuse_en_sw_app_read_test.21957716238295827930684036181967896642633313830157992714893965898258783790591","seed":21957716238295827930684036181967896642633313830157992714893965898258783790591,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3322799615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3322799615' seed=21957716238295827930684036181967896642633313830157992714893965898258783790591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21957716238295827930684036181967896642633313830157992714893965898258783790591 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_csrng","qual_name":"1.chip_sw_entropy_src_csrng.77276418141559500439508781859648003350351122937055853016153671151156542692089","seed":77276418141559500439508781859648003350351122937055853016153671151156542692089,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest run_opts='+sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1175837433 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1175837433' seed=77276418141559500439508781859648003350351122937055853016153671151156542692089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_csrng_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77276418141559500439508781859648003350351122937055853016153671151156542692089 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_csrng_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_kat_test","qual_name":"1.chip_sw_entropy_src_kat_test.76501768846048042816836019786677863595067917706654825450281975379781819618432","seed":76501768846048042816836019786677863595067917706654825450281975379781819618432,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2205734016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2205734016' seed=76501768846048042816836019786677863595067917706654825450281975379781819618432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76501768846048042816836019786677863595067917706654825450281975379781819618432 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_ast_rng_req","qual_name":"1.chip_sw_entropy_src_ast_rng_req.18899048696770120759695377047982125591193214998033427284683019194906883089899","seed":18899048696770120759695377047982125591193214998033427284683019194906883089899,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177169899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.177169899' seed=18899048696770120759695377047982125591193214998033427284683019194906883089899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_ast_rng_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18899048696770120759695377047982125591193214998033427284683019194906883089899 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_ast_rng_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc","qual_name":"1.chip_sw_hmac_enc.92014882778914222886791731954253281124504514037209502550095797909369696756082","seed":92014882778914222886791731954253281124504514037209502550095797909369696756082,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885441394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3885441394' seed=92014882778914222886791731954253281124504514037209502550095797909369696756082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92014882778914222886791731954253281124504514037209502550095797909369696756082 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"1.chip_sw_hmac_enc_jitter_en.66431390729909006972109067941911761516294402905368086981497480989652691414601","seed":66431390729909006972109067941911761516294402905368086981497480989652691414601,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest run_opts='+en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469279817 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1469279817' seed=66431390729909006972109067941911761516294402905368086981497480989652691414601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66431390729909006972109067941911761516294402905368086981497480989652691414601 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_idle","qual_name":"1.chip_sw_hmac_enc_idle.49722331120465959216037631203637897372738395005110928292088169690833044274827","seed":49722331120465959216037631203637897372738395005110928292088169690833044274827,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3927867019 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_idle.3927867019' seed=49722331120465959216037631203637897372738395005110928292088169690833044274827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49722331120465959216037631203637897372738395005110928292088169690833044274827 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_cshake","qual_name":"1.chip_sw_kmac_mode_cshake.113488103813567508689012828897612014429353221315568156790761290844175552516152","seed":113488103813567508689012828897612014429353221315568156790761290844175552516152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3469774904 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3469774904' seed=113488103813567508689012828897612014429353221315568156790761290844175552516152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_cshake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113488103813567508689012828897612014429353221315568156790761290844175552516152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_cshake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac","qual_name":"1.chip_sw_kmac_mode_kmac.99360313322870476694263882775893433496477152270236460242594028806196142649290","seed":99360313322870476694263882775893433496477152270236460242594028806196142649290,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048320970 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac.3048320970' seed=99360313322870476694263882775893433496477152270236460242594028806196142649290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99360313322870476694263882775893433496477152270236460242594028806196142649290 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"1.chip_sw_kmac_mode_kmac_jitter_en.97205480444081468441988127689264511644313260693231681134094642453950363931667","seed":97205480444081468441988127689264511644313260693231681134094642453950363931667,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest run_opts='+en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809467923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2809467923' seed=97205480444081468441988127689264511644313260693231681134094642453950363931667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97205480444081468441988127689264511644313260693231681134094642453950363931667 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"1.chip_sw_kmac_app_rom.121230921937016198549105629711460977243708071483088093483808229015587675341","seed":121230921937016198549105629711460977243708071483088093483808229015587675341,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_app_rom_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1829788877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_app_rom.1829788877' seed=121230921937016198549105629711460977243708071483088093483808229015587675341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_app_rom_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=121230921937016198549105629711460977243708071483088093483808229015587675341 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_app_rom_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_idle","qual_name":"1.chip_sw_kmac_idle.95529157633430416648738871321457070637751142840137314269304558617487737070141","seed":95529157633430416648738871321457070637751142840137314269304558617487737070141,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_idle/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2428740157 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_idle.2428740157' seed=95529157633430416648738871321457070637751142840137314269304558617487737070141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95529157633430416648738871321457070637751142840137314269304558617487737070141 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"1.chip_sw_rom_ctrl_integrity_check.19376869178773746799233703208421747420567795587159552789329751490630790480115","seed":19376869178773746799233703208421747420567795587159552789329751490630790480115,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest run_opts='+sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263941363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2263941363' seed=19376869178773746799233703208421747420567795587159552789329751490630790480115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19376869178773746799233703208421747420567795587159552789329751490630790480115 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_ctrl_integrity_check_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access","qual_name":"1.chip_sw_sram_ctrl_scrambled_access.36863455562471806784657329656586227436561737693454939866007384595684302026596","seed":36863455562471806784657329656586227436561737693454939866007384595684302026596,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest run_opts='+sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2700375908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access.2700375908' seed=36863455562471806784657329656586227436561737693454939866007384595684302026596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36863455562471806784657329656586227436561737693454939866007384595684302026596 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"1.chip_sw_sram_ctrl_scrambled_access_jitter_en.9990238802339673679250423190660062243857084825732252072472592932076794789368","seed":9990238802339673679250423190660062243857084825732252072472592932076794789368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest run_opts='+sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1856617976 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1856617976' seed=9990238802339673679250423190660062243857084825732252072472592932076794789368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9990238802339673679250423190660062243857084825732252072472592932076794789368 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"1.chip_sw_sram_ctrl_execution_main.42735673886186658126478661178699904088560558044397000640873229527803843804478","seed":42735673886186658126478661178699904088560558044397000640873229527803843804478,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest run_opts='+sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2050194750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2050194750' seed=42735673886186658126478661178699904088560558044397000640873229527803843804478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42735673886186658126478661178699904088560558044397000640873229527803843804478 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_execution_main_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.51565227236673463167252341498919770612031052823250348915435965915447331701742","seed":51565227236673463167252341498919770612031052823250348915435965915447331701742,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2719007726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2719007726' seed=51565227236673463167252341498919770612031052823250348915435965915447331701742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51565227236673463167252341498919770612031052823250348915435965915447331701742 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_prim_tl_access","qual_name":"1.chip_prim_tl_access.61190758895646869057884661894910690572515703263391443111927310889339535033745","seed":61190758895646869057884661894910690572515703263391443111927310889339535033745,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_prim_tl_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_prim_tl_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_prim_tl_access/latest run_opts='+en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1693255057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1693255057' seed=61190758895646869057884661894910690572515703263391443111927310889339535033745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61190758895646869057884661894910690572515703263391443111927310889339535033745 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_prim_tl_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_prim_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_plic_all_irqs_0","qual_name":"1.chip_plic_all_irqs_0.110837799532389293680564428549060108634770251938278274966428945886442375902654","seed":110837799532389293680564428549060108634770251938278274966428945886442375902654,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_0/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3768350142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_plic_all_irqs_0.3768350142' seed=110837799532389293680564428549060108634770251938278274966428945886442375902654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_0:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110837799532389293680564428549060108634770251938278274966428945886442375902654 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_0:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_plic_all_irqs_10","qual_name":"1.chip_plic_all_irqs_10.65142381145971398572677652558967808879455009609812907756622331484140408422180","seed":65142381145971398572677652558967808879455009609812907756622331484140408422180,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_10/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_10/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_10/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982873380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_plic_all_irqs_10.1982873380' seed=65142381145971398572677652558967808879455009609812907756622331484140408422180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_10:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65142381145971398572677652558967808879455009609812907756622331484140408422180 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_plic_all_irqs_10/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_10:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_plic_sw_irq","qual_name":"1.chip_sw_plic_sw_irq.46776921739579039321013377759445212895538349890134383232958247035534617760037","seed":46776921739579039321013377759445212895538349890134383232958247035534617760037,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_sw_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2147635493 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_plic_sw_irq.2147635493' seed=46776921739579039321013377759445212895538349890134383232958247035534617760037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:plic_sw_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46776921739579039321013377759445212895538349890134383232958247035534617760037 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:plic_sw_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"1.chip_sw_clkmgr_off_aes_trans.50942684664493240206665677285724127367548209823421375398769455127795978358145","seed":50942684664493240206665677285724127367548209823421375398769455127795978358145,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3184938369 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3184938369' seed=50942684664493240206665677285724127367548209823421375398769455127795978358145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_aes_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50942684664493240206665677285724127367548209823421375398769455127795978358145 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_aes_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"1.chip_sw_clkmgr_off_hmac_trans.30758409315213618113710880646076701296460991124185189791579818118278587515039","seed":30758409315213618113710880646076701296460991124185189791579818118278587515039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1610776735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1610776735' seed=30758409315213618113710880646076701296460991124185189791579818118278587515039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_hmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30758409315213618113710880646076701296460991124185189791579818118278587515039 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_hmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"1.chip_sw_clkmgr_off_kmac_trans.39559629128468127736395247604511208542566333009922430270198888709926678903320","seed":39559629128468127736395247604511208542566333009922430270198888709926678903320,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3257350680 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3257350680' seed=39559629128468127736395247604511208542566333009922430270198888709926678903320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_kmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39559629128468127736395247604511208542566333009922430270198888709926678903320 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_kmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"1.chip_sw_clkmgr_off_otbn_trans.60683092364806701832338149386825028749936210656092991012939351734094434004572","seed":60683092364806701832338149386825028749936210656092991012939351734094434004572,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758667868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2758667868' seed=60683092364806701832338149386825028749936210656092991012939351734094434004572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60683092364806701832338149386825028749936210656092991012939351734094434004572 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"1.chip_sw_clkmgr_reset_frequency.43924391693903064971720332749446255292805558453030804965848105795899464798958","seed":43924391693903064971720332749446255292805558453030804965848105795899464798958,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=514511598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.514511598' seed=43924391693903064971720332749446255292805558453030804965848105795899464798958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:clkmgr_reset_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43924391693903064971720332749446255292805558453030804965848105795899464798958 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:clkmgr_reset_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_jitter","qual_name":"1.chip_sw_clkmgr_jitter.49407242120488749320471827661116060695506428833696254654873636843262131900756","seed":49407242120488749320471827661116060695506428833696254654873636843262131900756,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4022145364 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter.4022145364' seed=49407242120488749320471827661116060695506428833696254654873636843262131900756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49407242120488749320471827661116060695506428833696254654873636843262131900756 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"1.chip_sw_clkmgr_sleep_frequency.51730567172287814346002191727109911975947932372987184444034703707219161928165","seed":51730567172287814346002191727109911975947932372987184444034703707219161928165,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1355698661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1355698661' seed=51730567172287814346002191727109911975947932372987184444034703707219161928165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:clkmgr_sleep_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51730567172287814346002191727109911975947932372987184444034703707219161928165 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:clkmgr_sleep_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_jtag_csr_rw","qual_name":"1.chip_jtag_csr_rw.95271415833109152833653621442647816093963178252363475449257309027502148172291","seed":95271415833109152833653621442647816093963178252363475449257309027502148172291,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest run_opts='+en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1885485571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.1885485571' seed=95271415833109152833653621442647816093963178252363475449257309027502148172291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95271415833109152833653621442647816093963178252363475449257309027502148172291 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_jtag_csr_rw_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_jtag_mem_access","qual_name":"1.chip_jtag_mem_access.81171705106206512224027458742557387128800132611179884142358200271614534925150","seed":81171705106206512224027458742557387128800132611179884142358200271614534925150,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest run_opts='+create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1770699614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1770699614' seed=81171705106206512224027458742557387128800132611179884142358200271614534925150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81171705106206512224027458742557387128800132611179884142358200271614534925150 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_jtag_mem_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"1.chip_sw_ast_clk_outputs.59178484648203557283253733264595078880252934766178791607822558080462780362699","seed":59178484648203557283253733264595078880252934766178791607822558080462780362699,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest run_opts='+sw_build_device=sim_dv +sw_images=ast_clk_outs_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220776395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.4220776395' seed=59178484648203557283253733264595078880252934766178791607822558080462780362699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:ast_clk_outs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59178484648203557283253733264595078880252934766178791607822558080462780362699 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:ast_clk_outs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"1.chip_sw_lc_ctrl_program_error.109169482243563838063976662510449808842320256026305040318040436039726726171786","seed":109169482243563838063976662510449808842320256026305040318040436039726726171786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4258843786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.4258843786' seed=109169482243563838063976662510449808842320256026305040318040436039726726171786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests/sim_dv:lc_ctrl_program_error:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109169482243563838063976662510449808842320256026305040318040436039726726171786 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests/sim_dv:lc_ctrl_program_error:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_program_error_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_rv_dm_ndm_reset_req","qual_name":"1.chip_rv_dm_ndm_reset_req.46802976080851659121869724531129938873593699535954271058224202574856457036021","seed":46802976080851659121869724531129938873593699535954271058224202574856457036021,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest run_opts='+en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_dev:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3729531125 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3729531125' seed=46802976080851659121869724531129938873593699535954271058224202574856457036021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_ndm_reset_req_dev:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46802976080851659121869724531129938873593699535954271058224202574856457036021 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_ndm_reset_req_dev:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_rv_dm_ndm_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.10087057100514981190998013173325907327045979918360713620398718918113553288663","seed":10087057100514981190998013173325907327045979918360713620398718918113553288663,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2934443479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2934443479' seed=10087057100514981190998013173325907327045979918360713620398718918113553288663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10087057100514981190998013173325907327045979918360713620398718918113553288663 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.98881380302852666788849557395686211751363870069177997720032359661343636860680","seed":98881380302852666788849557395686211751363870069177997720032359661343636860680,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3731500808 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3731500808' seed=98881380302852666788849557395686211751363870069177997720032359661343636860680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_access_after_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98881380302852666788849557395686211751363870069177997720032359661343636860680 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_access_after_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_access_after_wakeup_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"1.chip_sw_rv_dm_access_after_escalation_reset.105532936333446154665695619599984248815425891259341726550938925286189628032858","seed":105532936333446154665695619599984248815425891259341726550938925286189628032858,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=377653082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.377653082' seed=105532936333446154665695619599984248815425891259341726550938925286189628032858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105532936333446154665695619599984248815425891259341726550938925286189628032858 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_access_after_escalation_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.113211616604394824713930825093487955592452683400401701121559819281146066531039","seed":113211616604394824713930825093487955592452683400401701121559819281146066531039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest run_opts='+en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2490659551 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2490659551' seed=113211616604394824713930825093487955592452683400401701121559819281146066531039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113211616604394824713930825093487955592452683400401701121559819281146066531039 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_rv_dm_lc_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_address_translation","qual_name":"1.chip_sw_rv_core_ibex_address_translation.34637949272704444245897228442733560975571100773040301590437849766119036003755","seed":34637949272704444245897228442733560975571100773040301590437849766119036003755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest run_opts='+sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=314680747 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.314680747' seed=34637949272704444245897228442733560975571100773040301590437849766119036003755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_address_translation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34637949272704444245897228442733560975571100773040301590437849766119036003755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_address_translation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"1.chip_sw_rv_core_ibex_lockstep_glitch.43773650932900976831443133135691401002367085240830371459743486652834733798416","seed":43773650932900976831443133135691401002367085240830371459743486652834733798416,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest run_opts='+disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046131728 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1046131728' seed=43773650932900976831443133135691401002367085240830371459743486652834733798416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43773650932900976831443133135691401002367085240830371459743486652834733798416 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_core_ibex_lockstep_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_icache_invalidate","qual_name":"1.chip_sw_rv_core_ibex_icache_invalidate.22306888434834758442283875372328208259039029047797193696208823167166819558128","seed":22306888434834758442283875372328208259039029047797193696208823167166819558128,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4132135664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.4132135664' seed=22306888434834758442283875372328208259039029047797193696208823167166819558128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_core_ibex_icache_invalidate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22306888434834758442283875372328208259039029047797193696208823167166819558128 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_core_ibex_icache_invalidate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_core_ibex_icache_invalidate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"1.chip_padctrl_attributes.70398863589125218973647259521718362917937497930958050923401884609768145979407","seed":70398863589125218973647259521718362917937497930958050923401884609768145979407,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3014821903 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_padctrl_attributes.3014821903' seed=70398863589125218973647259521718362917937497930958050923401884609768145979407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70398863589125218973647259521718362917937497930958050923401884609768145979407 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_jitter_reduced_freq","qual_name":"1.chip_sw_clkmgr_jitter_reduced_freq.100690682347652672426866539540351154651968112247203272605990185367383292571461","seed":100690682347652672426866539540351154651968112247203272605990185367383292571461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest run_opts='+cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727065925 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1727065925' seed=100690682347652672426866539540351154651968112247203272605990185367383292571461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100690682347652672426866539540351154651968112247203272605990185367383292571461 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"1.chip_sw_aes_enc_jitter_en_reduced_freq.104524879694185920359262114443705318092159921628798701418897949953728067273116","seed":104524879694185920359262114443705318092159921628798701418897949953728067273116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest run_opts='+sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=103154076 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.103154076' seed=104524879694185920359262114443705318092159921628798701418897949953728067273116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104524879694185920359262114443705318092159921628798701418897949953728067273116 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"1.chip_sw_hmac_enc_jitter_en_reduced_freq.59794643854195347478985898469493150462518396631966977777594220496718902020155","seed":59794643854195347478985898469493150462518396631966977777594220496718902020155,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest run_opts='+en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3069397051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3069397051' seed=59794643854195347478985898469493150462518396631966977777594220496718902020155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59794643854195347478985898469493150462518396631966977777594220496718902020155 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.13713175065700830848700231366135156982419011548723031334444794930727781677622","seed":13713175065700830848700231366135156982419011548723031334444794930727781677622,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest run_opts='+en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2141731382 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2141731382' seed=13713175065700830848700231366135156982419011548723031334444794930727781677622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13713175065700830848700231366135156982419011548723031334444794930727781677622 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.68158299782402089673879580274063683952025182515288992025566982360007086046770","seed":68158299782402089673879580274063683952025182515288992025566982360007086046770,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest run_opts='+mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=883031602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.883031602' seed=68158299782402089673879580274063683952025182515288992025566982360007086046770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68158299782402089673879580274063683952025182515288992025566982360007086046770 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_power_virus","qual_name":"1.chip_sw_power_virus.1318979287457940932253619401865630228464819700341584881981775367634543165570","seed":1318979287457940932253619401865630228464819700341584881981775367634543165570,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.058s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_dma_inline_hashing","qual_name":"1.chip_sw_dma_inline_hashing.114471577685878622939813881530435124681549822492494070939050489881769073455741","seed":114471577685878622939813881530435124681549822492494070939050489881769073455741,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_inline_hashing/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_inline_hashing/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_inline_hashing/latest run_opts='+sw_test_timeout_ns=22_000_000 +abort=0 +sw_build_device=sim_dv +sw_images=dma_inline_hashing:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549625469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_dma_spi_hw_handshake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_dma_inline_hashing.2549625469' seed=114471577685878622939813881530435124681549822492494070939050489881769073455741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:dma_inline_hashing:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114471577685878622939813881530435124681549822492494070939050489881769073455741 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_inline_hashing/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:dma_inline_hashing:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_dma_spi_hw_handshake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_dma_abort","qual_name":"1.chip_sw_dma_abort.39182134380904454337286189160082427197299329445847412588874591048010519145023","seed":39182134380904454337286189160082427197299329445847412588874591048010519145023,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest run_opts='+sw_test_timeout_ns=22_000_000 +abort=1 +sw_build_device=sim_dv +sw_images=dma_abort:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2132404799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_dma_spi_hw_handshake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_dma_abort.2132404799' seed=39182134380904454337286189160082427197299329445847412588874591048010519145023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:dma_abort:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39182134380904454337286189160082427197299329445847412588874591048010519145023 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:dma_abort:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_dma_spi_hw_handshake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"base_rom_e2e_smoke","qual_name":"1.base_rom_e2e_smoke.25411313525458504346238097980021812813571685542618618575921737207669474774299","seed":25411313525458504346238097980021812813571685542618618575921737207669474774299,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.base_rom_e2e_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.base_rom_e2e_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.base_rom_e2e_smoke/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=base_rom_e2e_smoke:7:test_in_second_rom,base_rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866859291 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.base_rom_e2e_smoke.2866859291' seed=25411313525458504346238097980021812813571685542618618575921737207669474774299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom //sw/device/silicon_creator/rom:base_rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25411313525458504346238097980021812813571685542618618575921737207669474774299 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.base_rom_e2e_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom //sw/device/silicon_creator/rom:base_rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_smoke","qual_name":"1.rom_e2e_smoke.110014483914997430826553790548658395626509106872756064553310248244474554453212","seed":110014483914997430826553790548658395626509106872756064553310248244474554453212,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_smoke/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321728220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3321728220' seed=110014483914997430826553790548658395626509106872756064553310248244474554453212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110014483914997430826553790548658395626509106872756064553310248244474554453212 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"1.rom_e2e_shutdown_exception_c.49664434926978447079220689993485679435900095589687951935313763111421082775474","seed":49664434926978447079220689993485679435900095589687951935313763111421082775474,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=206745522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.206745522' seed=49664434926978447079220689993485679435900095589687951935313763111421082775474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49664434926978447079220689993485679435900095589687951935313763111421082775474 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_shutdown_exception_c_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"1.rom_e2e_shutdown_output.16234887324240355460092557174542095550613725738854100386420446380185387650157","seed":16234887324240355460092557174542095550613725738854100386420446380185387650157,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_output/latest run_opts='+sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:6:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2182990957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2182990957' seed=16234887324240355460092557174542095550613725738854100386420446380185387650157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_shutdown_output_test_unlocked0:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16234887324240355460092557174542095550613725738854100386420446380185387650157 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_output/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_shutdown_output_test_unlocked0:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_shutdown_output_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.36202189801649538343294674409367618336701158631972001734176475206532751912057","seed":36202189801649538343294674409367618336701158631972001734176475206532751912057,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.21023858835274250751095851354719976213480377892822222407648357256655661172591","seed":21023858835274250751095851354719976213480377892822222407648357256655661172591,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.87844293772048473823728370214877975433989402279955424768887740963977420782515","seed":87844293772048473823728370214877975433989402279955424768887740963977420782515,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.29304973749807098085741867311392183251206015805313987566286654800795716738762","seed":29304973749807098085741867311392183251206015805313987566286654800795716738762,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.69337320410843418266487722568401031957522230173603840178369329516013335506415","seed":69337320410843418266487722568401031957522230173603840178369329516013335506415,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"1.rom_e2e_static_critical.24298482246890362883375890318578780579566880335257792449249767656764416671596","seed":24298482246890362883375890318578780579566880335257792449249767656764416671596,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_static_critical/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_static_critical/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:6:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2539601772 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.2539601772' seed=24298482246890362883375890318578780579566880335257792449249767656764416671596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24298482246890362883375890318578780579566880335257792449249767656764416671596 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_static_critical/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_meas","qual_name":"1.rom_e2e_keymgr_dpe_init_rom_ext_meas.56751906805893438357823242038695268478178549459346445598639750773242699874655","seed":56751906805893438357823242038695268478178549459346445598639750773242699874655,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599766879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_dpe_init_rom_ext_meas.1599766879' seed=56751906805893438357823242038695268478178549459346445598639750773242699874655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56751906805893438357823242038695268478178549459346445598639750773242699874655 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_no_meas","qual_name":"1.rom_e2e_keymgr_dpe_init_rom_ext_no_meas.6018744102845513570186331411738493701096406237002926865274219960128767513851","seed":6018744102845513570186331411738493701096406237002926865274219960128767513851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_no_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764925179 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_dpe_init_rom_ext_no_meas.764925179' seed=6018744102845513570186331411738493701096406237002926865274219960128767513851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_no_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6018744102845513570186331411738493701096406237002926865274219960128767513851 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_no_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas","qual_name":"1.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas.93194862779552178292097398210086504398131787190246875698704636693726694353303","seed":93194862779552178292097398210086504398131787190246875698704636693726694353303,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_invalid_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1083582871 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas.1083582871' seed=93194862779552178292097398210086504398131787190246875698704636693726694353303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_invalid_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93194862779552178292097398210086504398131787190246875698704636693726694353303 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_invalid_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.108933157283221724548545071261597488966945949429652156944185206088164738094276","seed":108933157283221724548545071261597488966945949429652156944185206088164738094276,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["cwd=/nightly/current_run/opentitan\n","\n","Waiting for it to complete...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.68582318331267405573432892912558197100280939168825247433014698473891213480876","seed":68582318331267405573432892912558197100280939168825247433014698473891213480876,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=247403) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_dev_otbn.3056787395327039835327083876209148884630720416713289437061701282149896904423","seed":3056787395327039835327083876209148884630720416713289437061701282149896904423,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_dev_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719412967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_dev_otbn.719412967' seed=3056787395327039835327083876209148884630720416713289437061701282149896904423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3056787395327039835327083876209148884630720416713289437061701282149896904423 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_dev_sw.49915022444573646368799708763674908858249960910500165374098134746851973760960","seed":49915022444573646368799708763674908858249960910500165374098134746851973760960,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_dev_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4253517760 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_dev_sw.4253517760' seed=49915022444573646368799708763674908858249960910500165374098134746851973760960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49915022444573646368799708763674908858249960910500165374098134746851973760960 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_otbn.112912920803627583098132254904206064937454106628856543633641931445553350335004","seed":112912920803627583098132254904206064937454106628856543633641931445553350335004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2434030108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_prod_otbn.2434030108' seed=112912920803627583098132254904206064937454106628856543633641931445553350335004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112912920803627583098132254904206064937454106628856543633641931445553350335004 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_sw.61337710547233979808763395099075703526933747376481488948590174600139585126433","seed":61337710547233979808763395099075703526933747376481488948590174600139585126433,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802955809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_prod_sw.3802955809' seed=61337710547233979808763395099075703526933747376481488948590174600139585126433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61337710547233979808763395099075703526933747376481488948590174600139585126433 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_end_otbn.78015638531198881068425043322899591549060097567693654388210249374728513549991","seed":78015638531198881068425043322899591549060097567693654388210249374728513549991,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_end_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569355431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_prod_end_otbn.1569355431' seed=78015638531198881068425043322899591549060097567693654388210249374728513549991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78015638531198881068425043322899591549060097567693654388210249374728513549991 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_end_sw.33476680074858943847311063430297824825684900068488092184273714483336647996648","seed":33476680074858943847311063430297824825684900068488092184273714483336647996648,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_end_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3346724072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_prod_end_sw.3346724072' seed=33476680074858943847311063430297824825684900068488092184273714483336647996648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33476680074858943847311063430297824825684900068488092184273714483336647996648 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_rma_otbn.38562634616753883116004005028332319287061443200134970738331641022628137751681","seed":38562634616753883116004005028332319287061443200134970738331641022628137751681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_rma_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3434042497 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_rma_otbn.3434042497' seed=38562634616753883116004005028332319287061443200134970738331641022628137751681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38562634616753883116004005028332319287061443200134970738331641022628137751681 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_rma_sw.82698236359620749671529431643497611162316121045323336761302411544081572668939","seed":82698236359620749671529431643497611162316121045323336761302411544081572668939,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_rma_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4045776395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_sigverify_mod_exp_rma_sw.4045776395' seed=82698236359620749671529431643497611162316121045323336761302411544081572668939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82698236359620749671529431643497611162316121045323336761302411544081572668939 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.40659872491822153130133543144062291030603822146192542607854484644958870785709","seed":40659872491822153130133543144062291030603822146192542607854484644958870785709,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.99567842139856102583227646837320162943808358794036615812591232345927557343486","seed":99567842139856102583227646837320162943808358794036615812591232345927557343486,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.104984825587996088118560512366054413143399367270024451149038347474779971369561","seed":104984825587996088118560512366054413143399367270024451149038347474779971369561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"1.chip_sw_uart_smoketest_signed.109839587708387923171821144241601124064474211734693124657362418465515254721685","seed":109839587708387923171821144241601124064474211734693124657362418465515254721685,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_dpe_functest","qual_name":"1.rom_keymgr_dpe_functest.86639185889579031345953786079173956623466669689129059320577885638456624296183","seed":86639185889579031345953786079173956623466669689129059320577885638456624296183,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_keymgr_dpe_functest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_keymgr_dpe_functest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_keymgr_dpe_functest/latest run_opts='+sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_dpe_functest:6,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3119001847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_dpe_functest.3119001847' seed=86639185889579031345953786079173956623466669689129059320577885638456624296183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest:6 //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86639185889579031345953786079173956623466669689129059320577885638456624296183 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_keymgr_dpe_functest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest:6 //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_smoketest","qual_name":"1.chip_sw_aes_smoketest.80749543715811340231864470746291299125795216364236476877832453625502561775617","seed":80749543715811340231864470746291299125795216364236476877832453625502561775617,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2824908801 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2824908801' seed=80749543715811340231864470746291299125795216364236476877832453625502561775617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80749543715811340231864470746291299125795216364236476877832453625502561775617 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_smoketest","qual_name":"1.chip_sw_aon_timer_smoketest.30925007147138419776652989856991715949012349109995815102359174752374160095991","seed":30925007147138419776652989856991715949012349109995815102359174752374160095991,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=aon_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3111385847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_smoketest.3111385847' seed=30925007147138419776652989856991715949012349109995815102359174752374160095991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30925007147138419776652989856991715949012349109995815102359174752374160095991 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_smoketest","qual_name":"1.chip_sw_clkmgr_smoketest.75939787531223265849975163714535353198833864018386971451695437796435912528249","seed":75939787531223265849975163714535353198833864018386971451695437796435912528249,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2514194809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_smoketest.2514194809' seed=75939787531223265849975163714535353198833864018386971451695437796435912528249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75939787531223265849975163714535353198833864018386971451695437796435912528249 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_smoketest","qual_name":"1.chip_sw_csrng_smoketest.42555731901012062664752992485811676247074349190829215767626899701617117355109","seed":42555731901012062664752992485811676247074349190829215767626899701617117355109,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=csrng_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4010269797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_smoketest.4010269797' seed=42555731901012062664752992485811676247074349190829215767626899701617117355109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:csrng_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42555731901012062664752992485811676247074349190829215767626899701617117355109 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:csrng_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_smoketest","qual_name":"1.chip_sw_entropy_src_smoketest.31920096627509563516943941032335966913330744185048903072579980618852575643488","seed":31920096627509563516943941032335966913330744185048903072579980618852575643488,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest run_opts='+rng_srate_value_min=3 +rng_srate_value_max=10 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2063501152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2063501152' seed=31920096627509563516943941032335966913330744185048903072579980618852575643488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31920096627509563516943941032335966913330744185048903072579980618852575643488 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_gpio_smoketest","qual_name":"1.chip_sw_gpio_smoketest.88951231437232403850353817905075191567184382908008491482456411389160029965478","seed":88951231437232403850353817905075191567184382908008491482456411389160029965478,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=gpio_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248349350 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio_smoketest.1248349350' seed=88951231437232403850353817905075191567184382908008491482456411389160029965478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:gpio_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88951231437232403850353817905075191567184382908008491482456411389160029965478 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:gpio_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_gpio_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_smoketest","qual_name":"1.chip_sw_hmac_smoketest.38180373183676691632264211343892361820589953515485906343529003013204520256301","seed":38180373183676691632264211343892361820589953515485906343529003013204520256301,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2568274733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.2568274733' seed=38180373183676691632264211343892361820589953515485906343529003013204520256301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38180373183676691632264211343892361820589953515485906343529003013204520256301 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_smoketest","qual_name":"1.chip_sw_kmac_smoketest.5872963551627246080297943677027665116441194297986506170099685788839495100319","seed":5872963551627246080297943677027665116441194297986506170099685788839495100319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230609823 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_smoketest.2230609823' seed=5872963551627246080297943677027665116441194297986506170099685788839495100319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5872963551627246080297943677027665116441194297986506170099685788839495100319 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_mbx_smoketest","qual_name":"1.chip_sw_mbx_smoketest.54697131262416467600622275604865151010840255595082574685833362115934072563963","seed":54697131262416467600622275604865151010840255595082574685833362115934072563963,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_mbx_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_mbx_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_mbx_smoketest/latest run_opts='+use_mbx_if=1 +sw_build_device=sim_dv +sw_images=mbx_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1852532987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mbx_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_mbx_smoketest.1852532987' seed=54697131262416467600622275604865151010840255595082574685833362115934072563963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:mbx_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54697131262416467600622275604865151010840255595082574685833362115934072563963 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_mbx_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:mbx_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_mbx_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_smoketest","qual_name":"1.chip_sw_otbn_smoketest.47424131647078768590074970485023943426013707104133058730355007338647022069899","seed":47424131647078768590074970485023943426013707104133058730355007338647022069899,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=otbn_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738036363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_smoketest.3738036363' seed=47424131647078768590074970485023943426013707104133058730355007338647022069899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47424131647078768590074970485023943426013707104133058730355007338647022069899 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_smoketest","qual_name":"1.chip_sw_otp_ctrl_smoketest.25701466054190582275283263617607452732148526236422719494757269595950135773456","seed":25701466054190582275283263617607452732148526236422719494757269595950135773456,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3408791824 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_smoketest.3408791824' seed=25701466054190582275283263617607452732148526236422719494757269595950135773456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otp_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25701466054190582275283263617607452732148526236422719494757269595950135773456 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otp_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_plic_smoketest","qual_name":"1.chip_sw_rv_plic_smoketest.8757709102904967893512377944743681336031831505186511053317678093764643418013","seed":8757709102904967893512377944743681336031831505186511053317678093764643418013,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_plic_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=988704669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_plic_smoketest.988704669' seed=8757709102904967893512377944743681336031831505186511053317678093764643418013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_plic_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8757709102904967893512377944743681336031831505186511053317678093764643418013 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_plic_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_timer_smoketest","qual_name":"1.chip_sw_rv_timer_smoketest.63972982507382539447627906403416836892376421286114611866891168902797160422561","seed":63972982507382539447627906403416836892376421286114611866891168902797160422561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214744737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_timer_smoketest.3214744737' seed=63972982507382539447627906403416836892376421286114611866891168902797160422561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63972982507382539447627906403416836892376421286114611866891168902797160422561 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_smoketest","qual_name":"1.chip_sw_rstmgr_smoketest.20721894774551960278796421854816406190948328858449170723531008966820988208894","seed":20721894774551960278796421854816406190948328858449170723531008966820988208894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4161816318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_smoketest.4161816318' seed=20721894774551960278796421854816406190948328858449170723531008966820988208894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20721894774551960278796421854816406190948328858449170723531008966820988208894 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_smoketest","qual_name":"1.chip_sw_sram_ctrl_smoketest.6004563906689276107097998573135078293286487854548032046863808176857121108339","seed":6004563906689276107097998573135078293286487854548032046863808176857121108339,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1598108019 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1598108019' seed=6004563906689276107097998573135078293286487854548032046863808176857121108339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6004563906689276107097998573135078293286487854548032046863808176857121108339 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_smoketest","qual_name":"1.chip_sw_uart_smoketest.82404887196555606541310771145052404790271903348927998996445387829222552422663","seed":82404887196555606541310771145052404790271903348927998996445387829222552422663,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=uart_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1628752135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_smoketest.1628752135' seed=82404887196555606541310771145052404790271903348927998996445387829222552422663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82404887196555606541310771145052404790271903348927998996445387829222552422663 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"1.xbar_smoke.25607637218160082514938235825633260110569364609695692811889295664292303140982","seed":25607637218160082514938235825633260110569364609695692811889295664292303140982,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1453521014 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1453521014' seed=25607637218160082514938235825633260110569364609695692811889295664292303140982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25607637218160082514938235825633260110569364609695692811889295664292303140982 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"1.xbar_smoke_zero_delays.14249195438830012943783427903706971730736227970647161280347705309135011680995","seed":14249195438830012943783427903706971730736227970647161280347705309135011680995,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1572967139 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1572967139' seed=14249195438830012943783427903706971730736227970647161280347705309135011680995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14249195438830012943783427903706971730736227970647161280347705309135011680995 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"1.xbar_smoke_large_delays.64202669406747275929210163683745930457675308428926720517714229543595025138581","seed":64202669406747275929210163683745930457675308428926720517714229543595025138581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1878557589 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1878557589' seed=64202669406747275929210163683745930457675308428926720517714229543595025138581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64202669406747275929210163683745930457675308428926720517714229543595025138581 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"1.xbar_smoke_slow_rsp.74684921868467643865185417070433496261005164995983261711419405000162176802891","seed":74684921868467643865185417070433496261005164995983261711419405000162176802891,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955733579 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1955733579' seed=74684921868467643865185417070433496261005164995983261711419405000162176802891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74684921868467643865185417070433496261005164995983261711419405000162176802891 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"1.xbar_random.9690848650549104007220691001983613826722792265405205217637197803055954346058","seed":9690848650549104007220691001983613826722792265405205217637197803055954346058,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1142505546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1142505546' seed=9690848650549104007220691001983613826722792265405205217637197803055954346058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9690848650549104007220691001983613826722792265405205217637197803055954346058 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"1.xbar_random_zero_delays.40385081157151088148372770510934122009547669143374276709126362397206495884381","seed":40385081157151088148372770510934122009547669143374276709126362397206495884381,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287306845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.287306845' seed=40385081157151088148372770510934122009547669143374276709126362397206495884381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40385081157151088148372770510934122009547669143374276709126362397206495884381 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"1.xbar_random_large_delays.108206550024247311332334942168891740786656520923132820223861835930777144271946","seed":108206550024247311332334942168891740786656520923132820223861835930777144271946,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778290762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3778290762' seed=108206550024247311332334942168891740786656520923132820223861835930777144271946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108206550024247311332334942168891740786656520923132820223861835930777144271946 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"1.xbar_random_slow_rsp.35193926559261284177397027811560306111158942194368360296002190037894759433431","seed":35193926559261284177397027811560306111158942194368360296002190037894759433431,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2059912407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2059912407' seed=35193926559261284177397027811560306111158942194368360296002190037894759433431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35193926559261284177397027811560306111158942194368360296002190037894759433431 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"1.xbar_access_same_device.6430236565576424876188350729266503990447193830554002373461107765310751485427","seed":6430236565576424876188350729266503990447193830554002373461107765310751485427,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1252503027 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1252503027' seed=6430236565576424876188350729266503990447193830554002373461107765310751485427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6430236565576424876188350729266503990447193830554002373461107765310751485427 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"1.xbar_access_same_device_slow_rsp.43407456154110825483426034592952825517925359423568714698243709520724915264466","seed":43407456154110825483426034592952825517925359423568714698243709520724915264466,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2139495378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2139495378' seed=43407456154110825483426034592952825517925359423568714698243709520724915264466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43407456154110825483426034592952825517925359423568714698243709520724915264466 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"1.xbar_same_source.76186742888675011710585992751377633301353077189819293176659261001564629202628","seed":76186742888675011710585992751377633301353077189819293176659261001564629202628,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4210521796 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4210521796' seed=76186742888675011710585992751377633301353077189819293176659261001564629202628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76186742888675011710585992751377633301353077189819293176659261001564629202628 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"1.xbar_error_random.24775386068107559419548876933313444919204362533604134076784108637911534145038","seed":24775386068107559419548876933313444919204362533604134076784108637911534145038,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2111966734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2111966734' seed=24775386068107559419548876933313444919204362533604134076784108637911534145038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24775386068107559419548876933313444919204362533604134076784108637911534145038 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"1.xbar_unmapped_addr.10903402035300759829028102375599813503599696939162984419927506461835606098435","seed":10903402035300759829028102375599813503599696939162984419927506461835606098435,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=378798595 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.378798595' seed=10903402035300759829028102375599813503599696939162984419927506461835606098435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10903402035300759829028102375599813503599696939162984419927506461835606098435 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"1.xbar_error_and_unmapped_addr.44578585613221308878944229386067357714467546544966009485763232318311530479258","seed":44578585613221308878944229386067357714467546544966009485763232318311530479258,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334717082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3334717082' seed=44578585613221308878944229386067357714467546544966009485763232318311530479258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44578585613221308878944229386067357714467546544966009485763232318311530479258 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"1.xbar_stress_all.52131904956521817234113991738152677731241566738639240529562036021364832862925","seed":52131904956521817234113991738152677731241566738639240529562036021364832862925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572681933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2572681933' seed=52131904956521817234113991738152677731241566738639240529562036021364832862925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52131904956521817234113991738152677731241566738639240529562036021364832862925 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"1.xbar_stress_all_with_rand_reset.83661732601382322892140268928766271201952079217001297620642459601296073876404","seed":83661732601382322892140268928766271201952079217001297620642459601296073876404,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2081612724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2081612724' seed=83661732601382322892140268928766271201952079217001297620642459601296073876404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83661732601382322892140268928766271201952079217001297620642459601296073876404 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"1.xbar_stress_all_with_error.94667997447087511083207781872406334919171069883441913281549989272997463077224","seed":94667997447087511083207781872406334919171069883441913281549989272997463077224,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2948608360 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2948608360' seed=94667997447087511083207781872406334919171069883441913281549989272997463077224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94667997447087511083207781872406334919171069883441913281549989272997463077224 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"1.xbar_stress_all_with_reset_error.97155743070750336330828315626047127651765802710174648627602013636853881543023","seed":97155743070750336330828315626047127651765802710174648627602013636853881543023,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310286703 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.310286703' seed=97155743070750336330828315626047127651765802710174648627602013636853881543023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97155743070750336330828315626047127651765802710174648627602013636853881543023 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_same_csr_outstanding","qual_name":"2.chip_same_csr_outstanding.44088302657963521457427746476076918136616497317076865950284762077034895263565","seed":44088302657963521457427746476076918136616497317076865950284762077034895263565,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_same_csr_outstanding/latest run_opts='+test_timeout_ns=120_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2249869133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2249869133' seed=44088302657963521457427746476076918136616497317076865950284762077034895263565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44088302657963521457427746476076918136616497317076865950284762077034895263565 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_same_csr_outstanding/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_rom","qual_name":"2.chip_sw_example_rom.86127001750379256490368616157000302973751683155553662962570521059174248053561","seed":86127001750379256490368616157000302973751683155553662962570521059174248053561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1944812345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1944812345' seed=86127001750379256490368616157000302973751683155553662962570521059174248053561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:example_test_from_rom:0:test_in_rom'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86127001750379256490368616157000302973751683155553662962570521059174248053561 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images=//sw/device/tests:example_test_from_rom:0:test_in_rom uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"2.chip_sw_example_manufacturer.96593812882231696773279161419191607341696302316815783405579492071154095787642","seed":96593812882231696773279161419191607341696302316815783405579492071154095787642,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1499762298 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1499762298' seed=96593812882231696773279161419191607341696302316815783405579492071154095787642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96593812882231696773279161419191607341696302316815783405579492071154095787642 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_example_concurrency","qual_name":"2.chip_sw_example_concurrency.35858144145044953517553644431319242637195383393896868240535324554892720438742","seed":35858144145044953517553644431319242637195383393896868240535324554892720438742,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest run_opts='+sw_build_device=sim_dv +sw_images=example_concurrency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1051950550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.1051950550' seed=35858144145044953517553644431319242637195383393896868240535324554892720438742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35858144145044953517553644431319242637195383393896868240535324554892720438742 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"2.chip_sw_all_escalation_resets.3782907908014303616641893659234635117585235589819603033273422510592241253543","seed":3782907908014303616641893659234635117585235589819603033273422510592241253543,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=195378343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.195378343' seed=3782907908014303616641893659234635117585235589819603033273422510592241253543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3782907908014303616641893659234635117585235589819603033273422510592241253543 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"2.chip_sw_rstmgr_rst_cnsty_escalation.89970688095336440549643773889365032100180282527369669897147787301253484969596","seed":89970688095336440549643773889365032100180282527369669897147787301253484969596,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2872901244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2872901244' seed=89970688095336440549643773889365032100180282527369669897147787301253484969596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89970688095336440549643773889365032100180282527369669897147787301253484969596 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rstmgr_cnsty_fault_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"2.chip_sw_data_integrity_escalation.75654663920580537811953889787567124024052390104604897554720049482103034421716","seed":75654663920580537811953889787567124024052390104604897554720049482103034421716,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4137361876 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.4137361876' seed=75654663920580537811953889787567124024052390104604897554720049482103034421716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75654663920580537811953889787567124024052390104604897554720049482103034421716 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_data_integrity_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"2.chip_sw_sleep_pin_wake.113122005232286787271910090095575286119709303209289359389071824105595886094123","seed":113122005232286787271910090095575286119709303209289359389071824105595886094123,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest run_opts='+use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4178560811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.4178560811' seed=113122005232286787271910090095575286119709303209289359389071824105595886094123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sleep_pin_wake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113122005232286787271910090095575286119709303209289359389071824105595886094123 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sleep_pin_wake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sleep_pin_wake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"2.chip_sw_sleep_pin_retention.7144000915216594721529816529392002483315458898616801160588989924282889654977","seed":7144000915216594721529816529392002483315458898616801160588989924282889654977,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest run_opts='+sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=316396225 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.316396225' seed=7144000915216594721529816529392002483315458898616801160588989924282889654977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sleep_pin_retention_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7144000915216594721529816529392002483315458898616801160588989924282889654977 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sleep_pin_retention_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sleep_pin_retention_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"2.chip_sw_uart_tx_rx.37460234293830522043230107845914339229747788526261888875061167823164899277931","seed":37460234293830522043230107845914339229747788526261888875061167823164899277931,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest run_opts='+uart_idx=0 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3499834475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3499834475' seed=37460234293830522043230107845914339229747788526261888875061167823164899277931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37460234293830522043230107845914339229747788526261888875061167823164899277931 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"2.chip_sw_uart_tx_rx_bootstrap.91083660774396563672196430293213099151277915101310938858709625872459410407946","seed":91083660774396563672196430293213099151277915101310938858709625872459410407946,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.380s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"2.chip_sw_inject_scramble_seed.21447086785075182228648923484238621308168759870529260751102094279966666868739","seed":21447086785075182228648923484238621308168759870529260751102094279966666868739,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.068s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"2.chip_sw_exit_test_unlocked_bootstrap.29495875426371878096319286577799836614152376086452138680830405852738284985474","seed":29495875426371878096319286577799836614152376086452138680830405852738284985474,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.714s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"2.chip_sw_uart_rand_baudrate.104152245238599802868295838148129141118393869610778268414676273202267716594205","seed":104152245238599802868295838148129141118393869610778268414676273202267716594205,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4259588637 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.4259588637' seed=104152245238599802868295838148129141118393869610778268414676273202267716594205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104152245238599802868295838148129141118393869610778268414676273202267716594205 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"2.chip_sw_uart_tx_rx_alt_clk_freq.87450914520202952201646569273620451584374130320127751154266892730703731286139","seed":87450914520202952201646569273620451584374130320127751154266892730703731286139,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest run_opts='+sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2636439675 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq.2636439675' seed=87450914520202952201646569273620451584374130320127751154266892730703731286139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87450914520202952201646569273620451584374130320127751154266892730703731286139 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"2.chip_sw_i2c_host_tx_rx.82346423346217966866717281141736655020819064573411043256598619582807959907","seed":82346423346217966866717281141736655020819064573411043256598619582807959907,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest run_opts='+i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1354525027 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1354525027' seed=82346423346217966866717281141736655020819064573411043256598619582807959907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:i2c_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82346423346217966866717281141736655020819064573411043256598619582807959907 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:i2c_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_i2c_host_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"2.chip_sw_i2c_device_tx_rx.13744904328793538490859262710227865666647803048450188793255022831229284784282","seed":13744904328793538490859262710227865666647803048450188793255022831229284784282,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest run_opts='+sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898242714 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.898242714' seed=13744904328793538490859262710227865666647803048450188793255022831229284784282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:i2c_device_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13744904328793538490859262710227865666647803048450188793255022831229284784282 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:i2c_device_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_i2c_device_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"2.chip_sw_spi_device_tpm.20149478281717424912532209976732717070620875247956232722077466925950295748269","seed":20149478281717424912532209976732717070620875247956232722077466925950295748269,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3424530093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3424530093' seed=20149478281717424912532209976732717070620875247956232722077466925950295748269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:spi_device_tpm_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20149478281717424912532209976732717070620875247956232722077466925950295748269 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:spi_device_tpm_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_device_tpm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"2.chip_sw_spi_host_tx_rx.48183267756304090338772666562691689420452203948750337220211405402013737745850","seed":48183267756304090338772666562691689420452203948750337220211405402013737745850,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3053256122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3053256122' seed=48183267756304090338772666562691689420452203948750337220211405402013737745850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48183267756304090338772666562691689420452203948750337220211405402013737745850 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_host_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_host_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_pass_through","qual_name":"2.chip_sw_spi_device_pass_through.92969158960682985141821171603939797817659009265707031572331083643702689429005","seed":92969158960682985141821171603939797817659009265707031572331083643702689429005,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_passthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967945229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1967945229' seed=92969158960682985141821171603939797817659009265707031572331083643702689429005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92969158960682985141821171603939797817659009265707031572331083643702689429005 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_passthrough_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.94235025682780960367789690642735930828814376460648153969061578998925876425482","seed":94235025682780960367789690642735930828814376460648153969061578998925876425482,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest run_opts='+sw_build_device=sim_dv +sw_images=spi_passthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2644931338 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2644931338' seed=94235025682780960367789690642735930828814376460648153969061578998925876425482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94235025682780960367789690642735930828814376460648153969061578998925876425482 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:spi_passthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_spi_passthrough_collision_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_gpio","qual_name":"2.chip_sw_gpio.100348173316309276318048688840340953259442340196836951310226272750070354243656","seed":100348173316309276318048688840340953259442340196836951310226272750070354243656,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio/latest run_opts='+sw_build_device=sim_dv +sw_images=gpio_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197123144 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio.2197123144' seed=100348173316309276318048688840340953259442340196836951310226272750070354243656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:gpio_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100348173316309276318048688840340953259442340196836951310226272750070354243656 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:gpio_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_gpio_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_entropy","qual_name":"2.chip_sw_kmac_entropy.62080711196458644830524569813745682900486094843473583783749947348115302105492","seed":62080711196458644830524569813745682900486094843473583783749947348115302105492,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_entropy/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=757842324 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_entropy.757842324' seed=62080711196458644830524569813745682900486094843473583783749947348115302105492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62080711196458644830524569813745682900486094843473583783749947348115302105492 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"2.chip_sw_lc_ctrl_otp_hw_cfg.72223732458395770748476580395972005148458238433509637800276109318706780037632","seed":72223732458395770748476580395972005148458238433509637800276109318706780037632,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767418880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg.767418880' seed=72223732458395770748476580395972005148458238433509637800276109318706780037632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:lc_ctrl_otp_hw_cfg_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72223732458395770748476580395972005148458238433509637800276109318706780037632 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:lc_ctrl_otp_hw_cfg_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.113828316873556484070200454415596099174719664401987199339251957567472274188851","seed":113828316873556484070200454415596099174719664401987199339251957567472274188851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest run_opts='+use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3041602099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3041602099' seed=113828316873556484070200454415596099174719664401987199339251957567472274188851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113828316873556484070200454415596099174719664401987199339251957567472274188851 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"2.chip_sw_otp_ctrl_lc_signals_dev.84333816902980039537123346095989872570793502188947317802601673723266895609953","seed":84333816902980039537123346095989872570793502188947317802601673723266895609953,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest run_opts='+use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3762192481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3762192481' seed=84333816902980039537123346095989872570793502188947317802601673723266895609953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84333816902980039537123346095989872570793502188947317802601673723266895609953 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"2.chip_sw_otp_ctrl_lc_signals_prod.56495240739459609323870571163305307513463454501660250748105727358118919920923","seed":56495240739459609323870571163305307513463454501660250748105727358118919920923,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest run_opts='+use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3158039835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3158039835' seed=56495240739459609323870571163305307513463454501660250748105727358118919920923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56495240739459609323870571163305307513463454501660250748105727358118919920923 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.5388530683587496081363214778771971807305907876782236720181136224001628789263","seed":5388530683587496081363214778771971807305907876782236720181136224001628789263,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest run_opts='+use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +otp_clear_secret3=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2460703247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2460703247' seed=5388530683587496081363214778771971807305907876782236720181136224001628789263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5388530683587496081363214778771971807305907876782236720181136224001628789263 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"2.chip_sw_otp_ctrl_vendor_test_csr_access.62444247594729234054979998901396574212025674115516626692042286657245481593896","seed":62444247594729234054979998901396574212025674115516626692042286657245481593896,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest run_opts='+sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1243671592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1243671592' seed=62444247594729234054979998901396574212025674115516626692042286657245481593896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62444247594729234054979998901396574212025674115516626692042286657245481593896 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_otp_ctrl_vendor_test_csr_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"2.chip_sw_lc_ctrl_transition.82080702434223566583474376644116775107920619261894717142050345264137986324372","seed":82080702434223566583474376644116775107920619261894717142050345264137986324372,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94582676 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.94582676' seed=82080702434223566583474376644116775107920619261894717142050345264137986324372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82080702434223566583474376644116775107920619261894717142050345264137986324372 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"2.chip_sw_lc_ctrl_rand_to_scrap.79205316973551387859569728675913932047160068180830753335118062166498990176141","seed":79205316973551387859569728675913932047160068180830753335118062166498990176141,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=901068685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.901068685' seed=79205316973551387859569728675913932047160068180830753335118062166498990176141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79205316973551387859569728675913932047160068180830753335118062166498990176141 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_scrap_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_scrap_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.115451537815309846688716382981607433267125928397972104389318366545395926224217","seed":115451537815309846688716382981607433267125928397972104389318366545395926224217,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.496s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.104814896089116738800914289404506958463223137510467361301935159583096493042640","seed":104814896089116738800914289404506958463223137510467361301935159583096493042640,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.341s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"2.chip_sw_lc_walkthrough_prodend.82731295037154096365356411757903971343337445938012970090504682596729798174483","seed":82731295037154096365356411757903971343337445938012970090504682596729798174483,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest run_opts='+flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=798402323 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.798402323' seed=82731295037154096365356411757903971343337445938012970090504682596729798174483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_walkthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82731295037154096365356411757903971343337445938012970090504682596729798174483 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_walkthrough_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_walkthrough_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"2.chip_sw_lc_ctrl_volatile_raw_unlock.100063912681957273434267204871270445827943374644828667805481822545724919772528","seed":100063912681957273434267204871270445827943374644828667805481822545724919772528,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest run_opts='+use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4234147184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.4234147184' seed=100063912681957273434267204871270445827943374644828667805481822545724919772528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100063912681957273434267204871270445827943374644828667805481822545724919772528 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_volatile_raw_unlock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.28368751177424473716494458762184887571313898675349969659877763580230993756148","seed":28368751177424473716494458762184887571313898675349969659877763580230993756148,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest run_opts='+use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2723725300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2723725300' seed=28368751177424473716494458762184887571313898675349969659877763580230993756148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28368751177424473716494458762184887571313898675349969659877763580230993756148 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_volatile_raw_unlock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.79185342101329448744221207002434255672826237598497762924849809958526712403112","seed":79185342101329448744221207002434255672826237598497762924849809958526712403112,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.320s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"2.chip_sw_lc_walkthrough_testunlocks.32336385896225163238283692509756716154747143337445792238926200068835653159489","seed":32336385896225163238283692509756716154747143337445792238926200068835653159489,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest run_opts='+use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3694365249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunlocks.3694365249' seed=32336385896225163238283692509756716154747143337445792238926200068835653159489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32336385896225163238283692509756716154747143337445792238926200068835653159489 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_walkthrough_testunlocks_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_sw_req","qual_name":"2.chip_sw_rstmgr_sw_req.88519114816360082442959668427966312962976432847911218626014753259036331758926","seed":88519114816360082442959668427966312962976432847911218626014753259036331758926,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1092638030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_req.1092638030' seed=88519114816360082442959668427966312962976432847911218626014753259036331758926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_sw_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88519114816360082442959668427966312962976432847911218626014753259036331758926 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_sw_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_sw_rst","qual_name":"2.chip_sw_rstmgr_sw_rst.31760067771067051560016065808765964930775640295954588284934093865156585008752","seed":31760067771067051560016065808765964930775640295954588284934093865156585008752,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2673946224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2673946224' seed=31760067771067051560016065808765964930775640295954588284934093865156585008752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_sw_rst_ctrl_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31760067771067051560016065808765964930775640295954588284934093865156585008752 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_sw_rst_ctrl_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"2.chip_sw_rstmgr_alert_info.60643192460179434533723579794459775711322466409955999150586332590010805969754","seed":60643192460179434533723579794459775711322466409955999150586332590010805969754,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest run_opts='+sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3851871066 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.3851871066' seed=60643192460179434533723579794459775711322466409955999150586332590010805969754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_alert_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60643192460179434533723579794459775711322466409955999150586332590010805969754 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_alert_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"2.chip_sw_rstmgr_cpu_info.45669495874162516352829340949970228077312721357164515501324357870249630260760","seed":45669495874162516352829340949970228077312721357164515501324357870249630260760,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest run_opts='+sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3717488152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3717488152' seed=45669495874162516352829340949970228077312721357164515501324357870249630260760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_cpu_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45669495874162516352829340949970228077312721357164515501324357870249630260760 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_cpu_info_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.102123213201885517160501226639422800857575228727326107189364315084530935390033","seed":102123213201885517160501226639422800857575228727326107189364315084530935390033,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4260355921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.4260355921' seed=102123213201885517160501226639422800857575228727326107189364315084530935390033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102123213201885517160501226639422800857575228727326107189364315084530935390033 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_full_aon_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_main_power_glitch_reset.110871869967542297824972156338293187306336567692360611203646609856323539587588","seed":110871869967542297824972156338293187306336567692360611203646609856323539587588,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3402781188 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3402781188' seed=110871869967542297824972156338293187306336567692360611203646609856323539587588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110871869967542297824972156338293187306336567692360611203646609856323539587588 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_main_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.34601007115402224610031229723729088569581121790471775805644490936384135063264","seed":34601007115402224610031229723729088569581121790471775805644490936384135063264,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=861890272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.861890272' seed=34601007115402224610031229723729088569581121790471775805644490936384135063264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34601007115402224610031229723729088569581121790471775805644490936384135063264 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_main_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.71566753914466832440960725909842033017246247353376385317534379585727647563378","seed":71566753914466832440960725909842033017246247353376385317534379585727647563378,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1106624114 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1106624114' seed=71566753914466832440960725909842033017246247353376385317534379585727647563378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71566753914466832440960725909842033017246247353376385317534379585727647563378 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_deep_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.54096558428964919579422510994214414773291699108316221794471245327912959014697","seed":54096558428964919579422510994214414773291699108316221794471245327912959014697,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3013932841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3013932841' seed=54096558428964919579422510994214414773291699108316221794471245327912959014697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54096558428964919579422510994214414773291699108316221794471245327912959014697 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_random_power_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"2.chip_sw_pwrmgr_sleep_disabled.42955867523165229886336523857608654084422780421306586727959587521814349702715","seed":42955867523165229886336523857608654084422780421306586727959587521814349702715,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest run_opts='+sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2484561467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2484561467' seed=42955867523165229886336523857608654084422780421306586727959587521814349702715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:pwrmgr_sleep_disabled_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42955867523165229886336523857608654084422780421306586727959587521814349702715 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:pwrmgr_sleep_disabled_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_timer_irq","qual_name":"2.chip_sw_rv_timer_irq.37308405565166670190481265461702005813488140438661633136579483881069058050934","seed":37308405565166670190481265461702005813488140438661633136579483881069058050934,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1072286582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_timer_irq.1072286582' seed=37308405565166670190481265461702005813488140438661633136579483881069058050934 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37308405565166670190481265461702005813488140438661633136579483881069058050934 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"2.chip_sw_soc_proxy_smoketest.82702393632545831656295798726936210724966918303582474185448866851588644157903","seed":82702393632545831656295798726936210724966918303582474185448866851588644157903,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1891514831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_soc_proxy_smoketest.1891514831' seed=82702393632545831656295798726936210724966918303582474185448866851588644157903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82702393632545831656295798726936210724966918303582474185448866851588644157903 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"2.chip_sw_soc_proxy_external_wakeup.72029894078599529058795675528090446678206405054921041172470393341264524301004","seed":72029894078599529058795675528090446678206405054921041172470393341264524301004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_external_wakeup:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710655692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_external_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_soc_proxy_external_wakeup.2710655692' seed=72029894078599529058795675528090446678206405054921041172470393341264524301004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_external_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72029894078599529058795675528090446678206405054921041172470393341264524301004 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_external_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_external_wakeup_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_soc_proxy_gpios","qual_name":"2.chip_sw_soc_proxy_gpios.57841976877559831620315292262554956718784428572885065888812002814732690481909","seed":57841976877559831620315292262554956718784428572885065888812002814732690481909,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_gpios/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_gpios/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_gpios/latest run_opts='+sw_build_device=sim_dv +sw_images=soc_proxy_gpios:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=458711797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_soc_proxy_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_soc_proxy_gpios.458711797' seed=57841976877559831620315292262554956718784428572885065888812002814732690481909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:soc_proxy_gpios:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57841976877559831620315292262554956718784428572885065888812002814732690481909 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_gpios/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:soc_proxy_gpios:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_soc_proxy_gpio_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"2.chip_sw_aon_timer_irq.25582385236399842192024199785858644585392529279256197140933536099082065829916","seed":25582385236399842192024199785858644585392529279256197140933536099082065829916,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404095516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3404095516' seed=25582385236399842192024199785858644585392529279256197140933536099082065829916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25582385236399842192024199785858644585392529279256197140933536099082065829916 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_sleep_wdog_sleep_pause","qual_name":"2.chip_sw_aon_timer_sleep_wdog_sleep_pause.35140447624418693956325105379510920626169310179875472442185589047311105876070","seed":35140447624418693956325105379510920626169310179875472442185589047311105876070,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2111922278 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2111922278' seed=35140447624418693956325105379510920626169310179875472442185589047311105876070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35140447624418693956325105379510920626169310179875472442185589047311105876070 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.39850893322621165655646522048914240574820981212990344035570013528956319645718","seed":39850893322621165655646522048914240574820981212990344035570013528956319645718,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest run_opts='+sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1210400790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1210400790' seed=39850893322621165655646522048914240574820981212990344035570013528956319645718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_wdog_bite_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39850893322621165655646522048914240574820981212990344035570013528956319645718 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_wdog_bite_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"2.chip_sw_pwrmgr_wdog_reset.1349628027314649877663213953151370213248400586402462802738821741548866799827","seed":1349628027314649877663213953151370213248400586402462802738821741548866799827,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=451578067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.451578067' seed=1349628027314649877663213953151370213248400586402462802738821741548866799827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:pwrmgr_wdog_reset_reqs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1349628027314649877663213953151370213248400586402462802738821741548866799827 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:pwrmgr_wdog_reset_reqs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_wdog_lc_escalate","qual_name":"2.chip_sw_aon_timer_wdog_lc_escalate.53580639862570912284674084614714415758459844451615829085049056505881445482679","seed":53580639862570912284674084614714415758459844451615829085049056505881445482679,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=696991927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.696991927' seed=53580639862570912284674084614714415758459844451615829085049056505881445482679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_wdog_lc_escalate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53580639862570912284674084614714415758459844451615829085049056505881445482679 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_wdog_lc_escalate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_randomness","qual_name":"2.chip_sw_otbn_randomness.9953024606157330691413361126121219959705829225681240715921882975844697686923","seed":9953024606157330691413361126121219959705829225681240715921882975844697686923,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_randomness/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_randomness/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_randomness/latest run_opts='+sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2551759755 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2551759755' seed=9953024606157330691413361126121219959705829225681240715921882975844697686923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_randomness_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9953024606157330691413361126121219959705829225681240715921882975844697686923 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_randomness/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_randomness_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_mem_scramble","qual_name":"2.chip_sw_otbn_mem_scramble.35709212931916229834269511102984696430722444851776203351818129337182883062519","seed":35709212931916229834269511102984696430722444851776203351818129337182883062519,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest run_opts='+sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1340515063 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1340515063' seed=35709212931916229834269511102984696430722444851776203351818129337182883062519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_mem_scramble_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35709212931916229834269511102984696430722444851776203351818129337182883062519 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_mem_scramble_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"2.chip_sw_rv_core_ibex_rnd.14654559203517582754091275799137499779280603253737356051340131405066695491572","seed":14654559203517582754091275799137499779280603253737356051340131405066695491572,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest run_opts='+sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173479924 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.4173479924' seed=14654559203517582754091275799137499779280603253737356051340131405066695491572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_rnd_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14654559203517582754091275799137499779280603253737356051340131405066695491572 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_rnd_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"2.chip_sw_rv_core_ibex_nmi_irq.105621771615973323094229964372589252731546031230535565965096743343856328101554","seed":105621771615973323094229964372589252731546031230535565965096743343856328101554,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest run_opts='+sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=705154738 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.705154738' seed=105621771615973323094229964372589252731546031230535565965096743343856328101554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_nmi_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105621771615973323094229964372589252731546031230535565965096743343856328101554 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_nmi_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc","qual_name":"2.chip_sw_aes_enc.54389663946978197413382839986989821712087625027169479010529109464370620186439","seed":54389663946978197413382839986989821712087625027169479010529109464370620186439,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc/latest run_opts='+sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2638528327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2638528327' seed=54389663946978197413382839986989821712087625027169479010529109464370620186439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54389663946978197413382839986989821712087625027169479010529109464370620186439 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"2.chip_sw_aes_enc_jitter_en.12705479705622528824819037100615491986267508273771481114899707963526039084710","seed":12705479705622528824819037100615491986267508273771481114899707963526039084710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest run_opts='+sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3823771302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3823771302' seed=12705479705622528824819037100615491986267508273771481114899707963526039084710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12705479705622528824819037100615491986267508273771481114899707963526039084710 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_gcm","qual_name":"2.chip_sw_aes_gcm.91121031789871872501608471772663759665053832156552282282438316020248382643146","seed":91121031789871872501608471772663759665053832156552282282438316020248382643146,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_gcm/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_gcm/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_gcm/latest run_opts='+sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_gcm_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=302357450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_gcm.302357450' seed=91121031789871872501608471772663759665053832156552282282438316020248382643146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_gcm_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91121031789871872501608471772663759665053832156552282282438316020248382643146 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_gcm/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_gcm_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_idle","qual_name":"2.chip_sw_aes_idle.31775972948694249945865998107329620472999921577297168650826256888333781372223","seed":31775972948694249945865998107329620472999921577297168650826256888333781372223,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_idle/latest run_opts='+sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2229472575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2229472575' seed=31775972948694249945865998107329620472999921577297168650826256888333781372223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31775972948694249945865998107329620472999921577297168650826256888333781372223 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_masking_off","qual_name":"2.chip_sw_aes_masking_off.89171464101546051020767867618456317825724842232699916937706840696548943448218","seed":89171464101546051020767867618456317825724842232699916937706840696548943448218,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_masking_off/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_masking_off/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_masking_off/latest run_opts='+sw_build_device=sim_dv +sw_images=aes_masking_off_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702428314 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2702428314' seed=89171464101546051020767867618456317825724842232699916937706840696548943448218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_masking_off_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89171464101546051020767867618456317825724842232699916937706840696548943448218 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_masking_off/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_masking_off_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_aes_masking_off_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.93148613415682810758269363814088963433072367464121340667251176375699044929482","seed":93148613415682810758269363814088963433072367464121340667251176375699044929482,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_test/latest run_opts='+sw_build_device=sim_dv +sw_images=alert_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=780242890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_test.780242890' seed=93148613415682810758269363814088963433072367464121340667251176375699044929482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/autogen/top_darjeeling:alert_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93148613415682810758269363814088963433072367464121340667251176375699044929482 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/autogen/top_darjeeling:alert_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"2.chip_sw_alert_handler_escalation.47840171520566907647323175484677932381818392256564190869826474744901352069654","seed":47840171520566907647323175484677932381818392256564190869826474744901352069654,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1607244310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1607244310' seed=47840171520566907647323175484677932381818392256564190869826474744901352069654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47840171520566907647323175484677932381818392256564190869826474744901352069654 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_alert_handler_escalation_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_ping_timeout","qual_name":"2.chip_sw_alert_handler_ping_timeout.39152189835889936641060609588211561323120949406448031922218405555331206023617","seed":39152189835889936641060609588211561323120949406448031922218405555331206023617,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest run_opts='+en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=599067073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.599067073' seed=39152189835889936641060609588211561323120949406448031922218405555331206023617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_ping_timeout_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39152189835889936641060609588211561323120949406448031922218405555331206023617 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_ping_timeout_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.83776952342358846433309086299180498561619782975383430057086002557268665313681","seed":83776952342358846433309086299180498561619782975383430057086002557268665313681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.196s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.80063065279822836653867645598046316346384520471367450973520209091455834918345","seed":80063065279822836653867645598046316346384520471367450973520209091455834918345,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.22184992946040633794435593788221891136166840530541844065003246868753558958661","seed":22184992946040633794435593788221891136166840530541844065003246868753558958661,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.191s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"2.chip_sw_alert_handler_lpg_clkoff.58704062841099594712829057283048310325511806762560345648887802163095839739424","seed":58704062841099594712829057283048310325511806762560345648887802163095839739424,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.173s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"2.chip_sw_alert_handler_lpg_reset_toggle.3835123038356267777884556140795792555934874863967127154233649204341168826171","seed":3835123038356267777884556140795792555934874863967127154233649204341168826171,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.177s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"2.chip_sw_alert_handler_entropy.56196429393961489659957774897567485095067671248990504441363526940429534226294","seed":56196429393961489659957774897567485095067671248990504441363526940429534226294,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1687807862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1687807862' seed=56196429393961489659957774897567485095067671248990504441363526940429534226294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:alert_handler_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56196429393961489659957774897567485095067671248990504441363526940429534226294 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:alert_handler_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_alert_handler_entropy_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_entropy","qual_name":"2.chip_sw_aes_entropy.59836234939631603259716498778038121602460998663659194931367296996641583059640","seed":59836234939631603259716498778038121602460998663659194931367296996641583059640,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_entropy/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_entropy/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_entropy/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410416312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3410416312' seed=59836234939631603259716498778038121602460998663659194931367296996641583059640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59836234939631603259716498778038121602460998663659194931367296996641583059640 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_entropy/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_entropy_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_kat_test","qual_name":"2.chip_sw_csrng_kat_test.105362908160406757096970526490465312097800640513215127190785932679455124026646","seed":105362908160406757096970526490465312097800640513215127190785932679455124026646,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1465709846 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1465709846' seed=105362908160406757096970526490465312097800640513215127190785932679455124026646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:csrng_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105362908160406757096970526490465312097800640513215127190785932679455124026646 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:csrng_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.43501262203245323831480386555734174595997012835057555863091902232141900822835","seed":43501262203245323831480386555734174595997012835057555863091902232141900822835,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3285989683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3285989683' seed=43501262203245323831480386555734174595997012835057555863091902232141900822835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43501262203245323831480386555734174595997012835057555863091902232141900822835 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_csrng","qual_name":"2.chip_sw_entropy_src_csrng.45818656268694881585005654074715947029745114911234538301675585712473901206794","seed":45818656268694881585005654074715947029745114911234538301675585712473901206794,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest run_opts='+sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486275338 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2486275338' seed=45818656268694881585005654074715947029745114911234538301675585712473901206794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_csrng_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45818656268694881585005654074715947029745114911234538301675585712473901206794 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_csrng_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_kat_test","qual_name":"2.chip_sw_entropy_src_kat_test.5664315915973849555922255874159645522661040267433073553264996763602481847769","seed":5664315915973849555922255874159645522661040267433073553264996763602481847769,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3132628441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3132628441' seed=5664315915973849555922255874159645522661040267433073553264996763602481847769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5664315915973849555922255874159645522661040267433073553264996763602481847769 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_kat_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_ast_rng_req","qual_name":"2.chip_sw_entropy_src_ast_rng_req.16455672950628620585779793036249217680504467213957026764283267002895207782067","seed":16455672950628620585779793036249217680504467213957026764283267002895207782067,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest run_opts='+sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1172854451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1172854451' seed=16455672950628620585779793036249217680504467213957026764283267002895207782067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_ast_rng_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16455672950628620585779793036249217680504467213957026764283267002895207782067 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_ast_rng_req_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc","qual_name":"2.chip_sw_hmac_enc.430477401414990579578291711950777619684286717138198478488609389653224288142","seed":430477401414990579578291711950777619684286717138198478488609389653224288142,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3449515918 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3449515918' seed=430477401414990579578291711950777619684286717138198478488609389653224288142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=430477401414990579578291711950777619684286717138198478488609389653224288142 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"2.chip_sw_hmac_enc_jitter_en.426635815350553202278015269552787768455958260381626598286923067880564986165","seed":426635815350553202278015269552787768455958260381626598286923067880564986165,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest run_opts='+en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3390968117 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3390968117' seed=426635815350553202278015269552787768455958260381626598286923067880564986165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=426635815350553202278015269552787768455958260381626598286923067880564986165 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_idle","qual_name":"2.chip_sw_hmac_enc_idle.44634461660200784739750070308543910992164216698795108733273269694552707857152","seed":44634461660200784739750070308543910992164216698795108733273269694552707857152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=566655744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_idle.566655744' seed=44634461660200784739750070308543910992164216698795108733273269694552707857152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44634461660200784739750070308543910992164216698795108733273269694552707857152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_cshake","qual_name":"2.chip_sw_kmac_mode_cshake.4122479264551066119440541262134883557781125717478704272660851874375114962363","seed":4122479264551066119440541262134883557781125717478704272660851874375114962363,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506555323 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1506555323' seed=4122479264551066119440541262134883557781125717478704272660851874375114962363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_cshake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4122479264551066119440541262134883557781125717478704272660851874375114962363 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_cshake_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac","qual_name":"2.chip_sw_kmac_mode_kmac.82780239871862732890054254613321828002545161739466884872475119888088038268238","seed":82780239871862732890054254613321828002545161739466884872475119888088038268238,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2682150222 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac.2682150222' seed=82780239871862732890054254613321828002545161739466884872475119888088038268238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82780239871862732890054254613321828002545161739466884872475119888088038268238 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"2.chip_sw_kmac_mode_kmac_jitter_en.54349739612592832241108981642859043252341233063086869177794868399225262818216","seed":54349739612592832241108981642859043252341233063086869177794868399225262818216,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest run_opts='+en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737895848 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3737895848' seed=54349739612592832241108981642859043252341233063086869177794868399225262818216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54349739612592832241108981642859043252341233063086869177794868399225262818216 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"2.chip_sw_kmac_app_rom.83856420754237097086428133510402283017791657571826232233968472321493807506058","seed":83856420754237097086428133510402283017791657571826232233968472321493807506058,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_app_rom_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871211658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_app_rom.871211658' seed=83856420754237097086428133510402283017791657571826232233968472321493807506058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_app_rom_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83856420754237097086428133510402283017791657571826232233968472321493807506058 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_app_rom_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_idle","qual_name":"2.chip_sw_kmac_idle.41302580126156445717943088398715307307803283917848919539924402964390903223768","seed":41302580126156445717943088398715307307803283917848919539924402964390903223768,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_idle/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_idle/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_idle/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_idle_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=532354520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_idle.532354520' seed=41302580126156445717943088398715307307803283917848919539924402964390903223768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=41302580126156445717943088398715307307803283917848919539924402964390903223768 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_idle/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_idle_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"2.chip_sw_rom_ctrl_integrity_check.32530134579246155381980577741831335843449722363451857834725614442402506558980","seed":32530134579246155381980577741831335843449722363451857834725614442402506558980,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest run_opts='+sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570093572 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3570093572' seed=32530134579246155381980577741831335843449722363451857834725614442402506558980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32530134579246155381980577741831335843449722363451857834725614442402506558980 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_ctrl_integrity_check_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access","qual_name":"2.chip_sw_sram_ctrl_scrambled_access.73957172791742275246508055372745976008453560056028241873706603723246967345451","seed":73957172791742275246508055372745976008453560056028241873706603723246967345451,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest run_opts='+sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035596587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access.4035596587' seed=73957172791742275246508055372745976008453560056028241873706603723246967345451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73957172791742275246508055372745976008453560056028241873706603723246967345451 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"2.chip_sw_sram_ctrl_scrambled_access_jitter_en.34447814624867845364148575090825359100580533953960772321291860037771103943946","seed":34447814624867845364148575090825359100580533953960772321291860037771103943946,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest run_opts='+sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22920458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.22920458' seed=34447814624867845364148575090825359100580533953960772321291860037771103943946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34447814624867845364148575090825359100580533953960772321291860037771103943946 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"2.chip_sw_sram_ctrl_execution_main.58827018025709873125494098871599244362310169378749264845457477851940774458538","seed":58827018025709873125494098871599244362310169378749264845457477851940774458538,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest run_opts='+sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3904615594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3904615594' seed=58827018025709873125494098871599244362310169378749264845457477851940774458538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58827018025709873125494098871599244362310169378749264845457477851940774458538 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_execution_main_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.84427505489467647372011581737552038585879518840318790887325694612973506154833","seed":84427505489467647372011581737552038585879518840318790887325694612973506154833,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2592756049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2592756049' seed=84427505489467647372011581737552038585879518840318790887325694612973506154833 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84427505489467647372011581737552038585879518840318790887325694612973506154833 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_prim_tl_access","qual_name":"2.chip_prim_tl_access.59704098917825338331975202900245319568431518482575305522499182060057101966052","seed":59704098917825338331975202900245319568431518482575305522499182060057101966052,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_prim_tl_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_prim_tl_access/latest run_opts='+en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3934624484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3934624484' seed=59704098917825338331975202900245319568431518482575305522499182060057101966052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59704098917825338331975202900245319568431518482575305522499182060057101966052 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_prim_tl_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_prim_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_plic_all_irqs_0","qual_name":"2.chip_plic_all_irqs_0.50846734818461843448766562470203206959831105792956303809467640520138769859011","seed":50846734818461843448766562470203206959831105792956303809467640520138769859011,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_0/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_0/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_0/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15237571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_plic_all_irqs_0.15237571' seed=50846734818461843448766562470203206959831105792956303809467640520138769859011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_0:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50846734818461843448766562470203206959831105792956303809467640520138769859011 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_0/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_0:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_plic_all_irqs_10","qual_name":"2.chip_plic_all_irqs_10.23999293184756492989573007802601591034887837412670368849964152935920602866358","seed":23999293184756492989573007802601591034887837412670368849964152935920602866358,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_10/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_10/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_10/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=438198966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_plic_all_irqs_10.438198966' seed=23999293184756492989573007802601591034887837412670368849964152935920602866358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_10:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23999293184756492989573007802601591034887837412670368849964152935920602866358 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_plic_all_irqs_10/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//hw/top_darjeeling/sw/autogen/tests:plic_all_irqs_test_10:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_plic_sw_irq","qual_name":"2.chip_sw_plic_sw_irq.86923022857618256457354102310557014952674958637117080654623970916519227703622","seed":86923022857618256457354102310557014952674958637117080654623970916519227703622,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest run_opts='+sw_build_device=sim_dv +sw_images=plic_sw_irq_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3426500934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_plic_sw_irq.3426500934' seed=86923022857618256457354102310557014952674958637117080654623970916519227703622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:plic_sw_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86923022857618256457354102310557014952674958637117080654623970916519227703622 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:plic_sw_irq_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"2.chip_sw_clkmgr_off_aes_trans.81326631379189328648644094793089124299754916799350919453986300565776788578133","seed":81326631379189328648644094793089124299754916799350919453986300565776788578133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3563544405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3563544405' seed=81326631379189328648644094793089124299754916799350919453986300565776788578133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_aes_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81326631379189328648644094793089124299754916799350919453986300565776788578133 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_aes_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"2.chip_sw_clkmgr_off_hmac_trans.39102277901833633227411488593095895941119601298051255400448761502853332805883","seed":39102277901833633227411488593095895941119601298051255400448761502853332805883,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1549347067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.1549347067' seed=39102277901833633227411488593095895941119601298051255400448761502853332805883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_hmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39102277901833633227411488593095895941119601298051255400448761502853332805883 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_hmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"2.chip_sw_clkmgr_off_kmac_trans.100546233188458927930121041250422288457425645420298597550460683203250447856389","seed":100546233188458927930121041250422288457425645420298597550460683203250447856389,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=616968965 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.616968965' seed=100546233188458927930121041250422288457425645420298597550460683203250447856389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_kmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100546233188458927930121041250422288457425645420298597550460683203250447856389 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_kmac_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"2.chip_sw_clkmgr_off_otbn_trans.11340402076223901874057122498711232876550000188841167330148292506425012813443","seed":11340402076223901874057122498711232876550000188841167330148292506425012813443,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611876483 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.611876483' seed=11340402076223901874057122498711232876550000188841167330148292506425012813443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11340402076223901874057122498711232876550000188841167330148292506425012813443 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"2.chip_sw_clkmgr_reset_frequency.28568123878552187641310083803526973275340405248423885027642711017447875704396","seed":28568123878552187641310083803526973275340405248423885027642711017447875704396,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=979662412 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.979662412' seed=28568123878552187641310083803526973275340405248423885027642711017447875704396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:clkmgr_reset_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28568123878552187641310083803526973275340405248423885027642711017447875704396 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:clkmgr_reset_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_jitter","qual_name":"2.chip_sw_clkmgr_jitter.106438101000482866835282015295640517338923022103926127077134407407764524689490","seed":106438101000482866835282015295640517338923022103926127077134407407764524689490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1857218642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter.1857218642' seed=106438101000482866835282015295640517338923022103926127077134407407764524689490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106438101000482866835282015295640517338923022103926127077134407407764524689490 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"2.chip_sw_clkmgr_sleep_frequency.103232723677383876294504419901742993797192097237720509215061951447228219813730","seed":103232723677383876294504419901742993797192097237720509215061951447228219813730,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1153855330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1153855330' seed=103232723677383876294504419901742993797192097237720509215061951447228219813730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:clkmgr_sleep_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103232723677383876294504419901742993797192097237720509215061951447228219813730 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:clkmgr_sleep_frequency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_jtag_csr_rw","qual_name":"2.chip_jtag_csr_rw.15091216635879762057845994586442167234203709312321565430357171899637232472238","seed":15091216635879762057845994586442167234203709312321565430357171899637232472238,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_csr_rw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_csr_rw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_csr_rw/latest run_opts='+en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3396767918 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.3396767918' seed=15091216635879762057845994586442167234203709312321565430357171899637232472238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15091216635879762057845994586442167234203709312321565430357171899637232472238 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_csr_rw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_jtag_csr_rw_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_jtag_mem_access","qual_name":"2.chip_jtag_mem_access.11990406624789193181016290976575783512236950169456844536352383932473570841706","seed":11990406624789193181016290976575783512236950169456844536352383932473570841706,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest run_opts='+create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2238534762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2238534762' seed=11990406624789193181016290976575783512236950169456844536352383932473570841706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11990406624789193181016290976575783512236950169456844536352383932473570841706 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_jtag_mem_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"2.chip_sw_ast_clk_outputs.59689148605073628959923776674975918811742396320006893073018662205197021980664","seed":59689148605073628959923776674975918811742396320006893073018662205197021980664,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest run_opts='+sw_build_device=sim_dv +sw_images=ast_clk_outs_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391910392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2391910392' seed=59689148605073628959923776674975918811742396320006893073018662205197021980664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:ast_clk_outs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59689148605073628959923776674975918811742396320006893073018662205197021980664 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:ast_clk_outs_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"2.chip_sw_lc_ctrl_program_error.34551683965644998373470724121263065641821112048449575567094615302221481947098","seed":34551683965644998373470724121263065641821112048449575567094615302221481947098,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest run_opts='+en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1460187098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1460187098' seed=34551683965644998373470724121263065641821112048449575567094615302221481947098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests/sim_dv:lc_ctrl_program_error:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34551683965644998373470724121263065641821112048449575567094615302221481947098 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests/sim_dv:lc_ctrl_program_error:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_program_error_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_rv_dm_ndm_reset_req","qual_name":"2.chip_rv_dm_ndm_reset_req.93384112077573337864694626853448490877480692220094555531682930492931289617012","seed":93384112077573337864694626853448490877480692220094555531682930492931289617012,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest run_opts='+en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_dev:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=214930036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.214930036' seed=93384112077573337864694626853448490877480692220094555531682930492931289617012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_ndm_reset_req_dev:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93384112077573337864694626853448490877480692220094555531682930492931289617012 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_ndm_reset_req_dev:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_rv_dm_ndm_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.70948894249037895489705799144831380080363334068213587827443528341662252781283","seed":70948894249037895489705799144831380080363334068213587827443528341662252781283,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1451871971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1451871971' seed=70948894249037895489705799144831380080363334068213587827443528341662252781283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70948894249037895489705799144831380080363334068213587827443528341662252781283 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.23715823105713471995901236961294218968244390783486428126367672311872100352452","seed":23715823105713471995901236961294218968244390783486428126367672311872100352452,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3522019780 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3522019780' seed=23715823105713471995901236961294218968244390783486428126367672311872100352452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_dm_access_after_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23715823105713471995901236961294218968244390783486428126367672311872100352452 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_dm_access_after_wakeup:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_access_after_wakeup_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"2.chip_sw_rv_dm_access_after_escalation_reset.26459150937746706290448020206775666623812624142312641946158116116077141586144","seed":26459150937746706290448020206775666623812624142312641946158116116077141586144,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest run_opts='+use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454665952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1454665952' seed=26459150937746706290448020206775666623812624142312641946158116116077141586144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26459150937746706290448020206775666623812624142312641946158116116077141586144 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:alert_handler_escalation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_dm_access_after_escalation_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.24385696209234546154472777623499116593168509724953020558594638305485399848396","seed":24385696209234546154472777623499116593168509724953020558594638305485399848396,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest run_opts='+en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3862492620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3862492620' seed=24385696209234546154472777623499116593168509724953020558594638305485399848396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24385696209234546154472777623499116593168509724953020558594638305485399848396 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_rv_dm_lc_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_address_translation","qual_name":"2.chip_sw_rv_core_ibex_address_translation.107598672089465974328787204523843995512097957859475976758057020744100383748743","seed":107598672089465974328787204523843995512097957859475976758057020744100383748743,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest run_opts='+sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113415303 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3113415303' seed=107598672089465974328787204523843995512097957859475976758057020744100383748743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:rv_core_ibex_address_translation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107598672089465974328787204523843995512097957859475976758057020744100383748743 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:rv_core_ibex_address_translation_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"2.chip_sw_rv_core_ibex_lockstep_glitch.106776414198685537683981626504174526491789787984345104440354449741078544137319","seed":106776414198685537683981626504174526491789787984345104440354449741078544137319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest run_opts='+disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4140711015 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.4140711015' seed=106776414198685537683981626504174526491789787984345104440354449741078544137319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106776414198685537683981626504174526491789787984345104440354449741078544137319 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_core_ibex_lockstep_glitch_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_core_ibex_icache_invalidate","qual_name":"2.chip_sw_rv_core_ibex_icache_invalidate.58342690019135342225201282909181128918782097767360367480974618590122898163167","seed":58342690019135342225201282909181128918782097767360367480974618590122898163167,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2455832031 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2455832031' seed=58342690019135342225201282909181128918782097767360367480974618590122898163167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_core_ibex_icache_invalidate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58342690019135342225201282909181128918782097767360367480974618590122898163167 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_core_ibex_icache_invalidate_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rv_core_ibex_icache_invalidate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"2.chip_padctrl_attributes.80846790613451003052958590464266996281730845691385117980156377614182366853994","seed":80846790613451003052958590464266996281730845691385117980156377614182366853994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2626698090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_padctrl_attributes.2626698090' seed=80846790613451003052958590464266996281730845691385117980156377614182366853994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80846790613451003052958590464266996281730845691385117980156377614182366853994 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_jitter_reduced_freq","qual_name":"2.chip_sw_clkmgr_jitter_reduced_freq.105847663567560301686956865233332886047997892835675438582906812001479243257855","seed":105847663567560301686956865233332886047997892835675438582906812001479243257855,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest run_opts='+cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2232080383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2232080383' seed=105847663567560301686956865233332886047997892835675438582906812001479243257855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105847663567560301686956865233332886047997892835675438582906812001479243257855 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_jitter_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"2.chip_sw_aes_enc_jitter_en_reduced_freq.101405531401155337330176842088090824801563452899036830273357124299545041965824","seed":101405531401155337330176842088090824801563452899036830273357124299545041965824,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest run_opts='+sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225528064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1225528064' seed=101405531401155337330176842088090824801563452899036830273357124299545041965824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101405531401155337330176842088090824801563452899036830273357124299545041965824 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"2.chip_sw_hmac_enc_jitter_en_reduced_freq.14332005162744389895855413622763031694229138965571583580227687467517202682989","seed":14332005162744389895855413622763031694229138965571583580227687467517202682989,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest run_opts='+en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3030930541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3030930541' seed=14332005162744389895855413622763031694229138965571583580227687467517202682989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14332005162744389895855413622763031694229138965571583580227687467517202682989 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_enc_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.96156994040649122005745317119339942509435269559623384824773915423370550142746","seed":96156994040649122005745317119339942509435269559623384824773915423370550142746,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest run_opts='+en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1890543386 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1890543386' seed=96156994040649122005745317119339942509435269559623384824773915423370550142746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96156994040649122005745317119339942509435269559623384824773915423370550142746 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_mode_kmac_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.82085922204131589398462446690690074210442877450655233225585696605844538689387","seed":82085922204131589398462446690690074210442877450655233225585696605844538689387,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest run_opts='+mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4149512043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4149512043' seed=82085922204131589398462446690690074210442877450655233225585696605844538689387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82085922204131589398462446690690074210442877450655233225585696605844538689387 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_scrambled_access_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_sram_ctrl_scrambled_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_power_virus","qual_name":"2.chip_sw_power_virus.20133104598230027782244353424291837255583301086056672354936817816242688253473","seed":20133104598230027782244353424291837255583301086056672354936817816242688253473,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.788s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_dma_inline_hashing","qual_name":"2.chip_sw_dma_inline_hashing.72332489974604115794573911971351348951725550060834419543994970377493870984971","seed":72332489974604115794573911971351348951725550060834419543994970377493870984971,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_inline_hashing/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_inline_hashing/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_inline_hashing/latest run_opts='+sw_test_timeout_ns=22_000_000 +abort=0 +sw_build_device=sim_dv +sw_images=dma_inline_hashing:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4141793035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_dma_spi_hw_handshake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_dma_inline_hashing.4141793035' seed=72332489974604115794573911971351348951725550060834419543994970377493870984971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:dma_inline_hashing:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72332489974604115794573911971351348951725550060834419543994970377493870984971 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_inline_hashing/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:dma_inline_hashing:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_dma_spi_hw_handshake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_dma_abort","qual_name":"2.chip_sw_dma_abort.52495854235085212595745612227405923792150667865550584996876540311101112042165","seed":52495854235085212595745612227405923792150667865550584996876540311101112042165,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest run_opts='+sw_test_timeout_ns=22_000_000 +abort=1 +sw_build_device=sim_dv +sw_images=dma_abort:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521205941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_dma_spi_hw_handshake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_dma_abort.1521205941' seed=52495854235085212595745612227405923792150667865550584996876540311101112042165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:dma_abort:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52495854235085212595745612227405923792150667865550584996876540311101112042165 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:dma_abort:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_dma_spi_hw_handshake_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"base_rom_e2e_smoke","qual_name":"2.base_rom_e2e_smoke.10833558124020287587183181621467326561862006910668130526813947612655219881662","seed":10833558124020287587183181621467326561862006910668130526813947612655219881662,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.base_rom_e2e_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.base_rom_e2e_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.base_rom_e2e_smoke/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=base_rom_e2e_smoke:7:test_in_second_rom,base_rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442480318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.base_rom_e2e_smoke.442480318' seed=10833558124020287587183181621467326561862006910668130526813947612655219881662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom //sw/device/silicon_creator/rom:base_rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10833558124020287587183181621467326561862006910668130526813947612655219881662 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.base_rom_e2e_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom //sw/device/silicon_creator/rom:base_rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_smoke","qual_name":"2.rom_e2e_smoke.71427169340736772696634985526418662728690234859458709723880063099229374272192","seed":71427169340736772696634985526418662728690234859458709723880063099229374272192,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_smoke/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=185881280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.185881280' seed=71427169340736772696634985526418662728690234859458709723880063099229374272192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71427169340736772696634985526418662728690234859458709723880063099229374272192 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"2.rom_e2e_shutdown_exception_c.86186865172280943059424367128624597413967412803940111427348413091303273768503","seed":86186865172280943059424367128624597413967412803940111427348413091303273768503,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1463789111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.1463789111' seed=86186865172280943059424367128624597413967412803940111427348413091303273768503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86186865172280943059424367128624597413967412803940111427348413091303273768503 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_shutdown_exception_c_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"2.rom_e2e_shutdown_output.25836113214008676598370218430368302496863719657967261355901336002473430840927","seed":25836113214008676598370218430368302496863719657967261355901336002473430840927,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_output/latest run_opts='+sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:6:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3226695263 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3226695263' seed=25836113214008676598370218430368302496863719657967261355901336002473430840927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_shutdown_output_test_unlocked0:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25836113214008676598370218430368302496863719657967261355901336002473430840927 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_output/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:6:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_shutdown_output_test_unlocked0:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rom_e2e_shutdown_output_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.30910734668146730755634191226477942523205852091862073207429841219120480036568","seed":30910734668146730755634191226477942523205852091862073207429841219120480036568,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=248551) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.91084862838277770806299313993774484026919353983634882318487202355145807101923","seed":91084862838277770806299313993774484026919353983634882318487202355145807101923,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=393014) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.52835319265170285605584142157477726351292751375863071874927061452649223194534","seed":52835319265170285605584142157477726351292751375863071874927061452649223194534,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.86000937282908112743006979788038335203698471069282716361699015910393365084946","seed":86000937282908112743006979788038335203698471069282716361699015910393365084946,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.101847647952173796333030240277624240710846242104525617495696352159586534514490","seed":101847647952173796333030240277624240710846242104525617495696352159586534514490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"2.rom_e2e_static_critical.58029874652460581229994595826805349029492537662719177002080464951570946977759","seed":58029874652460581229994595826805349029492537662719177002080464951570946977759,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_static_critical/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_static_critical/latest run_opts='+sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:6:signed:fake_rsa_test_key_0,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4253937631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.4253937631' seed=58029874652460581229994595826805349029492537662719177002080464951570946977759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58029874652460581229994595826805349029492537662719177002080464951570946977759 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_static_critical/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:6:signed:fake_rsa_test_key_0 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_meas","qual_name":"2.rom_e2e_keymgr_dpe_init_rom_ext_meas.14459693069184238950869626228597216844477070375251515743206895532563336818546","seed":14459693069184238950869626228597216844477070375251515743206895532563336818546,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=307523442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_dpe_init_rom_ext_meas.307523442' seed=14459693069184238950869626228597216844477070375251515743206895532563336818546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14459693069184238950869626228597216844477070375251515743206895532563336818546 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_no_meas","qual_name":"2.rom_e2e_keymgr_dpe_init_rom_ext_no_meas.60766896242389805585334220141137041623506807869236184791746712699871022349605","seed":60766896242389805585334220141137041623506807869236184791746712699871022349605,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_no_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898170149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_dpe_init_rom_ext_no_meas.898170149' seed=60766896242389805585334220141137041623506807869236184791746712699871022349605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_no_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60766896242389805585334220141137041623506807869236184791746712699871022349605 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_no_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_no_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas","qual_name":"2.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas.108154266317303067772813593142475467337794519576416644741642134837204741533915","seed":108154266317303067772813593142475467337794519576416644741642134837204741533915,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest run_opts='+sw_test_timeout_ns=55_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary,otp_img_keymgr_dpe_rom_ext_invalid_meas:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1560817883 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas.1560817883' seed=108154266317303067772813593142475467337794519576416644741642134837204741533915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_invalid_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108154266317303067772813593142475467337794519576416644741642134837204741533915 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test:6:signed:fake_rsa_test_key_0:ot_flash_binary //sw/device/silicon_creator/rom/e2e:otp_img_keymgr_dpe_rom_ext_invalid_meas:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.78138077172709838197658948521935893639273537859237853186363602813581726582598","seed":78138077172709838197658948521935893639273537859237853186363602813581726582598,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.39268149096133318645199347224361372168468732705836667550194463681353513837880","seed":39268149096133318645199347224361372168468732705836667550194463681353513837880,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_dev_otbn.60414984642923774195860433081760562178912045231216098145811063611222522511009","seed":60414984642923774195860433081760562178912045231216098145811063611222522511009,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_dev_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1721417377 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_dev_otbn.1721417377' seed=60414984642923774195860433081760562178912045231216098145811063611222522511009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60414984642923774195860433081760562178912045231216098145811063611222522511009 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_dev_sw.41611732193455788980472313280232190621110909687290409624932130594129324729025","seed":41611732193455788980472313280232190621110909687290409624932130594129324729025,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_dev_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121037505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_dev_sw.121037505' seed=41611732193455788980472313280232190621110909687290409624932130594129324729025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=41611732193455788980472313280232190621110909687290409624932130594129324729025 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_otbn.108787162916058499027905439118137707353865330258989645156074005561937168517854","seed":108787162916058499027905439118137707353865330258989645156074005561937168517854,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3801696990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_prod_otbn.3801696990' seed=108787162916058499027905439118137707353865330258989645156074005561937168517854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108787162916058499027905439118137707353865330258989645156074005561937168517854 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_sw.67070120369837349037775977556821634132714678121846738578397216108581327133865","seed":67070120369837349037775977556821634132714678121846738578397216108581327133865,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1681841321 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_prod_sw.1681841321' seed=67070120369837349037775977556821634132714678121846738578397216108581327133865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67070120369837349037775977556821634132714678121846738578397216108581327133865 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_end_otbn.37519912224616881647012428673704326855660746958189418718602859726560673108706","seed":37519912224616881647012428673704326855660746958189418718602859726560673108706,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_end_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=751538914 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_prod_end_otbn.751538914' seed=37519912224616881647012428673704326855660746958189418718602859726560673108706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37519912224616881647012428673704326855660746958189418718602859726560673108706 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_end_sw.108319344439285691717069918666877856331520677870132699784762573686384322027930","seed":108319344439285691717069918666877856331520677870132699784762573686384322027930,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_prod_end_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802538394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_prod_end_sw.3802538394' seed=108319344439285691717069918666877856331520677870132699784762573686384322027930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108319344439285691717069918666877856331520677870132699784762573686384322027930 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_rma_otbn.27479742148477307301823970173686338628077218629874365437969719843437191531804","seed":27479742148477307301823970173686338628077218629874365437969719843437191531804,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_otbn/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_otbn/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_rma_otbn:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1297517852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_rma_otbn.1297517852' seed=27479742148477307301823970173686338628077218629874365437969719843437191531804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27479742148477307301823970173686338628077218629874365437969719843437191531804 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_otbn/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_rma_sw.87601422330035240714721928510323223239312158982806248868343244902655869579810","seed":87601422330035240714721928510323223239312158982806248868343244902655869579810,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_sw/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_sw/latest run_opts='+sw_test_timeout_ns=20_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_sigverify_mod_exp_rma_sw:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86241826 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_sigverify_mod_exp_rma_sw.86241826' seed=87601422330035240714721928510323223239312158982806248868343244902655869579810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87601422330035240714721928510323223239312158982806248868343244902655869579810 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_sw/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0 //sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_sw:4 //sw/device/silicon_creator/rom:rom_with_fake_keys:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.41839563489317868072839199372595711909577623024335520046328122212483856419880","seed":41839563489317868072839199372595711909577623024335520046328122212483856419880,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.30019964824286532751310395844455343717936192597585537586217176582995463167303","seed":30019964824286532751310395844455343717936192597585537586217176582995463167303,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=249934) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.23995050490965947236178992833072852578150884927473419348256522418244891359844","seed":23995050490965947236178992833072852578150884927473419348256522418244891359844,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"2.chip_sw_uart_smoketest_signed.36861168683337222287875510858049561741432374014095532298826683384355104143451","seed":36861168683337222287875510858049561741432374014095532298826683384355104143451,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_dpe_functest","qual_name":"2.rom_keymgr_dpe_functest.47575669365023346263205970554711896716918284231231365728948966497135213630011","seed":47575669365023346263205970554711896716918284231231365728948966497135213630011,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_keymgr_dpe_functest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_keymgr_dpe_functest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_keymgr_dpe_functest/latest run_opts='+sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_dpe_functest:6,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2938589755 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_dpe_functest.2938589755' seed=47575669365023346263205970554711896716918284231231365728948966497135213630011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest:6 //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47575669365023346263205970554711896716918284231231365728948966497135213630011 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_keymgr_dpe_functest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest:6 //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aes_smoketest","qual_name":"2.chip_sw_aes_smoketest.73505061450294078549392229389044342017156302619901040013335117161738562592189","seed":73505061450294078549392229389044342017156302619901040013335117161738562592189,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=aes_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3393609149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3393609149' seed=73505061450294078549392229389044342017156302619901040013335117161738562592189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73505061450294078549392229389044342017156302619901040013335117161738562592189 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aes_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_smoketest","qual_name":"2.chip_sw_aon_timer_smoketest.66885294455804697473975141511863653818689061125879665470352569489750479358731","seed":66885294455804697473975141511863653818689061125879665470352569489750479358731,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=aon_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483150603 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_smoketest.483150603' seed=66885294455804697473975141511863653818689061125879665470352569489750479358731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66885294455804697473975141511863653818689061125879665470352569489750479358731 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_clkmgr_smoketest","qual_name":"2.chip_sw_clkmgr_smoketest.98401240142427334554791575111516150129865619323619823032511805729523778648238","seed":98401240142427334554791575111516150129865619323619823032511805729523778648238,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=clkmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850041518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_smoketest.3850041518' seed=98401240142427334554791575111516150129865619323619823032511805729523778648238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:clkmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98401240142427334554791575111516150129865619323619823032511805729523778648238 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:clkmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_csrng_smoketest","qual_name":"2.chip_sw_csrng_smoketest.28443785353946163464078076792387821361622995573111479711694685325516952966836","seed":28443785353946163464078076792387821361622995573111479711694685325516952966836,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=csrng_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1744180916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_smoketest.1744180916' seed=28443785353946163464078076792387821361622995573111479711694685325516952966836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:csrng_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28443785353946163464078076792387821361622995573111479711694685325516952966836 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:csrng_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_entropy_src_smoketest","qual_name":"2.chip_sw_entropy_src_smoketest.24102326960646861096357324546891340792708337234007153083143828388887005047417","seed":24102326960646861096357324546891340792708337234007153083143828388887005047417,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest run_opts='+rng_srate_value_min=3 +rng_srate_value_max=10 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2173512313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2173512313' seed=24102326960646861096357324546891340792708337234007153083143828388887005047417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:entropy_src_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24102326960646861096357324546891340792708337234007153083143828388887005047417 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:entropy_src_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_gpio_smoketest","qual_name":"2.chip_sw_gpio_smoketest.104135367365153406299275928077059820649759430399845875202731657958766966676146","seed":104135367365153406299275928077059820649759430399845875202731657958766966676146,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=gpio_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2914196146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio_smoketest.2914196146' seed=104135367365153406299275928077059820649759430399845875202731657958766966676146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:gpio_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104135367365153406299275928077059820649759430399845875202731657958766966676146 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:gpio_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_gpio_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_hmac_smoketest","qual_name":"2.chip_sw_hmac_smoketest.78200089429827124963216156276989525006323105329594068531522861151239515281688","seed":78200089429827124963216156276989525006323105329594068531522861151239515281688,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=hmac_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438942488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_smoketest.3438942488' seed=78200089429827124963216156276989525006323105329594068531522861151239515281688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:hmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78200089429827124963216156276989525006323105329594068531522861151239515281688 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:hmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_kmac_smoketest","qual_name":"2.chip_sw_kmac_smoketest.113290433628462231835611291179464108119340421682607539502162217051666341423425","seed":113290433628462231835611291179464108119340421682607539502162217051666341423425,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=kmac_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010297153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.1010297153' seed=113290433628462231835611291179464108119340421682607539502162217051666341423425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:kmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113290433628462231835611291179464108119340421682607539502162217051666341423425 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:kmac_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_mbx_smoketest","qual_name":"2.chip_sw_mbx_smoketest.78221004492488923343439713866311748353665211917196605368360486120249696018344","seed":78221004492488923343439713866311748353665211917196605368360486120249696018344,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_mbx_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_mbx_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_mbx_smoketest/latest run_opts='+use_mbx_if=1 +sw_build_device=sim_dv +sw_images=mbx_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1759600552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mbx_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_mbx_smoketest.1759600552' seed=78221004492488923343439713866311748353665211917196605368360486120249696018344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:mbx_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78221004492488923343439713866311748353665211917196605368360486120249696018344 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_mbx_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:mbx_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_mbx_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otbn_smoketest","qual_name":"2.chip_sw_otbn_smoketest.33120299785287762253106279328317699934011855767542107953451234780222236806965","seed":33120299785287762253106279328317699934011855767542107953451234780222236806965,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=otbn_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612519733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.612519733' seed=33120299785287762253106279328317699934011855767542107953451234780222236806965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otbn_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33120299785287762253106279328317699934011855767542107953451234780222236806965 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otbn_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_otp_ctrl_smoketest","qual_name":"2.chip_sw_otp_ctrl_smoketest.85385338962952566236174153342899783169062897685244086588498294743356211576502","seed":85385338962952566236174153342899783169062897685244086588498294743356211576502,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3303915190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_smoketest.3303915190' seed=85385338962952566236174153342899783169062897685244086588498294743356211576502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:otp_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85385338962952566236174153342899783169062897685244086588498294743356211576502 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:otp_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_plic_smoketest","qual_name":"2.chip_sw_rv_plic_smoketest.21148773925703939754832993722206241401052910639089334603647211239034880804788","seed":21148773925703939754832993722206241401052910639089334603647211239034880804788,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_plic_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1533036468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_plic_smoketest.1533036468' seed=21148773925703939754832993722206241401052910639089334603647211239034880804788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_plic_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21148773925703939754832993722206241401052910639089334603647211239034880804788 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_plic_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rv_timer_smoketest","qual_name":"2.chip_sw_rv_timer_smoketest.49507292954733001641982189148608543171280584089542676547505879858559939713044","seed":49507292954733001641982189148608543171280584089542676547505879858559939713044,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rv_timer_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307514900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_timer_smoketest.1307514900' seed=49507292954733001641982189148608543171280584089542676547505879858559939713044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49507292954733001641982189148608543171280584089542676547505879858559939713044 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rv_timer_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_rstmgr_smoketest","qual_name":"2.chip_sw_rstmgr_smoketest.49637793946437135173102040740169669484029411434798393511243422211075174234677","seed":49637793946437135173102040740169669484029411434798393511243422211075174234677,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=rstmgr_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2185951797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_smoketest.2185951797' seed=49637793946437135173102040740169669484029411434798393511243422211075174234677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49637793946437135173102040740169669484029411434798393511243422211075174234677 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:rstmgr_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_sram_ctrl_smoketest","qual_name":"2.chip_sw_sram_ctrl_smoketest.50360430898384148118637442143638541187763343455334779346944947384956813769886","seed":50360430898384148118637442143638541187763343455334779346944947384956813769886,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362716830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3362716830' seed=50360430898384148118637442143638541187763343455334779346944947384956813769886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:sram_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50360430898384148118637442143638541187763343455334779346944947384956813769886 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:sram_ctrl_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_smoketest","qual_name":"2.chip_sw_uart_smoketest.31214982965322740191519506396495292604237371408243174486709343379113343011971","seed":31214982965322740191519506396495292604237371408243174486709343379113343011971,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest/latest run_opts='+sw_build_device=sim_dv +sw_images=uart_smoketest:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3687664771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_smoketest.3687664771' seed=31214982965322740191519506396495292604237371408243174486709343379113343011971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31214982965322740191519506396495292604237371408243174486709343379113343011971 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_smoketest:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"2.xbar_smoke.42196792434622662483585748770047295500573546516996586345436556037788012339789","seed":42196792434622662483585748770047295500573546516996586345436556037788012339789,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511744077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1511744077' seed=42196792434622662483585748770047295500573546516996586345436556037788012339789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42196792434622662483585748770047295500573546516996586345436556037788012339789 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"2.xbar_smoke_zero_delays.4152831171226648962701217366809313910363133645297818257510090785156850084841","seed":4152831171226648962701217366809313910363133645297818257510090785156850084841,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388669929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1388669929' seed=4152831171226648962701217366809313910363133645297818257510090785156850084841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4152831171226648962701217366809313910363133645297818257510090785156850084841 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"2.xbar_smoke_large_delays.52977967550856558271963849365946104113738012653474147641048829851851697719056","seed":52977967550856558271963849365946104113738012653474147641048829851851697719056,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3640952592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3640952592' seed=52977967550856558271963849365946104113738012653474147641048829851851697719056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52977967550856558271963849365946104113738012653474147641048829851851697719056 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"2.xbar_smoke_slow_rsp.92348805315902909422688484261134196712909184776765773511955202799015626835701","seed":92348805315902909422688484261134196712909184776765773511955202799015626835701,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2544404213 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2544404213' seed=92348805315902909422688484261134196712909184776765773511955202799015626835701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92348805315902909422688484261134196712909184776765773511955202799015626835701 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"2.xbar_random.65969540927439690184920066915132753789480200972299547565918090720029236241999","seed":65969540927439690184920066915132753789480200972299547565918090720029236241999,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599841871 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1599841871' seed=65969540927439690184920066915132753789480200972299547565918090720029236241999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65969540927439690184920066915132753789480200972299547565918090720029236241999 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"2.xbar_random_zero_delays.78703815881753681595454383990275903819660271122411918927829357400135056663162","seed":78703815881753681595454383990275903819660271122411918927829357400135056663162,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4277052026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4277052026' seed=78703815881753681595454383990275903819660271122411918927829357400135056663162 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78703815881753681595454383990275903819660271122411918927829357400135056663162 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"2.xbar_random_large_delays.114893671900453204377373390669366217619372621442070906334261071977002242328074","seed":114893671900453204377373390669366217619372621442070906334261071977002242328074,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589640202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2589640202' seed=114893671900453204377373390669366217619372621442070906334261071977002242328074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114893671900453204377373390669366217619372621442070906334261071977002242328074 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"2.xbar_random_slow_rsp.86869288555969624935329307644314449931077024673610495744081533401936723005459","seed":86869288555969624935329307644314449931077024673610495744081533401936723005459,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2542096403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2542096403' seed=86869288555969624935329307644314449931077024673610495744081533401936723005459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86869288555969624935329307644314449931077024673610495744081533401936723005459 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"2.xbar_access_same_device.106245602915307646797920859014878022841993302251007218873913597926796398413555","seed":106245602915307646797920859014878022841993302251007218873913597926796398413555,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=977782515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.977782515' seed=106245602915307646797920859014878022841993302251007218873913597926796398413555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106245602915307646797920859014878022841993302251007218873913597926796398413555 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"2.xbar_access_same_device_slow_rsp.25404134411966306456854491173311168622808440127554411029370527525339477836173","seed":25404134411966306456854491173311168622808440127554411029370527525339477836173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3342860685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3342860685' seed=25404134411966306456854491173311168622808440127554411029370527525339477836173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25404134411966306456854491173311168622808440127554411029370527525339477836173 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"2.xbar_same_source.18641597101991867753603336693313996786754059503295740897701840148839801763877","seed":18641597101991867753603336693313996786754059503295740897701840148839801763877,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172701733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.172701733' seed=18641597101991867753603336693313996786754059503295740897701840148839801763877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18641597101991867753603336693313996786754059503295740897701840148839801763877 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"2.xbar_error_random.57385048609009783773544347164217758372633943003605778493162675814545906683454","seed":57385048609009783773544347164217758372633943003605778493162675814545906683454,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2956414526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2956414526' seed=57385048609009783773544347164217758372633943003605778493162675814545906683454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57385048609009783773544347164217758372633943003605778493162675814545906683454 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"2.xbar_unmapped_addr.10571712925839241867110494527406436076604069001842990936906097857924936926372","seed":10571712925839241867110494527406436076604069001842990936906097857924936926372,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4114252964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4114252964' seed=10571712925839241867110494527406436076604069001842990936906097857924936926372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10571712925839241867110494527406436076604069001842990936906097857924936926372 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"2.xbar_error_and_unmapped_addr.107155798416164275584673676907416180396651561048005657961787850969597685266966","seed":107155798416164275584673676907416180396651561048005657961787850969597685266966,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817625622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.817625622' seed=107155798416164275584673676907416180396651561048005657961787850969597685266966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107155798416164275584673676907416180396651561048005657961787850969597685266966 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"2.xbar_stress_all.81096520350907208719086429769861237204397988322592144878157399385495393817770","seed":81096520350907208719086429769861237204397988322592144878157399385495393817770,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3061339306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3061339306' seed=81096520350907208719086429769861237204397988322592144878157399385495393817770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81096520350907208719086429769861237204397988322592144878157399385495393817770 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"2.xbar_stress_all_with_rand_reset.70833072213444420567486557275360173133860818630445109917972388304928581982681","seed":70833072213444420567486557275360173133860818630445109917972388304928581982681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3430521305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3430521305' seed=70833072213444420567486557275360173133860818630445109917972388304928581982681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70833072213444420567486557275360173133860818630445109917972388304928581982681 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"2.xbar_stress_all_with_error.77825924473622953192762644223077860221303538229491070166545499384170197012563","seed":77825924473622953192762644223077860221303538229491070166545499384170197012563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3165638739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3165638739' seed=77825924473622953192762644223077860221303538229491070166545499384170197012563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77825924473622953192762644223077860221303538229491070166545499384170197012563 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"2.xbar_stress_all_with_reset_error.91570816516566309253791609182389244867260623264854834079023121327950047848004","seed":91570816516566309253791609182389244867260623264854834079023121327950047848004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3813254724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3813254724' seed=91570816516566309253791609182389244867260623264854834079023121327950047848004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91570816516566309253791609182389244867260623264854834079023121327950047848004 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"3.chip_sw_all_escalation_resets.80862590006916432475005529965319048734894463803155935868668377016145614705202","seed":80862590006916432475005529965319048734894463803155935868668377016145614705202,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093533234 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3093533234' seed=80862590006916432475005529965319048734894463803155935868668377016145614705202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80862590006916432475005529965319048734894463803155935868668377016145614705202 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"3.chip_sw_data_integrity_escalation.37821321325331528602186236555624943345123021430850893268850677962944305461671","seed":37821321325331528602186236555624943345123021430850893268850677962944305461671,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173101479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.4173101479' seed=37821321325331528602186236555624943345123021430850893268850677962944305461671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37821321325331528602186236555624943345123021430850893268850677962944305461671 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_data_integrity_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"3.chip_sw_uart_tx_rx.109433651348474522244785240315147656171665318711189901126279725805836717143285","seed":109433651348474522244785240315147656171665318711189901126279725805836717143285,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest run_opts='+uart_idx=0 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3475649781 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3475649781' seed=109433651348474522244785240315147656171665318711189901126279725805836717143285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109433651348474522244785240315147656171665318711189901126279725805836717143285 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"3.chip_sw_uart_rand_baudrate.18758288731540143532514467830848421594261041632392300326979679541228467609006","seed":18758288731540143532514467830848421594261041632392300326979679541228467609006,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741825966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.741825966' seed=18758288731540143532514467830848421594261041632392300326979679541228467609006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18758288731540143532514467830848421594261041632392300326979679541228467609006 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"3.chip_sw_uart_tx_rx_alt_clk_freq.40580348699534178093020741652631359260353712334710420296865112104391557834056","seed":40580348699534178093020741652631359260353712334710420296865112104391557834056,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest run_opts='+sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128223048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq.3128223048' seed=40580348699534178093020741652631359260353712334710420296865112104391557834056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40580348699534178093020741652631359260353712334710420296865112104391557834056 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"3.chip_sw_lc_ctrl_transition.98817361295333279338038205445287040632147492111002251987744974069737867847994","seed":98817361295333279338038205445287040632147492111002251987744974069737867847994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1083320634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1083320634' seed=98817361295333279338038205445287040632147492111002251987744974069737867847994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98817361295333279338038205445287040632147492111002251987744974069737867847994 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_sleep_wdog_sleep_pause","qual_name":"3.chip_sw_aon_timer_sleep_wdog_sleep_pause.24833443965257632912947607018372615992543448362165541554618431141494440861728","seed":24833443965257632912947607018372615992543448362165541554618431141494440861728,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401326624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3401326624' seed=24833443965257632912947607018372615992543448362165541554618431141494440861728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24833443965257632912947607018372615992543448362165541554618431141494440861728 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.109036711152947343290866116914135758098570407918499190654303063098510377346363","seed":109036711152947343290866116914135758098570407918499190654303063098510377346363,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.80066011695648979689224750669447351266543969484177075605623650084409762523093","seed":80066011695648979689224750669447351266543969484177075605623650084409762523093,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640717781 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2640717781' seed=80066011695648979689224750669447351266543969484177075605623650084409762523093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80066011695648979689224750669447351266543969484177075605623650084409762523093 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"3.chip_padctrl_attributes.47458040890550874904338060016881027172431799805580232468492718484572146060656","seed":47458040890550874904338060016881027172431799805580232468492718484572146060656,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691859312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_padctrl_attributes.3691859312' seed=47458040890550874904338060016881027172431799805580232468492718484572146060656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47458040890550874904338060016881027172431799805580232468492718484572146060656 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"3.xbar_smoke.89711945620779563030077040103984719353096154653421862719632276884679362703365","seed":89711945620779563030077040103984719353096154653421862719632276884679362703365,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2238279685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2238279685' seed=89711945620779563030077040103984719353096154653421862719632276884679362703365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89711945620779563030077040103984719353096154653421862719632276884679362703365 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"3.xbar_smoke_zero_delays.33894080007535406046607653281068850983018224307106296026728722364534489581432","seed":33894080007535406046607653281068850983018224307106296026728722364534489581432,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=490178424 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.490178424' seed=33894080007535406046607653281068850983018224307106296026728722364534489581432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33894080007535406046607653281068850983018224307106296026728722364534489581432 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"3.xbar_smoke_large_delays.61261199415161030099023824541909263409442042779542793809136000039865376882797","seed":61261199415161030099023824541909263409442042779542793809136000039865376882797,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4284530797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4284530797' seed=61261199415161030099023824541909263409442042779542793809136000039865376882797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61261199415161030099023824541909263409442042779542793809136000039865376882797 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"3.xbar_smoke_slow_rsp.10243954436778736248409679223536088563609442260403332311780346045745946160842","seed":10243954436778736248409679223536088563609442260403332311780346045745946160842,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1077407434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1077407434' seed=10243954436778736248409679223536088563609442260403332311780346045745946160842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10243954436778736248409679223536088563609442260403332311780346045745946160842 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"3.xbar_random.30687640772321310703851653814759703023351931562039061567064221006275546321830","seed":30687640772321310703851653814759703023351931562039061567064221006275546321830,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2238845862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2238845862' seed=30687640772321310703851653814759703023351931562039061567064221006275546321830 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30687640772321310703851653814759703023351931562039061567064221006275546321830 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"3.xbar_random_zero_delays.68081563321610881984294561362384917184256430201332077135060223224126611877359","seed":68081563321610881984294561362384917184256430201332077135060223224126611877359,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1120890351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1120890351' seed=68081563321610881984294561362384917184256430201332077135060223224126611877359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68081563321610881984294561362384917184256430201332077135060223224126611877359 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"3.xbar_random_large_delays.23231152424190455643462677393285625673623812751519565795943888090416198997869","seed":23231152424190455643462677393285625673623812751519565795943888090416198997869,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2603898733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2603898733' seed=23231152424190455643462677393285625673623812751519565795943888090416198997869 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23231152424190455643462677393285625673623812751519565795943888090416198997869 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"3.xbar_random_slow_rsp.55316963844829970963014525059020994923851956306196125421266676997397476570996","seed":55316963844829970963014525059020994923851956306196125421266676997397476570996,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2524739444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2524739444' seed=55316963844829970963014525059020994923851956306196125421266676997397476570996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55316963844829970963014525059020994923851956306196125421266676997397476570996 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"3.xbar_access_same_device.98765956374605095399321758910372978906558751586507757372601113806919281835982","seed":98765956374605095399321758910372978906558751586507757372601113806919281835982,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423240142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3423240142' seed=98765956374605095399321758910372978906558751586507757372601113806919281835982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98765956374605095399321758910372978906558751586507757372601113806919281835982 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"3.xbar_access_same_device_slow_rsp.57539275126550028397826309309026398884267793794495302156713536385706797887469","seed":57539275126550028397826309309026398884267793794495302156713536385706797887469,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1095561197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1095561197' seed=57539275126550028397826309309026398884267793794495302156713536385706797887469 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57539275126550028397826309309026398884267793794495302156713536385706797887469 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"3.xbar_same_source.20994954102564263994729718564884649730038245172310478219599311393236181399660","seed":20994954102564263994729718564884649730038245172310478219599311393236181399660,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1206466668 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1206466668' seed=20994954102564263994729718564884649730038245172310478219599311393236181399660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20994954102564263994729718564884649730038245172310478219599311393236181399660 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"3.xbar_error_random.8583321850152130462429434872958491026872043534966306615081962086397026514002","seed":8583321850152130462429434872958491026872043534966306615081962086397026514002,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1023685714 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1023685714' seed=8583321850152130462429434872958491026872043534966306615081962086397026514002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8583321850152130462429434872958491026872043534966306615081962086397026514002 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"3.xbar_unmapped_addr.12701149659324390070822441385422173537206202208297724059278388399826441739530","seed":12701149659324390070822441385422173537206202208297724059278388399826441739530,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660217098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.660217098' seed=12701149659324390070822441385422173537206202208297724059278388399826441739530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12701149659324390070822441385422173537206202208297724059278388399826441739530 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"3.xbar_error_and_unmapped_addr.28017202371614303373625298460898570419354770556429814369536832415901876570366","seed":28017202371614303373625298460898570419354770556429814369536832415901876570366,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287473406 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1287473406' seed=28017202371614303373625298460898570419354770556429814369536832415901876570366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28017202371614303373625298460898570419354770556429814369536832415901876570366 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"3.xbar_stress_all.18376247455110500016521831176175404512730946971069145305897257374597243245918","seed":18376247455110500016521831176175404512730946971069145305897257374597243245918,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1575523678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1575523678' seed=18376247455110500016521831176175404512730946971069145305897257374597243245918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18376247455110500016521831176175404512730946971069145305897257374597243245918 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"3.xbar_stress_all_with_rand_reset.110803988583285169408963999800421403258647677318009717574433419399540411201629","seed":110803988583285169408963999800421403258647677318009717574433419399540411201629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507484765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3507484765' seed=110803988583285169408963999800421403258647677318009717574433419399540411201629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110803988583285169408963999800421403258647677318009717574433419399540411201629 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"3.xbar_stress_all_with_error.59446376474843100341547777511420629330862417727515145992419339330751612538574","seed":59446376474843100341547777511420629330862417727515145992419339330751612538574,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2632404686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2632404686' seed=59446376474843100341547777511420629330862417727515145992419339330751612538574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59446376474843100341547777511420629330862417727515145992419339330751612538574 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"3.xbar_stress_all_with_reset_error.45314863180551300359745338860994814900501973248506673567801865469283520780249","seed":45314863180551300359745338860994814900501973248506673567801865469283520780249,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4253587417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.4253587417' seed=45314863180551300359745338860994814900501973248506673567801865469283520780249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45314863180551300359745338860994814900501973248506673567801865469283520780249 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"4.chip_sw_all_escalation_resets.84586130449946563288387749557357751943733393934201839876998587386866887494162","seed":84586130449946563288387749557357751943733393934201839876998587386866887494162,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4108782098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.4108782098' seed=84586130449946563288387749557357751943733393934201839876998587386866887494162 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84586130449946563288387749557357751943733393934201839876998587386866887494162 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"4.chip_sw_data_integrity_escalation.43986670977669392005844531826611741756061318531444321817784306112157731702163","seed":43986670977669392005844531826611741756061318531444321817784306112157731702163,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3605448083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.3605448083' seed=43986670977669392005844531826611741756061318531444321817784306112157731702163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43986670977669392005844531826611741756061318531444321817784306112157731702163 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_data_integrity_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"4.chip_sw_uart_tx_rx.55350944883166569114209387976231411202741330138098388205296315340779014505562","seed":55350944883166569114209387976231411202741330138098388205296315340779014505562,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest run_opts='+uart_idx=0 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988098650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2988098650' seed=55350944883166569114209387976231411202741330138098388205296315340779014505562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55350944883166569114209387976231411202741330138098388205296315340779014505562 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_tx_rx_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"4.chip_sw_uart_rand_baudrate.85996921741523378906197770136933507090336225664969995209074411369108490202992","seed":85996921741523378906197770136933507090336225664969995209074411369108490202992,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1571336048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.1571336048' seed=85996921741523378906197770136933507090336225664969995209074411369108490202992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85996921741523378906197770136933507090336225664969995209074411369108490202992 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"4.chip_sw_uart_tx_rx_alt_clk_freq.43391124104344406707138662308457670009483653855935389772588017166531603802333","seed":43391124104344406707138662308457670009483653855935389772588017166531603802333,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest run_opts='+sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=729098461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq.729098461' seed=43391124104344406707138662308457670009483653855935389772588017166531603802333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43391124104344406707138662308457670009483653855935389772588017166531603802333 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"4.chip_sw_lc_ctrl_transition.93513808720557498722453476550857265047250726831254842516880522754223509145749","seed":93513808720557498722453476550857265047250726831254842516880522754223509145749,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4049143957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.4049143957' seed=93513808720557498722453476550857265047250726831254842516880522754223509145749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93513808720557498722453476550857265047250726831254842516880522754223509145749 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_aon_timer_sleep_wdog_sleep_pause","qual_name":"4.chip_sw_aon_timer_sleep_wdog_sleep_pause.89318985789972392438615449153068250239691064470615088366339773076344860931742","seed":89318985789972392438615449153068250239691064470615088366339773076344860931742,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest run_opts='+sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=433944222 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.433944222' seed=89318985789972392438615449153068250239691064470615088366339773076344860931742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89318985789972392438615449153068250239691064470615088366339773076344860931742 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.39953542558917161089451192373851222803984224556894589608894270951936953668382","seed":39953542558917161089451192373851222803984224556894589608894270951936953668382,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.33279146021903116265553554260734296951645281933175226348831192508023011067487","seed":33279146021903116265553554260734296951645281933175226348831192508023011067487,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776497247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.3776497247' seed=33279146021903116265553554260734296951645281933175226348831192508023011067487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33279146021903116265553554260734296951645281933175226348831192508023011067487 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"4.chip_padctrl_attributes.113740899684574049651965815556733516829112850057201499596365959023281085597139","seed":113740899684574049651965815556733516829112850057201499596365959023281085597139,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25413075 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_padctrl_attributes.25413075' seed=113740899684574049651965815556733516829112850057201499596365959023281085597139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113740899684574049651965815556733516829112850057201499596365959023281085597139 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"4.xbar_smoke.76101602381574087936378082073026489070693744539903176505848634520040252532038","seed":76101602381574087936378082073026489070693744539903176505848634520040252532038,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3472778566 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3472778566' seed=76101602381574087936378082073026489070693744539903176505848634520040252532038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76101602381574087936378082073026489070693744539903176505848634520040252532038 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"4.xbar_smoke_zero_delays.51040749009915881620670881624022219512533638333515421715299126400788097052755","seed":51040749009915881620670881624022219512533638333515421715299126400788097052755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3783700563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3783700563' seed=51040749009915881620670881624022219512533638333515421715299126400788097052755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51040749009915881620670881624022219512533638333515421715299126400788097052755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"4.xbar_smoke_large_delays.33059940088264483629579143083620661512965925408491920722252380544251144046607","seed":33059940088264483629579143083620661512965925408491920722252380544251144046607,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611452943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.611452943' seed=33059940088264483629579143083620661512965925408491920722252380544251144046607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33059940088264483629579143083620661512965925408491920722252380544251144046607 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"4.xbar_smoke_slow_rsp.28276921821915881554686760527006129120624994284678446597031828813432507332470","seed":28276921821915881554686760527006129120624994284678446597031828813432507332470,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1407711094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1407711094' seed=28276921821915881554686760527006129120624994284678446597031828813432507332470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28276921821915881554686760527006129120624994284678446597031828813432507332470 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"4.xbar_random.20824033917626753621626961292558692288271254707564582787495120150662362611400","seed":20824033917626753621626961292558692288271254707564582787495120150662362611400,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65191624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.65191624' seed=20824033917626753621626961292558692288271254707564582787495120150662362611400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20824033917626753621626961292558692288271254707564582787495120150662362611400 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"4.xbar_random_zero_delays.2944835848966871879826529052114849765902390511691085903214333545180642386543","seed":2944835848966871879826529052114849765902390511691085903214333545180642386543,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3115557487 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3115557487' seed=2944835848966871879826529052114849765902390511691085903214333545180642386543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2944835848966871879826529052114849765902390511691085903214333545180642386543 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"4.xbar_random_large_delays.84358428666785923442743767451525557390088693765385617758958000097120664681990","seed":84358428666785923442743767451525557390088693765385617758958000097120664681990,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1907359238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1907359238' seed=84358428666785923442743767451525557390088693765385617758958000097120664681990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84358428666785923442743767451525557390088693765385617758958000097120664681990 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"4.xbar_random_slow_rsp.107690310195828032764913865755684692465560271193208574649698226727429164687948","seed":107690310195828032764913865755684692465560271193208574649698226727429164687948,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3430605388 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3430605388' seed=107690310195828032764913865755684692465560271193208574649698226727429164687948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107690310195828032764913865755684692465560271193208574649698226727429164687948 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"4.xbar_access_same_device.68322605167254656444991453005600470561278933940719449672881049175278417844179","seed":68322605167254656444991453005600470561278933940719449672881049175278417844179,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=636983251 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.636983251' seed=68322605167254656444991453005600470561278933940719449672881049175278417844179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68322605167254656444991453005600470561278933940719449672881049175278417844179 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"4.xbar_access_same_device_slow_rsp.98300591116047075633880497893483695348477414799805868412528201231190764017404","seed":98300591116047075633880497893483695348477414799805868412528201231190764017404,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1593300732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1593300732' seed=98300591116047075633880497893483695348477414799805868412528201231190764017404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98300591116047075633880497893483695348477414799805868412528201231190764017404 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"4.xbar_same_source.114306817446146125023172119464294773228337212315059041923127633284097961436673","seed":114306817446146125023172119464294773228337212315059041923127633284097961436673,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3680577025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3680577025' seed=114306817446146125023172119464294773228337212315059041923127633284097961436673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114306817446146125023172119464294773228337212315059041923127633284097961436673 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"4.xbar_error_random.5821430912756448169273662604077943182782859544166047305935643621255963604100","seed":5821430912756448169273662604077943182782859544166047305935643621255963604100,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3849712772 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3849712772' seed=5821430912756448169273662604077943182782859544166047305935643621255963604100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5821430912756448169273662604077943182782859544166047305935643621255963604100 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"4.xbar_unmapped_addr.59319425104760671484901101546551286554701305109089185624699778677298572400999","seed":59319425104760671484901101546551286554701305109089185624699778677298572400999,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2501744999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2501744999' seed=59319425104760671484901101546551286554701305109089185624699778677298572400999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59319425104760671484901101546551286554701305109089185624699778677298572400999 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"4.xbar_error_and_unmapped_addr.93611972256544220648939031039785482661734055960455932632061429135229149955175","seed":93611972256544220648939031039785482661734055960455932632061429135229149955175,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2548745319 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2548745319' seed=93611972256544220648939031039785482661734055960455932632061429135229149955175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93611972256544220648939031039785482661734055960455932632061429135229149955175 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"4.xbar_stress_all.50387395378673911427164316829997313797349176604792570981421448892401925674858","seed":50387395378673911427164316829997313797349176604792570981421448892401925674858,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075842410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2075842410' seed=50387395378673911427164316829997313797349176604792570981421448892401925674858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50387395378673911427164316829997313797349176604792570981421448892401925674858 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"4.xbar_stress_all_with_rand_reset.16631981622298807846606012539890553625343933541818535302020712928189430149057","seed":16631981622298807846606012539890553625343933541818535302020712928189430149057,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4108890049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.4108890049' seed=16631981622298807846606012539890553625343933541818535302020712928189430149057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16631981622298807846606012539890553625343933541818535302020712928189430149057 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"4.xbar_stress_all_with_error.14398528126571098947106318655032461337580000991331134822595859788469136607466","seed":14398528126571098947106318655032461337580000991331134822595859788469136607466,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2382973162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2382973162' seed=14398528126571098947106318655032461337580000991331134822595859788469136607466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14398528126571098947106318655032461337580000991331134822595859788469136607466 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"4.xbar_stress_all_with_reset_error.64263923958665674110567118663906774380542119336506577619223948504288187792492","seed":64263923958665674110567118663906774380542119336506577619223948504288187792492,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2069511276 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2069511276' seed=64263923958665674110567118663906774380542119336506577619223948504288187792492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64263923958665674110567118663906774380542119336506577619223948504288187792492 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"5.chip_sw_all_escalation_resets.305879494448011862504204946292659093621224099503366091117675557961888514000","seed":305879494448011862504204946292659093621224099503366091117675557961888514000,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2166439888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2166439888' seed=305879494448011862504204946292659093621224099503366091117675557961888514000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=305879494448011862504204946292659093621224099503366091117675557961888514000 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"5.chip_sw_data_integrity_escalation.96852523484729185650963159229433312496778894561070254695436343205549877712741","seed":96852523484729185650963159229433312496778894561070254695436343205549877712741,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4262942565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.4262942565' seed=96852523484729185650963159229433312496778894561070254695436343205549877712741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96852523484729185650963159229433312496778894561070254695436343205549877712741 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_data_integrity_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"5.chip_sw_uart_rand_baudrate.54865770928672023411737489853047854658794936467443227417175112230310357631540","seed":54865770928672023411737489853047854658794936467443227417175112230310357631540,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1893859892 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1893859892' seed=54865770928672023411737489853047854658794936467443227417175112230310357631540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54865770928672023411737489853047854658794936467443227417175112230310357631540 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"5.chip_sw_lc_ctrl_transition.113704207125505437807633429066881521127995407944245289969033425024562112344226","seed":113704207125505437807633429066881521127995407944245289969033425024562112344226,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1711911074 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1711911074' seed=113704207125505437807633429066881521127995407944245289969033425024562112344226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113704207125505437807633429066881521127995407944245289969033425024562112344226 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.10656417574778776857132783429643722828201223456541328393815314306910405432102","seed":10656417574778776857132783429643722828201223456541328393815314306910405432102,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.86191422541928593995427607608803657862095162435038935295237303974596831317045","seed":86191422541928593995427607608803657862095162435038935295237303974596831317045,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251866677 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3251866677' seed=86191422541928593995427607608803657862095162435038935295237303974596831317045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86191422541928593995427607608803657862095162435038935295237303974596831317045 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"5.chip_padctrl_attributes.102290904099114627750672727079442033439820544665543691401321333301551507631510","seed":102290904099114627750672727079442033439820544665543691401321333301551507631510,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287056790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_padctrl_attributes.1287056790' seed=102290904099114627750672727079442033439820544665543691401321333301551507631510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102290904099114627750672727079442033439820544665543691401321333301551507631510 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"5.xbar_smoke.77484126482910593788753057286038707941083076891392136883831654684755413054534","seed":77484126482910593788753057286038707941083076891392136883831654684755413054534,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317576774 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3317576774' seed=77484126482910593788753057286038707941083076891392136883831654684755413054534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77484126482910593788753057286038707941083076891392136883831654684755413054534 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"5.xbar_smoke_zero_delays.115491366031212391069570251568254005458346785714706522527642759910447348236637","seed":115491366031212391069570251568254005458346785714706522527642759910447348236637,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1098170717 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1098170717' seed=115491366031212391069570251568254005458346785714706522527642759910447348236637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=115491366031212391069570251568254005458346785714706522527642759910447348236637 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"5.xbar_smoke_large_delays.96291729234286176218206768035593961525814913112108209337600561950510576259055","seed":96291729234286176218206768035593961525814913112108209337600561950510576259055,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3359592431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3359592431' seed=96291729234286176218206768035593961525814913112108209337600561950510576259055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96291729234286176218206768035593961525814913112108209337600561950510576259055 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"5.xbar_smoke_slow_rsp.30427601944407932765507570828870838802904196320561619961675698329716537316113","seed":30427601944407932765507570828870838802904196320561619961675698329716537316113,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=681202449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.681202449' seed=30427601944407932765507570828870838802904196320561619961675698329716537316113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30427601944407932765507570828870838802904196320561619961675698329716537316113 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"5.xbar_random.75195103283441411986459891853241212172315484860171745772828381444458285605181","seed":75195103283441411986459891853241212172315484860171745772828381444458285605181,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=9937213 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.9937213' seed=75195103283441411986459891853241212172315484860171745772828381444458285605181 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75195103283441411986459891853241212172315484860171745772828381444458285605181 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"5.xbar_random_zero_delays.112213619782601305025892918194652056986642517884811048785124671188601020540812","seed":112213619782601305025892918194652056986642517884811048785124671188601020540812,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3794724748 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3794724748' seed=112213619782601305025892918194652056986642517884811048785124671188601020540812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112213619782601305025892918194652056986642517884811048785124671188601020540812 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"5.xbar_random_large_delays.51812544261862455243091158574517726233086264684112037930985877780983475910733","seed":51812544261862455243091158574517726233086264684112037930985877780983475910733,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4105222221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4105222221' seed=51812544261862455243091158574517726233086264684112037930985877780983475910733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51812544261862455243091158574517726233086264684112037930985877780983475910733 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"5.xbar_random_slow_rsp.26684005447566926778197903333514539825681580684892105470466397867152304664898","seed":26684005447566926778197903333514539825681580684892105470466397867152304664898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4289884482 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4289884482' seed=26684005447566926778197903333514539825681580684892105470466397867152304664898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26684005447566926778197903333514539825681580684892105470466397867152304664898 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"5.xbar_access_same_device.1518917113035607617756091832794295112193595730353493949487532804393173513853","seed":1518917113035607617756091832794295112193595730353493949487532804393173513853,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181456509 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4181456509' seed=1518917113035607617756091832794295112193595730353493949487532804393173513853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1518917113035607617756091832794295112193595730353493949487532804393173513853 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"5.xbar_access_same_device_slow_rsp.92954872370621137338384414964785978599972762829992401660199325792908252999028","seed":92954872370621137338384414964785978599972762829992401660199325792908252999028,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=184479092 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.184479092' seed=92954872370621137338384414964785978599972762829992401660199325792908252999028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92954872370621137338384414964785978599972762829992401660199325792908252999028 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"5.xbar_same_source.111990218743327133795637182116537741385047181805870079279909395320919551410300","seed":111990218743327133795637182116537741385047181805870079279909395320919551410300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2207809660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2207809660' seed=111990218743327133795637182116537741385047181805870079279909395320919551410300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111990218743327133795637182116537741385047181805870079279909395320919551410300 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"5.xbar_error_random.49994291162643489658727065864486296202907566276262600738952336817365257373075","seed":49994291162643489658727065864486296202907566276262600738952336817365257373075,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286137747 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4286137747' seed=49994291162643489658727065864486296202907566276262600738952336817365257373075 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49994291162643489658727065864486296202907566276262600738952336817365257373075 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"5.xbar_unmapped_addr.3506256821616336976493659336407295437821756827218188890529391370024001242809","seed":3506256821616336976493659336407295437821756827218188890529391370024001242809,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37258937 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.37258937' seed=3506256821616336976493659336407295437821756827218188890529391370024001242809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3506256821616336976493659336407295437821756827218188890529391370024001242809 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"5.xbar_error_and_unmapped_addr.46843227009514074384561047676342776950918574039544962513821687262499418100392","seed":46843227009514074384561047676342776950918574039544962513821687262499418100392,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3449246376 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3449246376' seed=46843227009514074384561047676342776950918574039544962513821687262499418100392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46843227009514074384561047676342776950918574039544962513821687262499418100392 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"5.xbar_stress_all.39012530834307612914987857365060758257663385297622832495702458101386181342948","seed":39012530834307612914987857365060758257663385297622832495702458101386181342948,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1175189220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1175189220' seed=39012530834307612914987857365060758257663385297622832495702458101386181342948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39012530834307612914987857365060758257663385297622832495702458101386181342948 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"5.xbar_stress_all_with_rand_reset.82086720841543715217392667552233716921581454745507577322875602881945590933232","seed":82086720841543715217392667552233716921581454745507577322875602881945590933232,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830318320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.830318320' seed=82086720841543715217392667552233716921581454745507577322875602881945590933232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82086720841543715217392667552233716921581454745507577322875602881945590933232 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"5.xbar_stress_all_with_error.24802629370041071549927744383103108970541842448257540370587660887464821018142","seed":24802629370041071549927744383103108970541842448257540370587660887464821018142,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3937816094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3937816094' seed=24802629370041071549927744383103108970541842448257540370587660887464821018142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24802629370041071549927744383103108970541842448257540370587660887464821018142 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"5.xbar_stress_all_with_reset_error.77335517817621633186217597218516563639085582219688716208180537110763833386414","seed":77335517817621633186217597218516563639085582219688716208180537110763833386414,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221822382 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.4221822382' seed=77335517817621633186217597218516563639085582219688716208180537110763833386414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77335517817621633186217597218516563639085582219688716208180537110763833386414 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"6.chip_sw_all_escalation_resets.75861785727310823479686581673300776122205921752950759556238210940521852683059","seed":75861785727310823479686581673300776122205921752950759556238210940521852683059,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3812344627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3812344627' seed=75861785727310823479686581673300776122205921752950759556238210940521852683059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75861785727310823479686581673300776122205921752950759556238210940521852683059 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"6.chip_sw_uart_rand_baudrate.53071703948344796591278048863592739624313205808920069916811411115112445214722","seed":53071703948344796591278048863592739624313205808920069916811411115112445214722,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113817090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1113817090' seed=53071703948344796591278048863592739624313205808920069916811411115112445214722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53071703948344796591278048863592739624313205808920069916811411115112445214722 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"6.chip_sw_lc_ctrl_transition.97465980418276277133929112823064692441980415690215707556802486797219910891309","seed":97465980418276277133929112823064692441980415690215707556802486797219910891309,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4030183213 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.4030183213' seed=97465980418276277133929112823064692441980415690215707556802486797219910891309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97465980418276277133929112823064692441980415690215707556802486797219910891309 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.89652352063472186805014702577680354757153999574454524011161831857988219437157","seed":89652352063472186805014702577680354757153999574454524011161831857988219437157,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.29232708524342665126833906483865028668262555120642529925818197817288537531152","seed":29232708524342665126833906483865028668262555120642529925818197817288537531152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683874576 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1683874576' seed=29232708524342665126833906483865028668262555120642529925818197817288537531152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29232708524342665126833906483865028668262555120642529925818197817288537531152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"6.chip_padctrl_attributes.48631039336938703006686818611256903859880648884606956832893814828112790891043","seed":48631039336938703006686818611256903859880648884606956832893814828112790891043,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3552258595 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_padctrl_attributes.3552258595' seed=48631039336938703006686818611256903859880648884606956832893814828112790891043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48631039336938703006686818611256903859880648884606956832893814828112790891043 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"6.xbar_smoke.75802557511883195096067743908535754435364564111684955813480761956276680042544","seed":75802557511883195096067743908535754435364564111684955813480761956276680042544,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1854187568 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1854187568' seed=75802557511883195096067743908535754435364564111684955813480761956276680042544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75802557511883195096067743908535754435364564111684955813480761956276680042544 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"6.xbar_smoke_zero_delays.83172250569320654755805852755877604566013775801249049127406725839617030481066","seed":83172250569320654755805852755877604566013775801249049127406725839617030481066,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690587306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3690587306' seed=83172250569320654755805852755877604566013775801249049127406725839617030481066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83172250569320654755805852755877604566013775801249049127406725839617030481066 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"6.xbar_smoke_large_delays.114282070633682008767919250262818371328024251674906073936360849290388047707430","seed":114282070633682008767919250262818371328024251674906073936360849290388047707430,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2304556326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2304556326' seed=114282070633682008767919250262818371328024251674906073936360849290388047707430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114282070633682008767919250262818371328024251674906073936360849290388047707430 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"6.xbar_smoke_slow_rsp.69582307229515073457414184027997847810742428090483592604505118315344314566575","seed":69582307229515073457414184027997847810742428090483592604505118315344314566575,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3273459631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3273459631' seed=69582307229515073457414184027997847810742428090483592604505118315344314566575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69582307229515073457414184027997847810742428090483592604505118315344314566575 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"6.xbar_random.75541512176664581018499004286793465534235992193659914201811089945003034933658","seed":75541512176664581018499004286793465534235992193659914201811089945003034933658,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1386477978 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1386477978' seed=75541512176664581018499004286793465534235992193659914201811089945003034933658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75541512176664581018499004286793465534235992193659914201811089945003034933658 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"6.xbar_random_zero_delays.22517395252908260947940792158874857513324656307587301810669175245768663908763","seed":22517395252908260947940792158874857513324656307587301810669175245768663908763,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180558235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4180558235' seed=22517395252908260947940792158874857513324656307587301810669175245768663908763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22517395252908260947940792158874857513324656307587301810669175245768663908763 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"6.xbar_random_large_delays.87256469892495925526494027072379525980898168739930462640199445335236692804058","seed":87256469892495925526494027072379525980898168739930462640199445335236692804058,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2579890650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2579890650' seed=87256469892495925526494027072379525980898168739930462640199445335236692804058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87256469892495925526494027072379525980898168739930462640199445335236692804058 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"6.xbar_random_slow_rsp.76906794356972277403552554232592115009208237313926588691751772488554920877381","seed":76906794356972277403552554232592115009208237313926588691751772488554920877381,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2841189701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2841189701' seed=76906794356972277403552554232592115009208237313926588691751772488554920877381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76906794356972277403552554232592115009208237313926588691751772488554920877381 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"6.xbar_access_same_device.84466819824469605101315057209554685498977137646374648822764047465784578566933","seed":84466819824469605101315057209554685498977137646374648822764047465784578566933,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298112789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2298112789' seed=84466819824469605101315057209554685498977137646374648822764047465784578566933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84466819824469605101315057209554685498977137646374648822764047465784578566933 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"6.xbar_access_same_device_slow_rsp.89416768890702804050121032577626395100881838517051186592178006850359018174926","seed":89416768890702804050121032577626395100881838517051186592178006850359018174926,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660912590 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.660912590' seed=89416768890702804050121032577626395100881838517051186592178006850359018174926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89416768890702804050121032577626395100881838517051186592178006850359018174926 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"6.xbar_same_source.23989943489949381792381111707387860070773065728605091896042365134793531437335","seed":23989943489949381792381111707387860070773065728605091896042365134793531437335,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=687583511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.687583511' seed=23989943489949381792381111707387860070773065728605091896042365134793531437335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23989943489949381792381111707387860070773065728605091896042365134793531437335 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"6.xbar_error_random.35717348558982770371031035075577991010570037917815834965772840129116168774960","seed":35717348558982770371031035075577991010570037917815834965772840129116168774960,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862184752 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.862184752' seed=35717348558982770371031035075577991010570037917815834965772840129116168774960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35717348558982770371031035075577991010570037917815834965772840129116168774960 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"6.xbar_unmapped_addr.61501150188974810278025142408128909920013968152172914506595547579580206040554","seed":61501150188974810278025142408128909920013968152172914506595547579580206040554,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3827058154 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3827058154' seed=61501150188974810278025142408128909920013968152172914506595547579580206040554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61501150188974810278025142408128909920013968152172914506595547579580206040554 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"6.xbar_error_and_unmapped_addr.91013303941833410507461685123788448424460328504039230616355723479866954692490","seed":91013303941833410507461685123788448424460328504039230616355723479866954692490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3869718410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3869718410' seed=91013303941833410507461685123788448424460328504039230616355723479866954692490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91013303941833410507461685123788448424460328504039230616355723479866954692490 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"6.xbar_stress_all.88701920860535570831694543138180825919167325984778644498348997567787257496103","seed":88701920860535570831694543138180825919167325984778644498348997567787257496103,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2987065895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2987065895' seed=88701920860535570831694543138180825919167325984778644498348997567787257496103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88701920860535570831694543138180825919167325984778644498348997567787257496103 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"6.xbar_stress_all_with_rand_reset.48057179818584786263843793887182798945713543992704873241990807549271853051383","seed":48057179818584786263843793887182798945713543992704873241990807549271853051383,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2982489591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2982489591' seed=48057179818584786263843793887182798945713543992704873241990807549271853051383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48057179818584786263843793887182798945713543992704873241990807549271853051383 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"6.xbar_stress_all_with_error.4786822724200692652531008312695332225456807680547593131693883686152056351039","seed":4786822724200692652531008312695332225456807680547593131693883686152056351039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221863743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1221863743' seed=4786822724200692652531008312695332225456807680547593131693883686152056351039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4786822724200692652531008312695332225456807680547593131693883686152056351039 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"6.xbar_stress_all_with_reset_error.58953789386172214185013957150419821160773055547249358622595064124614852443125","seed":58953789386172214185013957150419821160773055547249358622595064124614852443125,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3721362421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3721362421' seed=58953789386172214185013957150419821160773055547249358622595064124614852443125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58953789386172214185013957150419821160773055547249358622595064124614852443125 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"7.chip_sw_all_escalation_resets.94356148860010020870932069669572094635337489177321097709129948251528456458250","seed":94356148860010020870932069669572094635337489177321097709129948251528456458250,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403829258 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3403829258' seed=94356148860010020870932069669572094635337489177321097709129948251528456458250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94356148860010020870932069669572094635337489177321097709129948251528456458250 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"7.chip_sw_uart_rand_baudrate.115707156331576552002546647091395972330326094405498634491313952245991402080841","seed":115707156331576552002546647091395972330326094405498634491313952245991402080841,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141789769 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.141789769' seed=115707156331576552002546647091395972330326094405498634491313952245991402080841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=115707156331576552002546647091395972330326094405498634491313952245991402080841 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"7.chip_sw_lc_ctrl_transition.114013336197099048780734597789432310852127509794317497091462993079880546084198","seed":114013336197099048780734597789432310852127509794317497091462993079880546084198,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1541498214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.1541498214' seed=114013336197099048780734597789432310852127509794317497091462993079880546084198 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114013336197099048780734597789432310852127509794317497091462993079880546084198 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.7255445634986878582900106320247628546560846397704778164354377318722427629474","seed":7255445634986878582900106320247628546560846397704778164354377318722427629474,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.103683678233151416886243423672703623494777096925401455604749026679872023571061","seed":103683678233151416886243423672703623494777096925401455604749026679872023571061,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2528258677 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2528258677' seed=103683678233151416886243423672703623494777096925401455604749026679872023571061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103683678233151416886243423672703623494777096925401455604749026679872023571061 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"7.chip_padctrl_attributes.19152176233146972981928876005983664576072161199272055040774994006622909232508","seed":19152176233146972981928876005983664576072161199272055040774994006622909232508,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268853628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_padctrl_attributes.2268853628' seed=19152176233146972981928876005983664576072161199272055040774994006622909232508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19152176233146972981928876005983664576072161199272055040774994006622909232508 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"7.xbar_smoke.66617377914291401075742077536446916828368114586644864325473294251977771234494","seed":66617377914291401075742077536446916828368114586644864325473294251977771234494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395728574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3395728574' seed=66617377914291401075742077536446916828368114586644864325473294251977771234494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66617377914291401075742077536446916828368114586644864325473294251977771234494 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"7.xbar_smoke_zero_delays.114391031342740635662901369758257675579713604886138631470032273371348820732148","seed":114391031342740635662901369758257675579713604886138631470032273371348820732148,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662350068 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.662350068' seed=114391031342740635662901369758257675579713604886138631470032273371348820732148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114391031342740635662901369758257675579713604886138631470032273371348820732148 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"7.xbar_smoke_large_delays.52233986829011981071921548513213543962291461291916269401477588893484719484865","seed":52233986829011981071921548513213543962291461291916269401477588893484719484865,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3258134465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3258134465' seed=52233986829011981071921548513213543962291461291916269401477588893484719484865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52233986829011981071921548513213543962291461291916269401477588893484719484865 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"7.xbar_smoke_slow_rsp.17840246206571785026494652441122728205196007399734606359490483159313219180417","seed":17840246206571785026494652441122728205196007399734606359490483159313219180417,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2283919233 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2283919233' seed=17840246206571785026494652441122728205196007399734606359490483159313219180417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17840246206571785026494652441122728205196007399734606359490483159313219180417 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"7.xbar_random.37873487024701405552173049450049589190174951074737301599742210467444939027268","seed":37873487024701405552173049450049589190174951074737301599742210467444939027268,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1972892484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1972892484' seed=37873487024701405552173049450049589190174951074737301599742210467444939027268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37873487024701405552173049450049589190174951074737301599742210467444939027268 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"7.xbar_random_zero_delays.34732610913056848344814512412441484143134907542245287081666980271857290698428","seed":34732610913056848344814512412441484143134907542245287081666980271857290698428,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1860689596 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1860689596' seed=34732610913056848344814512412441484143134907542245287081666980271857290698428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34732610913056848344814512412441484143134907542245287081666980271857290698428 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"7.xbar_random_large_delays.104948552473230951682875214975722415177742841676004982589569532205456747296751","seed":104948552473230951682875214975722415177742841676004982589569532205456747296751,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2253813743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2253813743' seed=104948552473230951682875214975722415177742841676004982589569532205456747296751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104948552473230951682875214975722415177742841676004982589569532205456747296751 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"7.xbar_random_slow_rsp.17987277050026769594321782910696010422588252524193140899416323121003116594894","seed":17987277050026769594321782910696010422588252524193140899416323121003116594894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835397838 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3835397838' seed=17987277050026769594321782910696010422588252524193140899416323121003116594894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17987277050026769594321782910696010422588252524193140899416323121003116594894 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"7.xbar_access_same_device.38060610716506633565047571786637819046096544141680450801759798538616841933749","seed":38060610716506633565047571786637819046096544141680450801759798538616841933749,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2187826101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2187826101' seed=38060610716506633565047571786637819046096544141680450801759798538616841933749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38060610716506633565047571786637819046096544141680450801759798538616841933749 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"7.xbar_access_same_device_slow_rsp.93311191040610486907758724645823730740013411722641282660608601649150445755879","seed":93311191040610486907758724645823730740013411722641282660608601649150445755879,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=935075303 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.935075303' seed=93311191040610486907758724645823730740013411722641282660608601649150445755879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93311191040610486907758724645823730740013411722641282660608601649150445755879 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"7.xbar_same_source.60017234483857608362890639867064282123846832227611036116379879043258179289405","seed":60017234483857608362890639867064282123846832227611036116379879043258179289405,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1736868157 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1736868157' seed=60017234483857608362890639867064282123846832227611036116379879043258179289405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60017234483857608362890639867064282123846832227611036116379879043258179289405 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"7.xbar_error_random.115240672269301262488704525764994176063938467140619564384764130799098150742656","seed":115240672269301262488704525764994176063938467140619564384764130799098150742656,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1621584512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1621584512' seed=115240672269301262488704525764994176063938467140619564384764130799098150742656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=115240672269301262488704525764994176063938467140619564384764130799098150742656 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"7.xbar_unmapped_addr.13696841153017765125535746605444596472689596910537578070589847899227781762385","seed":13696841153017765125535746605444596472689596910537578070589847899227781762385,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685832529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2685832529' seed=13696841153017765125535746605444596472689596910537578070589847899227781762385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13696841153017765125535746605444596472689596910537578070589847899227781762385 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"7.xbar_error_and_unmapped_addr.68752767727360014260665772469292362184304279128854347601741688873738757892105","seed":68752767727360014260665772469292362184304279128854347601741688873738757892105,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389783049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1389783049' seed=68752767727360014260665772469292362184304279128854347601741688873738757892105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68752767727360014260665772469292362184304279128854347601741688873738757892105 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"7.xbar_stress_all.87389784225742519918229268303773921851939086145091070757864828080461868613129","seed":87389784225742519918229268303773921851939086145091070757864828080461868613129,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988700681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3988700681' seed=87389784225742519918229268303773921851939086145091070757864828080461868613129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87389784225742519918229268303773921851939086145091070757864828080461868613129 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"7.xbar_stress_all_with_rand_reset.19543720886178812825538350660307926284169983920628118515318316641007149751327","seed":19543720886178812825538350660307926284169983920628118515318316641007149751327,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2694028319 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2694028319' seed=19543720886178812825538350660307926284169983920628118515318316641007149751327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19543720886178812825538350660307926284169983920628118515318316641007149751327 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"7.xbar_stress_all_with_error.114179805341014361939273778647165756994892074179430806046259700262842381936427","seed":114179805341014361939273778647165756994892074179430806046259700262842381936427,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41985835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.41985835' seed=114179805341014361939273778647165756994892074179430806046259700262842381936427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114179805341014361939273778647165756994892074179430806046259700262842381936427 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"7.xbar_stress_all_with_reset_error.66385119648390771477020818257487589611343353008669535146500177496337871149982","seed":66385119648390771477020818257487589611343353008669535146500177496337871149982,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1028529054 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1028529054' seed=66385119648390771477020818257487589611343353008669535146500177496337871149982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66385119648390771477020818257487589611343353008669535146500177496337871149982 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"8.chip_sw_all_escalation_resets.11776739090485748807117031230484354743261452926526340890521353917033914338784","seed":11776739090485748807117031230484354743261452926526340890521353917033914338784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1966116320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1966116320' seed=11776739090485748807117031230484354743261452926526340890521353917033914338784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11776739090485748807117031230484354743261452926526340890521353917033914338784 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"8.chip_sw_uart_rand_baudrate.104075758338433651754982696600495194571426646854363705356945788797302863350133","seed":104075758338433651754982696600495194571426646854363705356945788797302863350133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345557365 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.345557365' seed=104075758338433651754982696600495194571426646854363705356945788797302863350133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104075758338433651754982696600495194571426646854363705356945788797302863350133 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"8.chip_sw_lc_ctrl_transition.74787922060073611082084691996794470349415038666551364361662679917042464613741","seed":74787922060073611082084691996794470349415038666551364361662679917042464613741,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=823027053 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.823027053' seed=74787922060073611082084691996794470349415038666551364361662679917042464613741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74787922060073611082084691996794470349415038666551364361662679917042464613741 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.104346421684913171536686696274192482942910409356526058171479825711131052473120","seed":104346421684913171536686696274192482942910409356526058171479825711131052473120,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.112643998192951714383633836037797515291568807178399216883796282030901664052682","seed":112643998192951714383633836037797515291568807178399216883796282030901664052682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2855171530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.2855171530' seed=112643998192951714383633836037797515291568807178399216883796282030901664052682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112643998192951714383633836037797515291568807178399216883796282030901664052682 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"8.chip_padctrl_attributes.25013889429395030892359658767663914635770286211412455120283097807086536194543","seed":25013889429395030892359658767663914635770286211412455120283097807086536194543,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2534242799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_padctrl_attributes.2534242799' seed=25013889429395030892359658767663914635770286211412455120283097807086536194543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25013889429395030892359658767663914635770286211412455120283097807086536194543 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"8.xbar_smoke.29856708829230852225089306850424434980451571705083836606353438247472441778661","seed":29856708829230852225089306850424434980451571705083836606353438247472441778661,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=574546405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.574546405' seed=29856708829230852225089306850424434980451571705083836606353438247472441778661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29856708829230852225089306850424434980451571705083836606353438247472441778661 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"8.xbar_smoke_zero_delays.55295206703704016626940837161074945152030077736417651977375828528473367684942","seed":55295206703704016626940837161074945152030077736417651977375828528473367684942,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3833374542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3833374542' seed=55295206703704016626940837161074945152030077736417651977375828528473367684942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55295206703704016626940837161074945152030077736417651977375828528473367684942 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"8.xbar_smoke_large_delays.29232860451621439400147871749412714477096242260766613302227456993112715235746","seed":29232860451621439400147871749412714477096242260766613302227456993112715235746,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469911458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1469911458' seed=29232860451621439400147871749412714477096242260766613302227456993112715235746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29232860451621439400147871749412714477096242260766613302227456993112715235746 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"8.xbar_smoke_slow_rsp.76925576156010660372023774502226589780886208639743864662492499153065595525936","seed":76925576156010660372023774502226589780886208639743864662492499153065595525936,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1766742832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1766742832' seed=76925576156010660372023774502226589780886208639743864662492499153065595525936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76925576156010660372023774502226589780886208639743864662492499153065595525936 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"8.xbar_random.7134925342450847701705584483882798758455158551478005723528653041816308547812","seed":7134925342450847701705584483882798758455158551478005723528653041816308547812,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2108424420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2108424420' seed=7134925342450847701705584483882798758455158551478005723528653041816308547812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7134925342450847701705584483882798758455158551478005723528653041816308547812 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"8.xbar_random_zero_delays.84024281173463245664493692669304091450346995063122586924952884919850075087486","seed":84024281173463245664493692669304091450346995063122586924952884919850075087486,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634053246 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.634053246' seed=84024281173463245664493692669304091450346995063122586924952884919850075087486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84024281173463245664493692669304091450346995063122586924952884919850075087486 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"8.xbar_random_large_delays.103879639130382474081810804149999641210047370722830558646003815485316825392193","seed":103879639130382474081810804149999641210047370722830558646003815485316825392193,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430116929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2430116929' seed=103879639130382474081810804149999641210047370722830558646003815485316825392193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103879639130382474081810804149999641210047370722830558646003815485316825392193 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"8.xbar_random_slow_rsp.2805352999577819186774484794164194395073648825186514614040970440255242259682","seed":2805352999577819186774484794164194395073648825186514614040970440255242259682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1859407074 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1859407074' seed=2805352999577819186774484794164194395073648825186514614040970440255242259682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2805352999577819186774484794164194395073648825186514614040970440255242259682 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"8.xbar_access_same_device.79652837353921379201950040796650627447123692052840400666543910272462382748696","seed":79652837353921379201950040796650627447123692052840400666543910272462382748696,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1518392344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1518392344' seed=79652837353921379201950040796650627447123692052840400666543910272462382748696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79652837353921379201950040796650627447123692052840400666543910272462382748696 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"8.xbar_access_same_device_slow_rsp.57947277199200791083465941368156252205190775841363016004229712846830296690417","seed":57947277199200791083465941368156252205190775841363016004229712846830296690417,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524062961 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.3524062961' seed=57947277199200791083465941368156252205190775841363016004229712846830296690417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57947277199200791083465941368156252205190775841363016004229712846830296690417 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"8.xbar_same_source.12662592511473588075466672991388534447049659651579911625679822733412247077741","seed":12662592511473588075466672991388534447049659651579911625679822733412247077741,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3551593325 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3551593325' seed=12662592511473588075466672991388534447049659651579911625679822733412247077741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12662592511473588075466672991388534447049659651579911625679822733412247077741 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"8.xbar_error_random.73525838785323098144081494086929988051044637194481151418630357761772333982547","seed":73525838785323098144081494086929988051044637194481151418630357761772333982547,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2324063059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2324063059' seed=73525838785323098144081494086929988051044637194481151418630357761772333982547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73525838785323098144081494086929988051044637194481151418630357761772333982547 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"8.xbar_unmapped_addr.40272312879623571837199837196843226117027432626787397883114306928535886120769","seed":40272312879623571837199837196843226117027432626787397883114306928535886120769,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1649690433 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1649690433' seed=40272312879623571837199837196843226117027432626787397883114306928535886120769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40272312879623571837199837196843226117027432626787397883114306928535886120769 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"8.xbar_error_and_unmapped_addr.88511485450013955183119459730301686906876452007348482099677777986117042722700","seed":88511485450013955183119459730301686906876452007348482099677777986117042722700,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1742231436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1742231436' seed=88511485450013955183119459730301686906876452007348482099677777986117042722700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88511485450013955183119459730301686906876452007348482099677777986117042722700 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"8.xbar_stress_all.69783725409380003155014211998553932853741406646509949667189315738677967153955","seed":69783725409380003155014211998553932853741406646509949667189315738677967153955,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3670633251 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3670633251' seed=69783725409380003155014211998553932853741406646509949667189315738677967153955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69783725409380003155014211998553932853741406646509949667189315738677967153955 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"8.xbar_stress_all_with_rand_reset.44030840105308627219990857133230358425421223502037781827893299948867124965943","seed":44030840105308627219990857133230358425421223502037781827893299948867124965943,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=393720375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.393720375' seed=44030840105308627219990857133230358425421223502037781827893299948867124965943 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44030840105308627219990857133230358425421223502037781827893299948867124965943 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"8.xbar_stress_all_with_error.94904163265019502378771464683730412396680837416135688725936730713782861999914","seed":94904163265019502378771464683730412396680837416135688725936730713782861999914,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3971526442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3971526442' seed=94904163265019502378771464683730412396680837416135688725936730713782861999914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94904163265019502378771464683730412396680837416135688725936730713782861999914 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"8.xbar_stress_all_with_reset_error.98709525660060354462752399059869984702774984497360422496006809888993339623970","seed":98709525660060354462752399059869984702774984497360422496006809888993339623970,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3285830178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3285830178' seed=98709525660060354462752399059869984702774984497360422496006809888993339623970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98709525660060354462752399059869984702774984497360422496006809888993339623970 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"9.chip_sw_all_escalation_resets.97929714563074461064776129512496578628097070403538886224981037723031313382287","seed":97929714563074461064776129512496578628097070403538886224981037723031313382287,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836907407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1836907407' seed=97929714563074461064776129512496578628097070403538886224981037723031313382287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97929714563074461064776129512496578628097070403538886224981037723031313382287 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"9.chip_sw_uart_rand_baudrate.7213998652179934873601449199413689743770204343170343104949780923386414764655","seed":7213998652179934873601449199413689743770204343170343104949780923386414764655,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=834671215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.834671215' seed=7213998652179934873601449199413689743770204343170343104949780923386414764655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7213998652179934873601449199413689743770204343170343104949780923386414764655 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"9.chip_sw_lc_ctrl_transition.61013041676086154714646827225235639165407363984746501388645457829493399503402","seed":61013041676086154714646827225235639165407363984746501388645457829493399503402,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4030349866 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.4030349866' seed=61013041676086154714646827225235639165407363984746501388645457829493399503402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61013041676086154714646827225235639165407363984746501388645457829493399503402 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.27165989007071346957395686234902009931284148261450133214009163475011924342087","seed":27165989007071346957395686234902009931284148261450133214009163475011924342087,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.34620031119588053331677338206082767070726593239030683038543784962398758904078","seed":34620031119588053331677338206082767070726593239030683038543784962398758904078,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=535568654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.535568654' seed=34620031119588053331677338206082767070726593239030683038543784962398758904078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34620031119588053331677338206082767070726593239030683038543784962398758904078 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_padctrl_attributes","qual_name":"9.chip_padctrl_attributes.79710227514048659241498596054299702647298051718387499029427944168537359571527","seed":79710227514048659241498596054299702647298051718387499029427944168537359571527,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_padctrl_attributes/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_padctrl_attributes/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_padctrl_attributes/latest run_opts='+use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3159808583 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_padctrl_attributes.3159808583' seed=79710227514048659241498596054299702647298051718387499029427944168537359571527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79710227514048659241498596054299702647298051718387499029427944168537359571527 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_padctrl_attributes/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_padctrl_attributes_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"9.xbar_smoke.86566472375311009451388203653165338647873514801626586786733292174362910298282","seed":86566472375311009451388203653165338647873514801626586786733292174362910298282,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830616234 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3830616234' seed=86566472375311009451388203653165338647873514801626586786733292174362910298282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86566472375311009451388203653165338647873514801626586786733292174362910298282 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"9.xbar_smoke_zero_delays.80129340239481036808195679044308696978930584207819343429811520905421480533975","seed":80129340239481036808195679044308696978930584207819343429811520905421480533975,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2614632407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2614632407' seed=80129340239481036808195679044308696978930584207819343429811520905421480533975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80129340239481036808195679044308696978930584207819343429811520905421480533975 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"9.xbar_smoke_large_delays.160719584111678228627094837287710992134722412112931896673256009855067472343","seed":160719584111678228627094837287710992134722412112931896673256009855067472343,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2536489431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2536489431' seed=160719584111678228627094837287710992134722412112931896673256009855067472343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=160719584111678228627094837287710992134722412112931896673256009855067472343 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"9.xbar_smoke_slow_rsp.1306936700911040828557355341378911938729612201755149433246522934996513849095","seed":1306936700911040828557355341378911938729612201755149433246522934996513849095,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1737228039 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1737228039' seed=1306936700911040828557355341378911938729612201755149433246522934996513849095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1306936700911040828557355341378911938729612201755149433246522934996513849095 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"9.xbar_random.39471167690877465597152754527466387307334072142531671031861783017352071731630","seed":39471167690877465597152754527466387307334072142531671031861783017352071731630,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3135756718 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3135756718' seed=39471167690877465597152754527466387307334072142531671031861783017352071731630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39471167690877465597152754527466387307334072142531671031861783017352071731630 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"9.xbar_random_zero_delays.103050925424862053392031121388593657735860807433545477602393128505285850809603","seed":103050925424862053392031121388593657735860807433545477602393128505285850809603,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212452611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.212452611' seed=103050925424862053392031121388593657735860807433545477602393128505285850809603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103050925424862053392031121388593657735860807433545477602393128505285850809603 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"9.xbar_random_large_delays.78990758042268788146540925829777997984543294628768958983395491489912120342281","seed":78990758042268788146540925829777997984543294628768958983395491489912120342281,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877328137 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.877328137' seed=78990758042268788146540925829777997984543294628768958983395491489912120342281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78990758042268788146540925829777997984543294628768958983395491489912120342281 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"9.xbar_random_slow_rsp.73735091662396532981684296856774991923529845706386545578482494900917108002588","seed":73735091662396532981684296856774991923529845706386545578482494900917108002588,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4089761564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4089761564' seed=73735091662396532981684296856774991923529845706386545578482494900917108002588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73735091662396532981684296856774991923529845706386545578482494900917108002588 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"9.xbar_access_same_device.12495761145343640516031600537920590008177988885246129611185297509844755618180","seed":12495761145343640516031600537920590008177988885246129611185297509844755618180,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1174083972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1174083972' seed=12495761145343640516031600537920590008177988885246129611185297509844755618180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12495761145343640516031600537920590008177988885246129611185297509844755618180 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"9.xbar_access_same_device_slow_rsp.79759453768091755560186872327373207862830451900925983716112264982661326529409","seed":79759453768091755560186872327373207862830451900925983716112264982661326529409,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198589313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.4198589313' seed=79759453768091755560186872327373207862830451900925983716112264982661326529409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79759453768091755560186872327373207862830451900925983716112264982661326529409 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"9.xbar_same_source.83644620548731371992234147212818659846056770268269349026043461644363784490752","seed":83644620548731371992234147212818659846056770268269349026043461644363784490752,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1526435584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1526435584' seed=83644620548731371992234147212818659846056770268269349026043461644363784490752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83644620548731371992234147212818659846056770268269349026043461644363784490752 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"9.xbar_error_random.100099464848088827639849982063043014171262986881916077365437394878557570868296","seed":100099464848088827639849982063043014171262986881916077365437394878557570868296,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2923570248 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2923570248' seed=100099464848088827639849982063043014171262986881916077365437394878557570868296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100099464848088827639849982063043014171262986881916077365437394878557570868296 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"9.xbar_unmapped_addr.20443046929092490380275179967386159496648235349670604360767193792924012689857","seed":20443046929092490380275179967386159496648235349670604360767193792924012689857,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=492747201 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.492747201' seed=20443046929092490380275179967386159496648235349670604360767193792924012689857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20443046929092490380275179967386159496648235349670604360767193792924012689857 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"9.xbar_error_and_unmapped_addr.10356031916653288099037320656002392880514298728536985244021657977148992524520","seed":10356031916653288099037320656002392880514298728536985244021657977148992524520,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1085935848 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1085935848' seed=10356031916653288099037320656002392880514298728536985244021657977148992524520 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10356031916653288099037320656002392880514298728536985244021657977148992524520 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"9.xbar_stress_all.58692087389697741095528381726942870255043733175913572878769427691623009069957","seed":58692087389697741095528381726942870255043733175913572878769427691623009069957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=520203141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.520203141' seed=58692087389697741095528381726942870255043733175913572878769427691623009069957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58692087389697741095528381726942870255043733175913572878769427691623009069957 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"9.xbar_stress_all_with_rand_reset.73489552638658547365468417987127384889854265116905629772536558671826001583568","seed":73489552638658547365468417987127384889854265116905629772536558671826001583568,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1740103120 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1740103120' seed=73489552638658547365468417987127384889854265116905629772536558671826001583568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73489552638658547365468417987127384889854265116905629772536558671826001583568 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"9.xbar_stress_all_with_error.103146401080820846090789453708845624173394400925184039853472912921965991107861","seed":103146401080820846090789453708845624173394400925184039853472912921965991107861,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3842841877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3842841877' seed=103146401080820846090789453708845624173394400925184039853472912921965991107861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103146401080820846090789453708845624173394400925184039853472912921965991107861 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"9.xbar_stress_all_with_reset_error.27870304813565612621111985543592376099522086248675713221579811469981240026575","seed":27870304813565612621111985543592376099522086248675713221579811469981240026575,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4060112335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.4060112335' seed=27870304813565612621111985543592376099522086248675713221579811469981240026575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27870304813565612621111985543592376099522086248675713221579811469981240026575 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"10.chip_sw_all_escalation_resets.52946685816755633568610002995495356159384759874840985882711908628656559898765","seed":52946685816755633568610002995495356159384759874840985882711908628656559898765,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=368722061 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.368722061' seed=52946685816755633568610002995495356159384759874840985882711908628656559898765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52946685816755633568610002995495356159384759874840985882711908628656559898765 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"10.chip_sw_uart_rand_baudrate.33450473138748853107882412714500309338737358453176378050336155290306433016854","seed":33450473138748853107882412714500309338737358453176378050336155290306433016854,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2826986518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2826986518' seed=33450473138748853107882412714500309338737358453176378050336155290306433016854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33450473138748853107882412714500309338737358453176378050336155290306433016854 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"10.chip_sw_lc_ctrl_transition.36155299744837580984865113411610750329859077960659435226226437666292780057708","seed":36155299744837580984865113411610750329859077960659435226226437666292780057708,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252241516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3252241516' seed=36155299744837580984865113411610750329859077960659435226226437666292780057708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36155299744837580984865113411610750329859077960659435226226437666292780057708 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.106196648233476684912453989925510707813023578359632163705266474245017643897088","seed":106196648233476684912453989925510707813023578359632163705266474245017643897088,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.62086587781497524811819064795991881229908413432515066324574651554714246864650","seed":62086587781497524811819064795991881229908413432515066324574651554714246864650,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3441581834 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3441581834' seed=62086587781497524811819064795991881229908413432515066324574651554714246864650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62086587781497524811819064795991881229908413432515066324574651554714246864650 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"10.xbar_smoke.85553493711013531321496305096307281463993706121524099555012980816762661575158","seed":85553493711013531321496305096307281463993706121524099555012980816762661575158,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146872822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.146872822' seed=85553493711013531321496305096307281463993706121524099555012980816762661575158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85553493711013531321496305096307281463993706121524099555012980816762661575158 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"10.xbar_smoke_zero_delays.7624923233004865925927996230937189489302106288721163112941458896239108321943","seed":7624923233004865925927996230937189489302106288721163112941458896239108321943,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1415869079 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1415869079' seed=7624923233004865925927996230937189489302106288721163112941458896239108321943 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7624923233004865925927996230937189489302106288721163112941458896239108321943 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"10.xbar_smoke_large_delays.56869773222823947749063012543027766105180341236819496772320913302547919940407","seed":56869773222823947749063012543027766105180341236819496772320913302547919940407,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568970551 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3568970551' seed=56869773222823947749063012543027766105180341236819496772320913302547919940407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56869773222823947749063012543027766105180341236819496772320913302547919940407 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"10.xbar_smoke_slow_rsp.109835041079222389351300765635987147303770278808108294039274985836873945386723","seed":109835041079222389351300765635987147303770278808108294039274985836873945386723,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3211202275 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3211202275' seed=109835041079222389351300765635987147303770278808108294039274985836873945386723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109835041079222389351300765635987147303770278808108294039274985836873945386723 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"10.xbar_random.51574171338790474980150651437654626971552274931618874964347657561592127541781","seed":51574171338790474980150651437654626971552274931618874964347657561592127541781,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841287701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1841287701' seed=51574171338790474980150651437654626971552274931618874964347657561592127541781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51574171338790474980150651437654626971552274931618874964347657561592127541781 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"10.xbar_random_zero_delays.49222492587228296085562705531842940261942290043426895983681751718213672422629","seed":49222492587228296085562705531842940261942290043426895983681751718213672422629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1502006501 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1502006501' seed=49222492587228296085562705531842940261942290043426895983681751718213672422629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49222492587228296085562705531842940261942290043426895983681751718213672422629 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"10.xbar_random_large_delays.92879655159953315667349669349123125795400324707461237994625934708116265519259","seed":92879655159953315667349669349123125795400324707461237994625934708116265519259,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1198235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1198235' seed=92879655159953315667349669349123125795400324707461237994625934708116265519259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92879655159953315667349669349123125795400324707461237994625934708116265519259 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"10.xbar_random_slow_rsp.41869592823010022098256515890703391182185765292401716223623469921224947007615","seed":41869592823010022098256515890703391182185765292401716223623469921224947007615,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1126039679 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1126039679' seed=41869592823010022098256515890703391182185765292401716223623469921224947007615 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=41869592823010022098256515890703391182185765292401716223623469921224947007615 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"10.xbar_access_same_device.94506810521045233493913579606460462203174656265345229434194143759064495031878","seed":94506810521045233493913579606460462203174656265345229434194143759064495031878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3061843526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3061843526' seed=94506810521045233493913579606460462203174656265345229434194143759064495031878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94506810521045233493913579606460462203174656265345229434194143759064495031878 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"10.xbar_access_same_device_slow_rsp.24677395798661399435518009835010712235144698329691981624942999549028879244624","seed":24677395798661399435518009835010712235144698329691981624942999549028879244624,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337035088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3337035088' seed=24677395798661399435518009835010712235144698329691981624942999549028879244624 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24677395798661399435518009835010712235144698329691981624942999549028879244624 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"10.xbar_same_source.76487328420082340810140303346227222223028773812052181836577662611269097429681","seed":76487328420082340810140303346227222223028773812052181836577662611269097429681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2258442929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2258442929' seed=76487328420082340810140303346227222223028773812052181836577662611269097429681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76487328420082340810140303346227222223028773812052181836577662611269097429681 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"10.xbar_error_random.14708364496970086401933094931708930862902612749052521506542051291220449399561","seed":14708364496970086401933094931708930862902612749052521506542051291220449399561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1442026249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1442026249' seed=14708364496970086401933094931708930862902612749052521506542051291220449399561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14708364496970086401933094931708930862902612749052521506542051291220449399561 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"10.xbar_unmapped_addr.90233208177177076168610523201173986897758753167393245964581619441125032916656","seed":90233208177177076168610523201173986897758753167393245964581619441125032916656,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=240055984 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.240055984' seed=90233208177177076168610523201173986897758753167393245964581619441125032916656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90233208177177076168610523201173986897758753167393245964581619441125032916656 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"10.xbar_error_and_unmapped_addr.33555244203628258114233916914027385018895139960242425834973223222728748075770","seed":33555244203628258114233916914027385018895139960242425834973223222728748075770,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988870394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2988870394' seed=33555244203628258114233916914027385018895139960242425834973223222728748075770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33555244203628258114233916914027385018895139960242425834973223222728748075770 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"10.xbar_stress_all.50577521902224780065592164842863179463591980375558952069079902409869402993499","seed":50577521902224780065592164842863179463591980375558952069079902409869402993499,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2358145883 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2358145883' seed=50577521902224780065592164842863179463591980375558952069079902409869402993499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50577521902224780065592164842863179463591980375558952069079902409869402993499 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"10.xbar_stress_all_with_rand_reset.89352125834273744219645746335589412825304965729948679276969250650843528767080","seed":89352125834273744219645746335589412825304965729948679276969250650843528767080,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1077093992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1077093992' seed=89352125834273744219645746335589412825304965729948679276969250650843528767080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89352125834273744219645746335589412825304965729948679276969250650843528767080 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"10.xbar_stress_all_with_error.16712307104746647169893119740185270222847633062941487358776612008888160698205","seed":16712307104746647169893119740185270222847633062941487358776612008888160698205,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752724829 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2752724829' seed=16712307104746647169893119740185270222847633062941487358776612008888160698205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16712307104746647169893119740185270222847633062941487358776612008888160698205 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"10.xbar_stress_all_with_reset_error.54712554019647502346494100496975879464075740383502591171712369873730962869790","seed":54712554019647502346494100496975879464075740383502591171712369873730962869790,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2076855838 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.2076855838' seed=54712554019647502346494100496975879464075740383502591171712369873730962869790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54712554019647502346494100496975879464075740383502591171712369873730962869790 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"11.chip_sw_all_escalation_resets.48318289585810676574798454176172403162488041474467271885895982074349855816839","seed":48318289585810676574798454176172403162488041474467271885895982074349855816839,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4209622151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4209622151' seed=48318289585810676574798454176172403162488041474467271885895982074349855816839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48318289585810676574798454176172403162488041474467271885895982074349855816839 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"11.chip_sw_uart_rand_baudrate.6455269902961800277656731135596930947821840329809029280036685074340343014741","seed":6455269902961800277656731135596930947821840329809029280036685074340343014741,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1257334101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1257334101' seed=6455269902961800277656731135596930947821840329809029280036685074340343014741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6455269902961800277656731135596930947821840329809029280036685074340343014741 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"11.chip_sw_lc_ctrl_transition.89481437606231181225864295196277590835965936828769961821668157500495852655120","seed":89481437606231181225864295196277590835965936828769961821668157500495852655120,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3696153104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.3696153104' seed=89481437606231181225864295196277590835965936828769961821668157500495852655120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89481437606231181225864295196277590835965936828769961821668157500495852655120 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.48594457663406950929489058324478075596975395267093688747232513954013033017934","seed":48594457663406950929489058324478075596975395267093688747232513954013033017934,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.33192806934097712238727411321738279804397410735940179843041003163114629526602","seed":33192806934097712238727411321738279804397410735940179843041003163114629526602,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=516191306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.516191306' seed=33192806934097712238727411321738279804397410735940179843041003163114629526602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33192806934097712238727411321738279804397410735940179843041003163114629526602 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"11.xbar_smoke.30208720282557103343306408419563748182802508756584360986648829449995502556094","seed":30208720282557103343306408419563748182802508756584360986648829449995502556094,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641799102 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.641799102' seed=30208720282557103343306408419563748182802508756584360986648829449995502556094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30208720282557103343306408419563748182802508756584360986648829449995502556094 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"11.xbar_smoke_zero_delays.42818400327397055469087185564639392146689979389234922466111710407785890438368","seed":42818400327397055469087185564639392146689979389234922466111710407785890438368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155704544 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.155704544' seed=42818400327397055469087185564639392146689979389234922466111710407785890438368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42818400327397055469087185564639392146689979389234922466111710407785890438368 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"11.xbar_smoke_large_delays.28355019639186464881250356080888661426453514210806374812476847961320197082976","seed":28355019639186464881250356080888661426453514210806374812476847961320197082976,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165198688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2165198688' seed=28355019639186464881250356080888661426453514210806374812476847961320197082976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28355019639186464881250356080888661426453514210806374812476847961320197082976 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"11.xbar_smoke_slow_rsp.109056385749933898414084499669172797428082658533111035423473667564223733928736","seed":109056385749933898414084499669172797428082658533111035423473667564223733928736,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3784282912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3784282912' seed=109056385749933898414084499669172797428082658533111035423473667564223733928736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109056385749933898414084499669172797428082658533111035423473667564223733928736 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"11.xbar_random.60109424785612978189977473083681450441911319179251921056505235762661068942876","seed":60109424785612978189977473083681450441911319179251921056505235762661068942876,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023009820 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2023009820' seed=60109424785612978189977473083681450441911319179251921056505235762661068942876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60109424785612978189977473083681450441911319179251921056505235762661068942876 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"11.xbar_random_zero_delays.51133273879366786147346704809394764273239307445688275388442071663469661844710","seed":51133273879366786147346704809394764273239307445688275388442071663469661844710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3837326566 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3837326566' seed=51133273879366786147346704809394764273239307445688275388442071663469661844710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51133273879366786147346704809394764273239307445688275388442071663469661844710 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"11.xbar_random_large_delays.105529829911058589506217358864510344060958815847356725667367723771036410282973","seed":105529829911058589506217358864510344060958815847356725667367723771036410282973,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2620359645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2620359645' seed=105529829911058589506217358864510344060958815847356725667367723771036410282973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105529829911058589506217358864510344060958815847356725667367723771036410282973 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"11.xbar_random_slow_rsp.20111265187213814240073696335716153941697951853817946113658459848316409932626","seed":20111265187213814240073696335716153941697951853817946113658459848316409932626,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2614422354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2614422354' seed=20111265187213814240073696335716153941697951853817946113658459848316409932626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20111265187213814240073696335716153941697951853817946113658459848316409932626 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"11.xbar_access_same_device.114472407544234330239245195246527651321241405944506587092219473688372796137399","seed":114472407544234330239245195246527651321241405944506587092219473688372796137399,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2848661431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2848661431' seed=114472407544234330239245195246527651321241405944506587092219473688372796137399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114472407544234330239245195246527651321241405944506587092219473688372796137399 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"11.xbar_access_same_device_slow_rsp.86966855628147492574179289662980160069291712019482398699126419768762637591185","seed":86966855628147492574179289662980160069291712019482398699126419768762637591185,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1357488785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1357488785' seed=86966855628147492574179289662980160069291712019482398699126419768762637591185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86966855628147492574179289662980160069291712019482398699126419768762637591185 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"11.xbar_same_source.61603852864767131551382711448015362193068256862409924035005349328837298076208","seed":61603852864767131551382711448015362193068256862409924035005349328837298076208,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29866544 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.29866544' seed=61603852864767131551382711448015362193068256862409924035005349328837298076208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61603852864767131551382711448015362193068256862409924035005349328837298076208 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"11.xbar_error_random.24698793672968995657463898317058299802048655864015069228769225463960481356110","seed":24698793672968995657463898317058299802048655864015069228769225463960481356110,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=554228046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.554228046' seed=24698793672968995657463898317058299802048655864015069228769225463960481356110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24698793672968995657463898317058299802048655864015069228769225463960481356110 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"11.xbar_unmapped_addr.5156824328460337982179392057036451492116932218347512756397493187210498551750","seed":5156824328460337982179392057036451492116932218347512756397493187210498551750,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2820419526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2820419526' seed=5156824328460337982179392057036451492116932218347512756397493187210498551750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5156824328460337982179392057036451492116932218347512756397493187210498551750 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"11.xbar_error_and_unmapped_addr.42445963460972858499143068440426598099707769816291133948894168378900902114900","seed":42445963460972858499143068440426598099707769816291133948894168378900902114900,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=883488340 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.883488340' seed=42445963460972858499143068440426598099707769816291133948894168378900902114900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42445963460972858499143068440426598099707769816291133948894168378900902114900 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"11.xbar_stress_all.17166138012513297732649764159253652266008838571188536849730923074368946593576","seed":17166138012513297732649764159253652266008838571188536849730923074368946593576,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1377591080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1377591080' seed=17166138012513297732649764159253652266008838571188536849730923074368946593576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17166138012513297732649764159253652266008838571188536849730923074368946593576 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"11.xbar_stress_all_with_rand_reset.1585586103932514963731631737037372662980997058912132073384017195779366325567","seed":1585586103932514963731631737037372662980997058912132073384017195779366325567,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4133752127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.4133752127' seed=1585586103932514963731631737037372662980997058912132073384017195779366325567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1585586103932514963731631737037372662980997058912132073384017195779366325567 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"11.xbar_stress_all_with_error.54287089348640257395558119395453343107450040588859873059142630243780384637473","seed":54287089348640257395558119395453343107450040588859873059142630243780384637473,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037839905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3037839905' seed=54287089348640257395558119395453343107450040588859873059142630243780384637473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54287089348640257395558119395453343107450040588859873059142630243780384637473 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"11.xbar_stress_all_with_reset_error.12239753945391239786541641817581486861269349221652657985726438561132924319866","seed":12239753945391239786541641817581486861269349221652657985726438561132924319866,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2021079162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2021079162' seed=12239753945391239786541641817581486861269349221652657985726438561132924319866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12239753945391239786541641817581486861269349221652657985726438561132924319866 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"12.chip_sw_all_escalation_resets.51859295488994937598560771843444791400278789851650186605040010026066983352365","seed":51859295488994937598560771843444791400278789851650186605040010026066983352365,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2999547949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2999547949' seed=51859295488994937598560771843444791400278789851650186605040010026066983352365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51859295488994937598560771843444791400278789851650186605040010026066983352365 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"12.chip_sw_uart_rand_baudrate.75987459301544942063646985799770972883335554022071495964814520703440199571125","seed":75987459301544942063646985799770972883335554022071495964814520703440199571125,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3689109173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3689109173' seed=75987459301544942063646985799770972883335554022071495964814520703440199571125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75987459301544942063646985799770972883335554022071495964814520703440199571125 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"12.chip_sw_lc_ctrl_transition.14951332601632361919683332872862249222394738339424968306688716739172384354105","seed":14951332601632361919683332872862249222394738339424968306688716739172384354105,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526261049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2526261049' seed=14951332601632361919683332872862249222394738339424968306688716739172384354105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14951332601632361919683332872862249222394738339424968306688716739172384354105 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.96512890976690737515620738363377671915925655154945236020322366032808143086587","seed":96512890976690737515620738363377671915925655154945236020322366032808143086587,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.91602506767565703315128555382108125949823932035008588718887702091846950182258","seed":91602506767565703315128555382108125949823932035008588718887702091846950182258,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446005106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3446005106' seed=91602506767565703315128555382108125949823932035008588718887702091846950182258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91602506767565703315128555382108125949823932035008588718887702091846950182258 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"12.xbar_smoke.11655303939340892056458208877931918926152366414159976554400056118357456708248","seed":11655303939340892056458208877931918926152366414159976554400056118357456708248,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68543128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.68543128' seed=11655303939340892056458208877931918926152366414159976554400056118357456708248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11655303939340892056458208877931918926152366414159976554400056118357456708248 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"12.xbar_smoke_zero_delays.6357456894567833370413831126677183345270417840236111160743749449899658262487","seed":6357456894567833370413831126677183345270417840236111160743749449899658262487,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=743520215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.743520215' seed=6357456894567833370413831126677183345270417840236111160743749449899658262487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6357456894567833370413831126677183345270417840236111160743749449899658262487 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"12.xbar_smoke_large_delays.110204546965881198918080972579340756668020074763219736749324843412320645020451","seed":110204546965881198918080972579340756668020074763219736749324843412320645020451,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3354131235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3354131235' seed=110204546965881198918080972579340756668020074763219736749324843412320645020451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110204546965881198918080972579340756668020074763219736749324843412320645020451 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"12.xbar_smoke_slow_rsp.69799767783212353583272505057509315839331412476481404369469115574194942547786","seed":69799767783212353583272505057509315839331412476481404369469115574194942547786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3180631882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3180631882' seed=69799767783212353583272505057509315839331412476481404369469115574194942547786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69799767783212353583272505057509315839331412476481404369469115574194942547786 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"12.xbar_random.72489079469853746830598520090609368047907853374208446458722374371085091139691","seed":72489079469853746830598520090609368047907853374208446458722374371085091139691,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505109611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2505109611' seed=72489079469853746830598520090609368047907853374208446458722374371085091139691 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72489079469853746830598520090609368047907853374208446458722374371085091139691 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"12.xbar_random_zero_delays.59298565292010585774614100633513369424995018633784462158318639040667870105766","seed":59298565292010585774614100633513369424995018633784462158318639040667870105766,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2825195686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2825195686' seed=59298565292010585774614100633513369424995018633784462158318639040667870105766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59298565292010585774614100633513369424995018633784462158318639040667870105766 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"12.xbar_random_large_delays.83934455689140543390430544756478982218465215045010719761196994254665979309299","seed":83934455689140543390430544756478982218465215045010719761196994254665979309299,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1193848051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1193848051' seed=83934455689140543390430544756478982218465215045010719761196994254665979309299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83934455689140543390430544756478982218465215045010719761196994254665979309299 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"12.xbar_random_slow_rsp.115230686587578604914230386909975569080484351568610535610492974202959635153454","seed":115230686587578604914230386909975569080484351568610535610492974202959635153454,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560623150 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2560623150' seed=115230686587578604914230386909975569080484351568610535610492974202959635153454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=115230686587578604914230386909975569080484351568610535610492974202959635153454 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"12.xbar_access_same_device.50655491126969742100842389465819207697929018603993073272235324086928333132494","seed":50655491126969742100842389465819207697929018603993073272235324086928333132494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3815822030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3815822030' seed=50655491126969742100842389465819207697929018603993073272235324086928333132494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50655491126969742100842389465819207697929018603993073272235324086928333132494 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"12.xbar_access_same_device_slow_rsp.92442090685021610198789493719179980458192866953813262962486608087224372673245","seed":92442090685021610198789493719179980458192866953813262962486608087224372673245,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=71809757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.71809757' seed=92442090685021610198789493719179980458192866953813262962486608087224372673245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92442090685021610198789493719179980458192866953813262962486608087224372673245 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"12.xbar_same_source.92959475631012535966467259148579713215850401477970308981370284451107029545992","seed":92959475631012535966467259148579713215850401477970308981370284451107029545992,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1679717384 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1679717384' seed=92959475631012535966467259148579713215850401477970308981370284451107029545992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92959475631012535966467259148579713215850401477970308981370284451107029545992 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"12.xbar_error_random.19247276364978793602886403779874643745465939154270542856544485619668957060093","seed":19247276364978793602886403779874643745465939154270542856544485619668957060093,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1101061117 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1101061117' seed=19247276364978793602886403779874643745465939154270542856544485619668957060093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19247276364978793602886403779874643745465939154270542856544485619668957060093 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"12.xbar_unmapped_addr.81263317515757242314435430595157587742507584347275767692483503579488565632165","seed":81263317515757242314435430595157587742507584347275767692483503579488565632165,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1699519653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1699519653' seed=81263317515757242314435430595157587742507584347275767692483503579488565632165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81263317515757242314435430595157587742507584347275767692483503579488565632165 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"12.xbar_error_and_unmapped_addr.75978181292693965678627116255071349414262274427386369681200377750624436004225","seed":75978181292693965678627116255071349414262274427386369681200377750624436004225,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2784011649 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2784011649' seed=75978181292693965678627116255071349414262274427386369681200377750624436004225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75978181292693965678627116255071349414262274427386369681200377750624436004225 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"12.xbar_stress_all.74760572416528016122599562348724500788275326259261062166954786936383726880911","seed":74760572416528016122599562348724500788275326259261062166954786936383726880911,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=692521103 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.692521103' seed=74760572416528016122599562348724500788275326259261062166954786936383726880911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74760572416528016122599562348724500788275326259261062166954786936383726880911 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"12.xbar_stress_all_with_rand_reset.61260833537360187093316315713617651359442436882110730466407853296049344857426","seed":61260833537360187093316315713617651359442436882110730466407853296049344857426,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=246269266 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.246269266' seed=61260833537360187093316315713617651359442436882110730466407853296049344857426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61260833537360187093316315713617651359442436882110730466407853296049344857426 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"12.xbar_stress_all_with_error.109732749622716985688969412675396487106384099790635341191951207135672312656245","seed":109732749622716985688969412675396487106384099790635341191951207135672312656245,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1130230133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1130230133' seed=109732749622716985688969412675396487106384099790635341191951207135672312656245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109732749622716985688969412675396487106384099790635341191951207135672312656245 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"12.xbar_stress_all_with_reset_error.61818433651397136141409982076642968317139383693944633806431100251664012596678","seed":61818433651397136141409982076642968317139383693944633806431100251664012596678,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=196662726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.196662726' seed=61818433651397136141409982076642968317139383693944633806431100251664012596678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61818433651397136141409982076642968317139383693944633806431100251664012596678 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"13.chip_sw_all_escalation_resets.5896909202579677397249727072608311440571124841398263507499322927608199535408","seed":5896909202579677397249727072608311440571124841398263507499322927608199535408,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1689410352 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1689410352' seed=5896909202579677397249727072608311440571124841398263507499322927608199535408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5896909202579677397249727072608311440571124841398263507499322927608199535408 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"13.chip_sw_uart_rand_baudrate.60019226660890148189394616577322059383841227847870506951828746239807717276152","seed":60019226660890148189394616577322059383841227847870506951828746239807717276152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2517531128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2517531128' seed=60019226660890148189394616577322059383841227847870506951828746239807717276152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60019226660890148189394616577322059383841227847870506951828746239807717276152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"13.chip_sw_lc_ctrl_transition.12700901039802445473366814664099216326071726585250610100129914624256949226851","seed":12700901039802445473366814664099216326071726585250610100129914624256949226851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877530467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.877530467' seed=12700901039802445473366814664099216326071726585250610100129914624256949226851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12700901039802445473366814664099216326071726585250610100129914624256949226851 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.84998066342421583057992002106137811997447911948136619782532999098103657621000","seed":84998066342421583057992002106137811997447911948136619782532999098103657621000,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.61591234711187649355505350580980567669105886505421226633706554176295929859607","seed":61591234711187649355505350580980567669105886505421226633706554176295929859607,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007270423 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3007270423' seed=61591234711187649355505350580980567669105886505421226633706554176295929859607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61591234711187649355505350580980567669105886505421226633706554176295929859607 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"13.xbar_smoke.6365112161206035143419738578797762361476402236732335861809707940945513758930","seed":6365112161206035143419738578797762361476402236732335861809707940945513758930,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446751442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3446751442' seed=6365112161206035143419738578797762361476402236732335861809707940945513758930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6365112161206035143419738578797762361476402236732335861809707940945513758930 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"13.xbar_smoke_zero_delays.42352001926396209769152802639452520257063389043803022704053691090801890226737","seed":42352001926396209769152802639452520257063389043803022704053691090801890226737,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743319601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1743319601' seed=42352001926396209769152802639452520257063389043803022704053691090801890226737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42352001926396209769152802639452520257063389043803022704053691090801890226737 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"13.xbar_smoke_large_delays.64022783404095519082611550061253979296026724452957060427975364289147900144667","seed":64022783404095519082611550061253979296026724452957060427975364289147900144667,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799315995 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2799315995' seed=64022783404095519082611550061253979296026724452957060427975364289147900144667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64022783404095519082611550061253979296026724452957060427975364289147900144667 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"13.xbar_smoke_slow_rsp.66892717885283522971908832149998755993258943045734650759227197642413378707222","seed":66892717885283522971908832149998755993258943045734650759227197642413378707222,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=101261078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.101261078' seed=66892717885283522971908832149998755993258943045734650759227197642413378707222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66892717885283522971908832149998755993258943045734650759227197642413378707222 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"13.xbar_random.75356036352367543136316251965319838118430819438060953948625569649940303060083","seed":75356036352367543136316251965319838118430819438060953948625569649940303060083,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2394561651 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2394561651' seed=75356036352367543136316251965319838118430819438060953948625569649940303060083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75356036352367543136316251965319838118430819438060953948625569649940303060083 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"13.xbar_random_zero_delays.53401736678504822458613457221259736428280636954271474794181648604694552417006","seed":53401736678504822458613457221259736428280636954271474794181648604694552417006,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2321978094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2321978094' seed=53401736678504822458613457221259736428280636954271474794181648604694552417006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53401736678504822458613457221259736428280636954271474794181648604694552417006 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"13.xbar_random_large_delays.71720961527801548288093699943011889290130207861785888259241000730343589793984","seed":71720961527801548288093699943011889290130207861785888259241000730343589793984,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1329582272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1329582272' seed=71720961527801548288093699943011889290130207861785888259241000730343589793984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71720961527801548288093699943011889290130207861785888259241000730343589793984 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"13.xbar_random_slow_rsp.11885267042522344446582139858816797170392152189348280869309130896883107468302","seed":11885267042522344446582139858816797170392152189348280869309130896883107468302,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78091278 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.78091278' seed=11885267042522344446582139858816797170392152189348280869309130896883107468302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11885267042522344446582139858816797170392152189348280869309130896883107468302 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"13.xbar_access_same_device.8672615679462164324104551848308765982727939224624638931332224287022038645584","seed":8672615679462164324104551848308765982727939224624638931332224287022038645584,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=669514576 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.669514576' seed=8672615679462164324104551848308765982727939224624638931332224287022038645584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8672615679462164324104551848308765982727939224624638931332224287022038645584 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"13.xbar_access_same_device_slow_rsp.85605053590449336965740704713594608873589775035748551263210636041581163674762","seed":85605053590449336965740704713594608873589775035748551263210636041581163674762,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3909844106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.3909844106' seed=85605053590449336965740704713594608873589775035748551263210636041581163674762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85605053590449336965740704713594608873589775035748551263210636041581163674762 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"13.xbar_same_source.32416566913008580055139772391467036278468771692084828086937902719293381906985","seed":32416566913008580055139772391467036278468771692084828086937902719293381906985,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1890554409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1890554409' seed=32416566913008580055139772391467036278468771692084828086937902719293381906985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32416566913008580055139772391467036278468771692084828086937902719293381906985 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"13.xbar_error_random.49555325633887363847934487688004000229593434766416724781428613204866956868943","seed":49555325633887363847934487688004000229593434766416724781428613204866956868943,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3134274895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3134274895' seed=49555325633887363847934487688004000229593434766416724781428613204866956868943 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49555325633887363847934487688004000229593434766416724781428613204866956868943 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"13.xbar_unmapped_addr.63543087355275662787382408794316841632745734447841615400084604549764673909993","seed":63543087355275662787382408794316841632745734447841615400084604549764673909993,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1245656297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1245656297' seed=63543087355275662787382408794316841632745734447841615400084604549764673909993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63543087355275662787382408794316841632745734447841615400084604549764673909993 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"13.xbar_error_and_unmapped_addr.73692165559339014992476484798428031395678207859300767938431043789488178464557","seed":73692165559339014992476484798428031395678207859300767938431043789488178464557,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046611757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1046611757' seed=73692165559339014992476484798428031395678207859300767938431043789488178464557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73692165559339014992476484798428031395678207859300767938431043789488178464557 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"13.xbar_stress_all.68074349596118897312751961095602542917671564865453025779395375081113745438692","seed":68074349596118897312751961095602542917671564865453025779395375081113745438692,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1542272996 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1542272996' seed=68074349596118897312751961095602542917671564865453025779395375081113745438692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68074349596118897312751961095602542917671564865453025779395375081113745438692 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"13.xbar_stress_all_with_rand_reset.63220523862330326195275658872535767611959057412796666845516266115121785734057","seed":63220523862330326195275658872535767611959057412796666845516266115121785734057,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2367030185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2367030185' seed=63220523862330326195275658872535767611959057412796666845516266115121785734057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63220523862330326195275658872535767611959057412796666845516266115121785734057 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"13.xbar_stress_all_with_error.86505432587671612044958328594987245009026185125272168584279049661034948749679","seed":86505432587671612044958328594987245009026185125272168584279049661034948749679,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1850239343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1850239343' seed=86505432587671612044958328594987245009026185125272168584279049661034948749679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86505432587671612044958328594987245009026185125272168584279049661034948749679 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"13.xbar_stress_all_with_reset_error.84742792635126576270187959478275388154854509433045791662057437387575749387252","seed":84742792635126576270187959478275388154854509433045791662057437387575749387252,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1069163508 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1069163508' seed=84742792635126576270187959478275388154854509433045791662057437387575749387252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84742792635126576270187959478275388154854509433045791662057437387575749387252 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"14.chip_sw_all_escalation_resets.6462266533316014510180142526721554519534678851539404107409326710029981916264","seed":6462266533316014510180142526721554519534678851539404107409326710029981916264,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1497701480 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1497701480' seed=6462266533316014510180142526721554519534678851539404107409326710029981916264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6462266533316014510180142526721554519534678851539404107409326710029981916264 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"14.chip_sw_uart_rand_baudrate.28840061622365459465200698183541121463235611409109717056277448873918493378158","seed":28840061622365459465200698183541121463235611409109717056277448873918493378158,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=602949230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.602949230' seed=28840061622365459465200698183541121463235611409109717056277448873918493378158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28840061622365459465200698183541121463235611409109717056277448873918493378158 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"14.chip_sw_lc_ctrl_transition.56255053057001195321863745319122565711053164211853249415719154127779679780036","seed":56255053057001195321863745319122565711053164211853249415719154127779679780036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest run_opts='+sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2383494340 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2383494340' seed=56255053057001195321863745319122565711053164211853249415719154127779679780036 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56255053057001195321863745319122565711053164211853249415719154127779679780036 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:lc_ctrl_transition_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_lc_ctrl_transition_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.88214244588653888019443767840872225002668359342739102166745084640991963756583","seed":88214244588653888019443767840872225002668359342739102166745084640991963756583,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.26011814982881902985467635339654087798404755251193400592786151974106990400170","seed":26011814982881902985467635339654087798404755251193400592786151974106990400170,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557863594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.557863594' seed=26011814982881902985467635339654087798404755251193400592786151974106990400170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26011814982881902985467635339654087798404755251193400592786151974106990400170 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"14.xbar_smoke.361245213676429223198407008445529381780830930531633876028635759864062212764","seed":361245213676429223198407008445529381780830930531633876028635759864062212764,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1196489372 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1196489372' seed=361245213676429223198407008445529381780830930531633876028635759864062212764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=361245213676429223198407008445529381780830930531633876028635759864062212764 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"14.xbar_smoke_zero_delays.51483907236926500888982878007964433294909369700403975734206544885237781865515","seed":51483907236926500888982878007964433294909369700403975734206544885237781865515,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=160408619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.160408619' seed=51483907236926500888982878007964433294909369700403975734206544885237781865515 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51483907236926500888982878007964433294909369700403975734206544885237781865515 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"14.xbar_smoke_large_delays.105043329540209226529274596457830541011006236300287213853630157624195086555443","seed":105043329540209226529274596457830541011006236300287213853630157624195086555443,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2489063731 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2489063731' seed=105043329540209226529274596457830541011006236300287213853630157624195086555443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105043329540209226529274596457830541011006236300287213853630157624195086555443 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"14.xbar_smoke_slow_rsp.69020525795260239772222412016203290725132645885808031215210858972763194462984","seed":69020525795260239772222412016203290725132645885808031215210858972763194462984,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2639860488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2639860488' seed=69020525795260239772222412016203290725132645885808031215210858972763194462984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69020525795260239772222412016203290725132645885808031215210858972763194462984 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"14.xbar_random.9142899213970523453728468579709851585045133193552750435410377151445644369574","seed":9142899213970523453728468579709851585045133193552750435410377151445644369574,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1714445990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1714445990' seed=9142899213970523453728468579709851585045133193552750435410377151445644369574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9142899213970523453728468579709851585045133193552750435410377151445644369574 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"14.xbar_random_zero_delays.75226520872832821940280354749996592832799572259956795795649536397255941538831","seed":75226520872832821940280354749996592832799572259956795795649536397255941538831,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=759677967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.759677967' seed=75226520872832821940280354749996592832799572259956795795649536397255941538831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75226520872832821940280354749996592832799572259956795795649536397255941538831 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"14.xbar_random_large_delays.111883716109816545359632274020262339900521605692948740386378773724991385570670","seed":111883716109816545359632274020262339900521605692948740386378773724991385570670,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=474549614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.474549614' seed=111883716109816545359632274020262339900521605692948740386378773724991385570670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111883716109816545359632274020262339900521605692948740386378773724991385570670 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"14.xbar_random_slow_rsp.15123735422721366011723363237203681541587291304780309231087337662272095792983","seed":15123735422721366011723363237203681541587291304780309231087337662272095792983,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=548286295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.548286295' seed=15123735422721366011723363237203681541587291304780309231087337662272095792983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15123735422721366011723363237203681541587291304780309231087337662272095792983 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"14.xbar_access_same_device.109537560474845989473404222843679661360861862337428118016457193681987700338784","seed":109537560474845989473404222843679661360861862337428118016457193681987700338784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3989385312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3989385312' seed=109537560474845989473404222843679661360861862337428118016457193681987700338784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109537560474845989473404222843679661360861862337428118016457193681987700338784 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"14.xbar_access_same_device_slow_rsp.3255300195708438889153921793455276198604278509874123218708027840651253809338","seed":3255300195708438889153921793455276198604278509874123218708027840651253809338,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028399802 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.4028399802' seed=3255300195708438889153921793455276198604278509874123218708027840651253809338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3255300195708438889153921793455276198604278509874123218708027840651253809338 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"14.xbar_same_source.75875403507408019658758226847302142534141114445096256178544256887952879964058","seed":75875403507408019658758226847302142534141114445096256178544256887952879964058,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708628378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.708628378' seed=75875403507408019658758226847302142534141114445096256178544256887952879964058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75875403507408019658758226847302142534141114445096256178544256887952879964058 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"14.xbar_error_random.13581265525320159055645557866976049944502726532934262805052621908310712306338","seed":13581265525320159055645557866976049944502726532934262805052621908310712306338,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2320419490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2320419490' seed=13581265525320159055645557866976049944502726532934262805052621908310712306338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13581265525320159055645557866976049944502726532934262805052621908310712306338 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"14.xbar_unmapped_addr.70554442942242049534855596609641946615321344256154922168611033181939037645770","seed":70554442942242049534855596609641946615321344256154922168611033181939037645770,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073228746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1073228746' seed=70554442942242049534855596609641946615321344256154922168611033181939037645770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70554442942242049534855596609641946615321344256154922168611033181939037645770 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"14.xbar_error_and_unmapped_addr.93262217897615929986384012403510423311784269093074263463218935391311364728190","seed":93262217897615929986384012403510423311784269093074263463218935391311364728190,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4251559294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.4251559294' seed=93262217897615929986384012403510423311784269093074263463218935391311364728190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93262217897615929986384012403510423311784269093074263463218935391311364728190 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"14.xbar_stress_all.24202329019342266023537274108332854775029948876308774480974480634112741928022","seed":24202329019342266023537274108332854775029948876308774480974480634112741928022,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=90369110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.90369110' seed=24202329019342266023537274108332854775029948876308774480974480634112741928022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24202329019342266023537274108332854775029948876308774480974480634112741928022 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"14.xbar_stress_all_with_rand_reset.69696078242559170435836253574436879681568049653156630601195400534673553632274","seed":69696078242559170435836253574436879681568049653156630601195400534673553632274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3593481234 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.3593481234' seed=69696078242559170435836253574436879681568049653156630601195400534673553632274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69696078242559170435836253574436879681568049653156630601195400534673553632274 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"14.xbar_stress_all_with_error.87005866984114483782060884371468561793362557142102844191712010735955856073334","seed":87005866984114483782060884371468561793362557142102844191712010735955856073334,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3869254262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3869254262' seed=87005866984114483782060884371468561793362557142102844191712010735955856073334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87005866984114483782060884371468561793362557142102844191712010735955856073334 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"14.xbar_stress_all_with_reset_error.94061976194936699121323079926603833400186509058101646764979011614972558911982","seed":94061976194936699121323079926603833400186509058101646764979011614972558911982,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1616849390 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1616849390' seed=94061976194936699121323079926603833400186509058101646764979011614972558911982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94061976194936699121323079926603833400186509058101646764979011614972558911982 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"15.chip_sw_all_escalation_resets.28863127980203850193774251814220535758138399170562668257502321407039277835755","seed":28863127980203850193774251814220535758138399170562668257502321407039277835755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100241899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2100241899' seed=28863127980203850193774251814220535758138399170562668257502321407039277835755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28863127980203850193774251814220535758138399170562668257502321407039277835755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"15.chip_sw_uart_rand_baudrate.44905129962762132924929155664925537789372680167042404623851428928090823323293","seed":44905129962762132924929155664925537789372680167042404623851428928090823323293,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491543197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2491543197' seed=44905129962762132924929155664925537789372680167042404623851428928090823323293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44905129962762132924929155664925537789372680167042404623851428928090823323293 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.22432888578015508040852737011442841158730515187787177781623708886558899302131","seed":22432888578015508040852737011442841158730515187787177781623708886558899302131,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.32028987223177065427593149619563871607330446342524005846023257400323947603182","seed":32028987223177065427593149619563871607330446342524005846023257400323947603182,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1572054254 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1572054254' seed=32028987223177065427593149619563871607330446342524005846023257400323947603182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32028987223177065427593149619563871607330446342524005846023257400323947603182 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"15.xbar_smoke.65992140004228095779942629470303035152108576738485717968504281187321087143798","seed":65992140004228095779942629470303035152108576738485717968504281187321087143798,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1134440310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1134440310' seed=65992140004228095779942629470303035152108576738485717968504281187321087143798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65992140004228095779942629470303035152108576738485717968504281187321087143798 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"15.xbar_smoke_zero_delays.95058230803324493878700464466681548606147695711583520362613016547525844579642","seed":95058230803324493878700464466681548606147695711583520362613016547525844579642,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3633624378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3633624378' seed=95058230803324493878700464466681548606147695711583520362613016547525844579642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95058230803324493878700464466681548606147695711583520362613016547525844579642 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"15.xbar_smoke_large_delays.62907864016945122773259428357910631592617470446423168081730719115910511031057","seed":62907864016945122773259428357910631592617470446423168081730719115910511031057,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2451534609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2451534609' seed=62907864016945122773259428357910631592617470446423168081730719115910511031057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62907864016945122773259428357910631592617470446423168081730719115910511031057 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"15.xbar_smoke_slow_rsp.77803132342890951879895587787759288072436153148417170798848388960214645854956","seed":77803132342890951879895587787759288072436153148417170798848388960214645854956,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706676972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1706676972' seed=77803132342890951879895587787759288072436153148417170798848388960214645854956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77803132342890951879895587787759288072436153148417170798848388960214645854956 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"15.xbar_random.82421823934426647875377114456646325310378444970598289565357439254924702174786","seed":82421823934426647875377114456646325310378444970598289565357439254924702174786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3477786178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3477786178' seed=82421823934426647875377114456646325310378444970598289565357439254924702174786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82421823934426647875377114456646325310378444970598289565357439254924702174786 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"15.xbar_random_zero_delays.88830167291967206443879170225883351030455565036648301593002569125505046430932","seed":88830167291967206443879170225883351030455565036648301593002569125505046430932,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=894452948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.894452948' seed=88830167291967206443879170225883351030455565036648301593002569125505046430932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88830167291967206443879170225883351030455565036648301593002569125505046430932 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"15.xbar_random_large_delays.41393161049780721276249823532558482641304345059660309273652410273163365520957","seed":41393161049780721276249823532558482641304345059660309273652410273163365520957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2744587837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2744587837' seed=41393161049780721276249823532558482641304345059660309273652410273163365520957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=41393161049780721276249823532558482641304345059660309273652410273163365520957 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"15.xbar_random_slow_rsp.48654774298658901572992818085534866415788556230681296763545514540060797427063","seed":48654774298658901572992818085534866415788556230681296763545514540060797427063,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1028513143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1028513143' seed=48654774298658901572992818085534866415788556230681296763545514540060797427063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48654774298658901572992818085534866415788556230681296763545514540060797427063 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"15.xbar_access_same_device.65215266455052773842772022902793057887411909102306801287503836854135595916320","seed":65215266455052773842772022902793057887411909102306801287503836854135595916320,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=350149664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.350149664' seed=65215266455052773842772022902793057887411909102306801287503836854135595916320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65215266455052773842772022902793057887411909102306801287503836854135595916320 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"15.xbar_access_same_device_slow_rsp.109724491167240808648054353789106727382406140414498668780349710229846428854343","seed":109724491167240808648054353789106727382406140414498668780349710229846428854343,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088689223 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.3088689223' seed=109724491167240808648054353789106727382406140414498668780349710229846428854343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109724491167240808648054353789106727382406140414498668780349710229846428854343 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"15.xbar_same_source.97866770264171045752996728111610117019628843044514322376442311004276447195044","seed":97866770264171045752996728111610117019628843044514322376442311004276447195044,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=753610660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.753610660' seed=97866770264171045752996728111610117019628843044514322376442311004276447195044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97866770264171045752996728111610117019628843044514322376442311004276447195044 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"15.xbar_error_random.64048506822849402610177199656353971441530600689603919955301619400541023651971","seed":64048506822849402610177199656353971441530600689603919955301619400541023651971,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748991619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2748991619' seed=64048506822849402610177199656353971441530600689603919955301619400541023651971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64048506822849402610177199656353971441530600689603919955301619400541023651971 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"15.xbar_unmapped_addr.52731978652526305539023110533242345853676175925867943062224160536687566934147","seed":52731978652526305539023110533242345853676175925867943062224160536687566934147,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3038269571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3038269571' seed=52731978652526305539023110533242345853676175925867943062224160536687566934147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52731978652526305539023110533242345853676175925867943062224160536687566934147 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"15.xbar_error_and_unmapped_addr.94748001314039176901798633427828747350405760317306693654842387838876552909803","seed":94748001314039176901798633427828747350405760317306693654842387838876552909803,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4088255467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4088255467' seed=94748001314039176901798633427828747350405760317306693654842387838876552909803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94748001314039176901798633427828747350405760317306693654842387838876552909803 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"15.xbar_stress_all.27801213850409140303852077592081904716570094139855259914670290445237786453973","seed":27801213850409140303852077592081904716570094139855259914670290445237786453973,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=317663189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.317663189' seed=27801213850409140303852077592081904716570094139855259914670290445237786453973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27801213850409140303852077592081904716570094139855259914670290445237786453973 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"15.xbar_stress_all_with_rand_reset.37271849839101787628462138507796832456464789507520092499827351056998647231117","seed":37271849839101787628462138507796832456464789507520092499827351056998647231117,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184475277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2184475277' seed=37271849839101787628462138507796832456464789507520092499827351056998647231117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37271849839101787628462138507796832456464789507520092499827351056998647231117 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"15.xbar_stress_all_with_error.77926143319599090261599317490449933022117374121713372890312437324978147749838","seed":77926143319599090261599317490449933022117374121713372890312437324978147749838,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2080829390 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2080829390' seed=77926143319599090261599317490449933022117374121713372890312437324978147749838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77926143319599090261599317490449933022117374121713372890312437324978147749838 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"15.xbar_stress_all_with_reset_error.60336978321838988006052363513350960235082932405577292364735930359512119768617","seed":60336978321838988006052363513350960235082932405577292364735930359512119768617,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4176082473 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.4176082473' seed=60336978321838988006052363513350960235082932405577292364735930359512119768617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60336978321838988006052363513350960235082932405577292364735930359512119768617 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"16.chip_sw_all_escalation_resets.82246542994324078947043708961666395269663817913551018352926289251668543087898","seed":82246542994324078947043708961666395269663817913551018352926289251668543087898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2884314394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2884314394' seed=82246542994324078947043708961666395269663817913551018352926289251668543087898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82246542994324078947043708961666395269663817913551018352926289251668543087898 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"16.chip_sw_uart_rand_baudrate.30071427194895078276492082400991837830393839707603745835170400323147171616112","seed":30071427194895078276492082400991837830393839707603745835170400323147171616112,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332387696 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.332387696' seed=30071427194895078276492082400991837830393839707603745835170400323147171616112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30071427194895078276492082400991837830393839707603745835170400323147171616112 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.30029553206857532946766202895105815483690460533857149120821348204343279364125","seed":30029553206857532946766202895105815483690460533857149120821348204343279364125,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.84961599471557274849214607004393363718392243463237676816503589213272202525921","seed":84961599471557274849214607004393363718392243463237676816503589213272202525921,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2584722657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2584722657' seed=84961599471557274849214607004393363718392243463237676816503589213272202525921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84961599471557274849214607004393363718392243463237676816503589213272202525921 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"16.xbar_smoke.10511522812629644376548088611527580478658863111873546248864490063565787872484","seed":10511522812629644376548088611527580478658863111873546248864490063565787872484,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1520811236 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1520811236' seed=10511522812629644376548088611527580478658863111873546248864490063565787872484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10511522812629644376548088611527580478658863111873546248864490063565787872484 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"16.xbar_smoke_zero_delays.38209583593852041858907209103253759218517866818944042879660194287572135858929","seed":38209583593852041858907209103253759218517866818944042879660194287572135858929,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3634254577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3634254577' seed=38209583593852041858907209103253759218517866818944042879660194287572135858929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38209583593852041858907209103253759218517866818944042879660194287572135858929 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"16.xbar_smoke_large_delays.103752471894722478196772531786842145659550351089396783782934212145855284886687","seed":103752471894722478196772531786842145659550351089396783782934212145855284886687,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1533787295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1533787295' seed=103752471894722478196772531786842145659550351089396783782934212145855284886687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103752471894722478196772531786842145659550351089396783782934212145855284886687 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"16.xbar_smoke_slow_rsp.11336509062495717825209609748833728338399892865182833018841877152472679460419","seed":11336509062495717825209609748833728338399892865182833018841877152472679460419,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1806577219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1806577219' seed=11336509062495717825209609748833728338399892865182833018841877152472679460419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11336509062495717825209609748833728338399892865182833018841877152472679460419 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"16.xbar_random.55554015349512071741373061202205445967041317046797767552319431676266156124711","seed":55554015349512071741373061202205445967041317046797767552319431676266156124711,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2882529831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2882529831' seed=55554015349512071741373061202205445967041317046797767552319431676266156124711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55554015349512071741373061202205445967041317046797767552319431676266156124711 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"16.xbar_random_zero_delays.48946939898206193908256140519752538821662625250502202054657731140879313188196","seed":48946939898206193908256140519752538821662625250502202054657731140879313188196,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2409543012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2409543012' seed=48946939898206193908256140519752538821662625250502202054657731140879313188196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48946939898206193908256140519752538821662625250502202054657731140879313188196 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"16.xbar_random_large_delays.48129833373185857359385568025272419434656192145186610107756854341969415717697","seed":48129833373185857359385568025272419434656192145186610107756854341969415717697,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1978352449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1978352449' seed=48129833373185857359385568025272419434656192145186610107756854341969415717697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48129833373185857359385568025272419434656192145186610107756854341969415717697 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"16.xbar_random_slow_rsp.27472976550013889130264485621527295057782668365164293819311006094675254498034","seed":27472976550013889130264485621527295057782668365164293819311006094675254498034,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3807171314 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3807171314' seed=27472976550013889130264485621527295057782668365164293819311006094675254498034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27472976550013889130264485621527295057782668365164293819311006094675254498034 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"16.xbar_access_same_device.1564331457607104317090302318843191217198678508987584170808119134757747216086","seed":1564331457607104317090302318843191217198678508987584170808119134757747216086,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1036832470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1036832470' seed=1564331457607104317090302318843191217198678508987584170808119134757747216086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1564331457607104317090302318843191217198678508987584170808119134757747216086 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"16.xbar_access_same_device_slow_rsp.24683194960512007625345919094772600297942477388932447396813156636448672278912","seed":24683194960512007625345919094772600297942477388932447396813156636448672278912,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776014720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3776014720' seed=24683194960512007625345919094772600297942477388932447396813156636448672278912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24683194960512007625345919094772600297942477388932447396813156636448672278912 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"16.xbar_same_source.102084802724435142173885874584550600370468360028701640115910946029225483420575","seed":102084802724435142173885874584550600370468360028701640115910946029225483420575,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1265353631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1265353631' seed=102084802724435142173885874584550600370468360028701640115910946029225483420575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102084802724435142173885874584550600370468360028701640115910946029225483420575 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"16.xbar_error_random.100009782139584645351486156885368528315820888449213192387674748652557399205343","seed":100009782139584645351486156885368528315820888449213192387674748652557399205343,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=421504479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.421504479' seed=100009782139584645351486156885368528315820888449213192387674748652557399205343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100009782139584645351486156885368528315820888449213192387674748652557399205343 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"16.xbar_unmapped_addr.77731530851078631372498103639243233185085228195419196583935404052960963229039","seed":77731530851078631372498103639243233185085228195419196583935404052960963229039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289699183 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.289699183' seed=77731530851078631372498103639243233185085228195419196583935404052960963229039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77731530851078631372498103639243233185085228195419196583935404052960963229039 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"16.xbar_error_and_unmapped_addr.93480910648396977026502345839097271197990574750587307934162662302816826717888","seed":93480910648396977026502345839097271197990574750587307934162662302816826717888,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602544320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3602544320' seed=93480910648396977026502345839097271197990574750587307934162662302816826717888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93480910648396977026502345839097271197990574750587307934162662302816826717888 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"16.xbar_stress_all.45040463521680945420885760116720282518378321447244221651818513631644282946521","seed":45040463521680945420885760116720282518378321447244221651818513631644282946521,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=843744217 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.843744217' seed=45040463521680945420885760116720282518378321447244221651818513631644282946521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45040463521680945420885760116720282518378321447244221651818513631644282946521 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"16.xbar_stress_all_with_rand_reset.48164357376778079251537178444990712652750778409205540234020980637072709157148","seed":48164357376778079251537178444990712652750778409205540234020980637072709157148,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=175669532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.175669532' seed=48164357376778079251537178444990712652750778409205540234020980637072709157148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48164357376778079251537178444990712652750778409205540234020980637072709157148 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"16.xbar_stress_all_with_error.103054056691877512914007905362028156596591064312571988413775519119965070402953","seed":103054056691877512914007905362028156596591064312571988413775519119965070402953,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1437705609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1437705609' seed=103054056691877512914007905362028156596591064312571988413775519119965070402953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103054056691877512914007905362028156596591064312571988413775519119965070402953 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"16.xbar_stress_all_with_reset_error.98321277977339084511251430484667116531842860249613555613636079361367519395026","seed":98321277977339084511251430484667116531842860249613555613636079361367519395026,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=208796882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.208796882' seed=98321277977339084511251430484667116531842860249613555613636079361367519395026 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98321277977339084511251430484667116531842860249613555613636079361367519395026 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"17.chip_sw_all_escalation_resets.27250233050110970278086114833229247790639760371915065361105535124714420725079","seed":27250233050110970278086114833229247790639760371915065361105535124714420725079,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=574121303 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.574121303' seed=27250233050110970278086114833229247790639760371915065361105535124714420725079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27250233050110970278086114833229247790639760371915065361105535124714420725079 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"17.chip_sw_uart_rand_baudrate.113975143330582255071324223850399580972261800407028928156837888237475388013635","seed":113975143330582255071324223850399580972261800407028928156837888237475388013635,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3492101187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3492101187' seed=113975143330582255071324223850399580972261800407028928156837888237475388013635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113975143330582255071324223850399580972261800407028928156837888237475388013635 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3696058966470558232039889885077264823005793183207330035601757782975780753292","seed":3696058966470558232039889885077264823005793183207330035601757782975780753292,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.59887600068015338623707237442132727579149278094805632120172249022895810792402","seed":59887600068015338623707237442132727579149278094805632120172249022895810792402,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1877855186 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1877855186' seed=59887600068015338623707237442132727579149278094805632120172249022895810792402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59887600068015338623707237442132727579149278094805632120172249022895810792402 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"17.xbar_smoke.51059863714328877541166338420867922341549592774164117521710678307363812821523","seed":51059863714328877541166338420867922341549592774164117521710678307363812821523,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=613435923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.613435923' seed=51059863714328877541166338420867922341549592774164117521710678307363812821523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51059863714328877541166338420867922341549592774164117521710678307363812821523 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"17.xbar_smoke_zero_delays.113490029056826603568171141770492363376573481483473582772788056592706821100462","seed":113490029056826603568171141770492363376573481483473582772788056592706821100462,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1665340334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1665340334' seed=113490029056826603568171141770492363376573481483473582772788056592706821100462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113490029056826603568171141770492363376573481483473582772788056592706821100462 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"17.xbar_smoke_large_delays.13548652894749455626578920438837212643763502296597892572196708603714889499912","seed":13548652894749455626578920438837212643763502296597892572196708603714889499912,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727527688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2727527688' seed=13548652894749455626578920438837212643763502296597892572196708603714889499912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13548652894749455626578920438837212643763502296597892572196708603714889499912 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"17.xbar_smoke_slow_rsp.98533041262231376414641307631449523715039995943030351076658297979532978150338","seed":98533041262231376414641307631449523715039995943030351076658297979532978150338,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2064112578 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2064112578' seed=98533041262231376414641307631449523715039995943030351076658297979532978150338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98533041262231376414641307631449523715039995943030351076658297979532978150338 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"17.xbar_random.103615391401533141325040122279471187294218235559225027917148344293143950947684","seed":103615391401533141325040122279471187294218235559225027917148344293143950947684,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=733771108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.733771108' seed=103615391401533141325040122279471187294218235559225027917148344293143950947684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103615391401533141325040122279471187294218235559225027917148344293143950947684 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"17.xbar_random_zero_delays.14997722166704974967436138865072172455958700639578111657821634868807133667207","seed":14997722166704974967436138865072172455958700639578111657821634868807133667207,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2340528007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2340528007' seed=14997722166704974967436138865072172455958700639578111657821634868807133667207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14997722166704974967436138865072172455958700639578111657821634868807133667207 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"17.xbar_random_large_delays.99915274531819729041831768777647322144092132155845653323746214139622731945843","seed":99915274531819729041831768777647322144092132155845653323746214139622731945843,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=328079219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.328079219' seed=99915274531819729041831768777647322144092132155845653323746214139622731945843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99915274531819729041831768777647322144092132155845653323746214139622731945843 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"17.xbar_random_slow_rsp.96398789187019881593789958531126556408319101219300693450158685292171461197879","seed":96398789187019881593789958531126556408319101219300693450158685292171461197879,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034565175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2034565175' seed=96398789187019881593789958531126556408319101219300693450158685292171461197879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96398789187019881593789958531126556408319101219300693450158685292171461197879 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"17.xbar_access_same_device.29213907616482241146247960035446150231168241293589734776874648841543437656958","seed":29213907616482241146247960035446150231168241293589734776874648841543437656958,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646325118 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.646325118' seed=29213907616482241146247960035446150231168241293589734776874648841543437656958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29213907616482241146247960035446150231168241293589734776874648841543437656958 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"17.xbar_access_same_device_slow_rsp.88265445698015750707485971608557847904897502378165475227442090126045895993125","seed":88265445698015750707485971608557847904897502378165475227442090126045895993125,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1949050661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1949050661' seed=88265445698015750707485971608557847904897502378165475227442090126045895993125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88265445698015750707485971608557847904897502378165475227442090126045895993125 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"17.xbar_same_source.105978111395804148299127778417458617538880305512759153965233066214987063542631","seed":105978111395804148299127778417458617538880305512759153965233066214987063542631,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866725735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2866725735' seed=105978111395804148299127778417458617538880305512759153965233066214987063542631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105978111395804148299127778417458617538880305512759153965233066214987063542631 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"17.xbar_error_random.85565872097677266488196654749537852584323842585274915308473009771367428494966","seed":85565872097677266488196654749537852584323842585274915308473009771367428494966,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3889141366 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3889141366' seed=85565872097677266488196654749537852584323842585274915308473009771367428494966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85565872097677266488196654749537852584323842585274915308473009771367428494966 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"17.xbar_unmapped_addr.12899033642162035927275297572609576291309965215040047376981066790694713442810","seed":12899033642162035927275297572609576291309965215040047376981066790694713442810,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827029498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1827029498' seed=12899033642162035927275297572609576291309965215040047376981066790694713442810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12899033642162035927275297572609576291309965215040047376981066790694713442810 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"17.xbar_error_and_unmapped_addr.43138395330033454084058860334464872562224750193804991692642941150219860111991","seed":43138395330033454084058860334464872562224750193804991692642941150219860111991,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659747447 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.659747447' seed=43138395330033454084058860334464872562224750193804991692642941150219860111991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43138395330033454084058860334464872562224750193804991692642941150219860111991 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"17.xbar_stress_all.15805299037312508631580834453518277827835029740805290924850752423337441622241","seed":15805299037312508631580834453518277827835029740805290924850752423337441622241,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=846461153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.846461153' seed=15805299037312508631580834453518277827835029740805290924850752423337441622241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15805299037312508631580834453518277827835029740805290924850752423337441622241 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"17.xbar_stress_all_with_rand_reset.13545592706882537206900219904597265434350795921048909962097614007844816839137","seed":13545592706882537206900219904597265434350795921048909962097614007844816839137,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=650142177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.650142177' seed=13545592706882537206900219904597265434350795921048909962097614007844816839137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13545592706882537206900219904597265434350795921048909962097614007844816839137 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"17.xbar_stress_all_with_error.23081364194007531440840064798136764067008140889500036817556139903128512726275","seed":23081364194007531440840064798136764067008140889500036817556139903128512726275,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2210891011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2210891011' seed=23081364194007531440840064798136764067008140889500036817556139903128512726275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23081364194007531440840064798136764067008140889500036817556139903128512726275 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"17.xbar_stress_all_with_reset_error.31663854320947247044542153762077661136850157860587597718379725429236312290936","seed":31663854320947247044542153762077661136850157860587597718379725429236312290936,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799679096 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2799679096' seed=31663854320947247044542153762077661136850157860587597718379725429236312290936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31663854320947247044542153762077661136850157860587597718379725429236312290936 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"18.chip_sw_all_escalation_resets.114092227112380016062719487342647908654226704792049970963793456318505941113440","seed":114092227112380016062719487342647908654226704792049970963793456318505941113440,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3719469664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3719469664' seed=114092227112380016062719487342647908654226704792049970963793456318505941113440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114092227112380016062719487342647908654226704792049970963793456318505941113440 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"18.chip_sw_uart_rand_baudrate.63180735722074267415212641038549617740172357581447550929451349358644070677336","seed":63180735722074267415212641038549617740172357581447550929451349358644070677336,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241980248 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4241980248' seed=63180735722074267415212641038549617740172357581447550929451349358644070677336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63180735722074267415212641038549617740172357581447550929451349358644070677336 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.89351307680499821693074835742312990085932523793736089987703484994836925834246","seed":89351307680499821693074835742312990085932523793736089987703484994836925834246,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.50018725109502405618743892406117063343702265034007962705137277700689096810594","seed":50018725109502405618743892406117063343702265034007962705137277700689096810594,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3030589538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3030589538' seed=50018725109502405618743892406117063343702265034007962705137277700689096810594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50018725109502405618743892406117063343702265034007962705137277700689096810594 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"18.xbar_smoke.60317305254118101794319059123420081734536429425224463927184624387399866832988","seed":60317305254118101794319059123420081734536429425224463927184624387399866832988,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394975324 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.394975324' seed=60317305254118101794319059123420081734536429425224463927184624387399866832988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60317305254118101794319059123420081734536429425224463927184624387399866832988 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"18.xbar_smoke_zero_delays.18831812547277347271175359814938467328458053447382518651706367086084040282939","seed":18831812547277347271175359814938467328458053447382518651706367086084040282939,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2984104763 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2984104763' seed=18831812547277347271175359814938467328458053447382518651706367086084040282939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18831812547277347271175359814938467328458053447382518651706367086084040282939 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"18.xbar_smoke_large_delays.47945355515526565922082671259279329647057878669069070116510445129667277438353","seed":47945355515526565922082671259279329647057878669069070116510445129667277438353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=415710609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.415710609' seed=47945355515526565922082671259279329647057878669069070116510445129667277438353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47945355515526565922082671259279329647057878669069070116510445129667277438353 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"18.xbar_smoke_slow_rsp.30305997376671155592953255679687209561276880740998786659609301116457342975922","seed":30305997376671155592953255679687209561276880740998786659609301116457342975922,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2696396722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2696396722' seed=30305997376671155592953255679687209561276880740998786659609301116457342975922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30305997376671155592953255679687209561276880740998786659609301116457342975922 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"18.xbar_random.80781637500803058736334843267113042177547953146413464141026274064272623083107","seed":80781637500803058736334843267113042177547953146413464141026274064272623083107,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=899358307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.899358307' seed=80781637500803058736334843267113042177547953146413464141026274064272623083107 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80781637500803058736334843267113042177547953146413464141026274064272623083107 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"18.xbar_random_zero_delays.28701460524403785779962199930513684115957724718383865933718286208059931645416","seed":28701460524403785779962199930513684115957724718383865933718286208059931645416,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1085036008 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1085036008' seed=28701460524403785779962199930513684115957724718383865933718286208059931645416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28701460524403785779962199930513684115957724718383865933718286208059931645416 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"18.xbar_random_large_delays.66829511434887576394744620992128775761803331757816170159727873307435437450893","seed":66829511434887576394744620992128775761803331757816170159727873307435437450893,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572215949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2572215949' seed=66829511434887576394744620992128775761803331757816170159727873307435437450893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66829511434887576394744620992128775761803331757816170159727873307435437450893 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"18.xbar_random_slow_rsp.31270759454707803767704004196801763498876058056157509052351430009029219646","seed":31270759454707803767704004196801763498876058056157509052351430009029219646,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574158654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3574158654' seed=31270759454707803767704004196801763498876058056157509052351430009029219646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31270759454707803767704004196801763498876058056157509052351430009029219646 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"18.xbar_access_same_device.92823779910499276886580966369968636014487403475472011718556781862881023452951","seed":92823779910499276886580966369968636014487403475472011718556781862881023452951,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862414615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.862414615' seed=92823779910499276886580966369968636014487403475472011718556781862881023452951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92823779910499276886580966369968636014487403475472011718556781862881023452951 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"18.xbar_access_same_device_slow_rsp.85147984976290957198636972080439443511537881001097771453336528896452792583767","seed":85147984976290957198636972080439443511537881001097771453336528896452792583767,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923436631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.923436631' seed=85147984976290957198636972080439443511537881001097771453336528896452792583767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85147984976290957198636972080439443511537881001097771453336528896452792583767 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"18.xbar_same_source.49860028206102008587953771714677764651740544689694732812060045710566255226144","seed":49860028206102008587953771714677764651740544689694732812060045710566255226144,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2064641312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2064641312' seed=49860028206102008587953771714677764651740544689694732812060045710566255226144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49860028206102008587953771714677764651740544689694732812060045710566255226144 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"18.xbar_error_random.62339794459293024582801850838296296074818099389243726528815608369802226240235","seed":62339794459293024582801850838296296074818099389243726528815608369802226240235,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3240168171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3240168171' seed=62339794459293024582801850838296296074818099389243726528815608369802226240235 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62339794459293024582801850838296296074818099389243726528815608369802226240235 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"18.xbar_unmapped_addr.33961172576374373191931169915519689612126840732201470780728874479326189559572","seed":33961172576374373191931169915519689612126840732201470780728874479326189559572,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1926471444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1926471444' seed=33961172576374373191931169915519689612126840732201470780728874479326189559572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33961172576374373191931169915519689612126840732201470780728874479326189559572 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"18.xbar_error_and_unmapped_addr.22337859793290960611344899729953783997492515185081418717828249670888306549549","seed":22337859793290960611344899729953783997492515185081418717828249670888306549549,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399811373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.399811373' seed=22337859793290960611344899729953783997492515185081418717828249670888306549549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22337859793290960611344899729953783997492515185081418717828249670888306549549 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"18.xbar_stress_all.22601550705279198602516204931990872334483677253621708919033874771599245706569","seed":22601550705279198602516204931990872334483677253621708919033874771599245706569,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2431124809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2431124809' seed=22601550705279198602516204931990872334483677253621708919033874771599245706569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22601550705279198602516204931990872334483677253621708919033874771599245706569 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"18.xbar_stress_all_with_rand_reset.108707987772387276465441281945508105736994667709532336585484740212861328555865","seed":108707987772387276465441281945508105736994667709532336585484740212861328555865,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596222297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.3596222297' seed=108707987772387276465441281945508105736994667709532336585484740212861328555865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108707987772387276465441281945508105736994667709532336585484740212861328555865 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"18.xbar_stress_all_with_error.44917291579659280908758064468017680357539251084745973248005818870229756234412","seed":44917291579659280908758064468017680357539251084745973248005818870229756234412,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2931247788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2931247788' seed=44917291579659280908758064468017680357539251084745973248005818870229756234412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44917291579659280908758064468017680357539251084745973248005818870229756234412 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"18.xbar_stress_all_with_reset_error.47428674318510573446340150918647638851959840831415340737121252720654687656311","seed":47428674318510573446340150918647638851959840831415340737121252720654687656311,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727256951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.1727256951' seed=47428674318510573446340150918647638851959840831415340737121252720654687656311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47428674318510573446340150918647638851959840831415340737121252720654687656311 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"19.chip_sw_all_escalation_resets.21756130192400794242484410703435739381743575870067064205814219343470554715885","seed":21756130192400794242484410703435739381743575870067064205814219343470554715885,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1817122541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1817122541' seed=21756130192400794242484410703435739381743575870067064205814219343470554715885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21756130192400794242484410703435739381743575870067064205814219343470554715885 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"19.chip_sw_uart_rand_baudrate.44867136613777370457155161180083473357196910390358855539085261732497747976476","seed":44867136613777370457155161180083473357196910390358855539085261732497747976476,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest run_opts='+sw_test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3766853916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3766853916' seed=44867136613777370457155161180083473357196910390358855539085261732497747976476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44867136613777370457155161180083473357196910390358855539085261732497747976476 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:uart_tx_rx_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_uart_rand_baudrate_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.41560905080458406893778565800627106462360409400227486789957490807204488370998","seed":41560905080458406893778565800627106462360409400227486789957490807204488370998,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.77858590467621941626247766621513741350714081786676307165918382548406406388772","seed":77858590467621941626247766621513741350714081786676307165918382548406406388772,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717293604 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2717293604' seed=77858590467621941626247766621513741350714081786676307165918382548406406388772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77858590467621941626247766621513741350714081786676307165918382548406406388772 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"19.xbar_smoke.37320951863785444709334196279215370385501215676210826069655636679311686222629","seed":37320951863785444709334196279215370385501215676210826069655636679311686222629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81904421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.81904421' seed=37320951863785444709334196279215370385501215676210826069655636679311686222629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37320951863785444709334196279215370385501215676210826069655636679311686222629 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"19.xbar_smoke_zero_delays.88092498222897376380381588555030853716865442386543412217958360963721242646928","seed":88092498222897376380381588555030853716865442386543412217958360963721242646928,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599117712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1599117712' seed=88092498222897376380381588555030853716865442386543412217958360963721242646928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88092498222897376380381588555030853716865442386543412217958360963721242646928 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"19.xbar_smoke_large_delays.14855846931252279623897284056071835210322030999877627377409330680239805795219","seed":14855846931252279623897284056071835210322030999877627377409330680239805795219,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=927042451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.927042451' seed=14855846931252279623897284056071835210322030999877627377409330680239805795219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14855846931252279623897284056071835210322030999877627377409330680239805795219 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"19.xbar_smoke_slow_rsp.92999496900387669467150879369944122384772045356184347538467896734366038143930","seed":92999496900387669467150879369944122384772045356184347538467896734366038143930,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3561141178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3561141178' seed=92999496900387669467150879369944122384772045356184347538467896734366038143930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92999496900387669467150879369944122384772045356184347538467896734366038143930 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"19.xbar_random.46731481904729898950876613768837753091938888652750606804783210985276267065490","seed":46731481904729898950876613768837753091938888652750606804783210985276267065490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753065106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2753065106' seed=46731481904729898950876613768837753091938888652750606804783210985276267065490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46731481904729898950876613768837753091938888652750606804783210985276267065490 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"19.xbar_random_zero_delays.2471091482906603327377225473929722865794300406079210052606534186913927782543","seed":2471091482906603327377225473929722865794300406079210052606534186913927782543,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710298767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2710298767' seed=2471091482906603327377225473929722865794300406079210052606534186913927782543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2471091482906603327377225473929722865794300406079210052606534186913927782543 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"19.xbar_random_large_delays.5905407547923632349687906359395436074095871037910136493879772085981620178985","seed":5905407547923632349687906359395436074095871037910136493879772085981620178985,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17010729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.17010729' seed=5905407547923632349687906359395436074095871037910136493879772085981620178985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5905407547923632349687906359395436074095871037910136493879772085981620178985 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"19.xbar_random_slow_rsp.12275580700333665169539207194751016902705910441044481907326992073591339631159","seed":12275580700333665169539207194751016902705910441044481907326992073591339631159,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1578123831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1578123831' seed=12275580700333665169539207194751016902705910441044481907326992073591339631159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12275580700333665169539207194751016902705910441044481907326992073591339631159 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"19.xbar_access_same_device.24642734337920740415327081534427737606914731628945520632830811470689979987769","seed":24642734337920740415327081534427737606914731628945520632830811470689979987769,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3474847545 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3474847545' seed=24642734337920740415327081534427737606914731628945520632830811470689979987769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24642734337920740415327081534427737606914731628945520632830811470689979987769 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"19.xbar_access_same_device_slow_rsp.60823617892826553636668884291366462601568842618087851493700288105730609364695","seed":60823617892826553636668884291366462601568842618087851493700288105730609364695,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2907291351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2907291351' seed=60823617892826553636668884291366462601568842618087851493700288105730609364695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60823617892826553636668884291366462601568842618087851493700288105730609364695 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"19.xbar_same_source.88323385224079643189901788762523830074788099214882104496803585149076084567351","seed":88323385224079643189901788762523830074788099214882104496803585149076084567351,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706844983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2706844983' seed=88323385224079643189901788762523830074788099214882104496803585149076084567351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88323385224079643189901788762523830074788099214882104496803585149076084567351 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"19.xbar_error_random.87645171251596698249058584123642602807368482054161239062659426305237053348015","seed":87645171251596698249058584123642602807368482054161239062659426305237053348015,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1151342767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1151342767' seed=87645171251596698249058584123642602807368482054161239062659426305237053348015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87645171251596698249058584123642602807368482054161239062659426305237053348015 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"19.xbar_unmapped_addr.15514559851804590570013213912988533173476275066339141021596585091187242632656","seed":15514559851804590570013213912988533173476275066339141021596585091187242632656,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=364840400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.364840400' seed=15514559851804590570013213912988533173476275066339141021596585091187242632656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15514559851804590570013213912988533173476275066339141021596585091187242632656 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"19.xbar_error_and_unmapped_addr.29535378336429098891667625518673424993446098431208268099359397157982931328956","seed":29535378336429098891667625518673424993446098431208268099359397157982931328956,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836130236 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1836130236' seed=29535378336429098891667625518673424993446098431208268099359397157982931328956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29535378336429098891667625518673424993446098431208268099359397157982931328956 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"19.xbar_stress_all.46161619911150131007991402015475593027818108630500337930394309325692951665260","seed":46161619911150131007991402015475593027818108630500337930394309325692951665260,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=577837676 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.577837676' seed=46161619911150131007991402015475593027818108630500337930394309325692951665260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46161619911150131007991402015475593027818108630500337930394309325692951665260 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"19.xbar_stress_all_with_rand_reset.74224923389427390268097181075210875414979444987387296083769946323070662554888","seed":74224923389427390268097181075210875414979444987387296083769946323070662554888,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1188902152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.1188902152' seed=74224923389427390268097181075210875414979444987387296083769946323070662554888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74224923389427390268097181075210875414979444987387296083769946323070662554888 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"19.xbar_stress_all_with_error.61720465499900162347189467013803250604344579904634920285448002331845482547033","seed":61720465499900162347189467013803250604344579904634920285448002331845482547033,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=80250713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.80250713' seed=61720465499900162347189467013803250604344579904634920285448002331845482547033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61720465499900162347189467013803250604344579904634920285448002331845482547033 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"19.xbar_stress_all_with_reset_error.46558444580118557646655578940801986869072420587429667157586105042774923181305","seed":46558444580118557646655578940801986869072420587429667157586105042774923181305,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2609675513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2609675513' seed=46558444580118557646655578940801986869072420587429667157586105042774923181305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46558444580118557646655578940801986869072420587429667157586105042774923181305 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"20.chip_sw_all_escalation_resets.13314796733109935115197830682941736517663172709036448899842143981542044888934","seed":13314796733109935115197830682941736517663172709036448899842143981542044888934,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=378826598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.378826598' seed=13314796733109935115197830682941736517663172709036448899842143981542044888934 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13314796733109935115197830682941736517663172709036448899842143981542044888934 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.114952861887303976582864543587986875456186297434707288030077778903407875658977","seed":114952861887303976582864543587986875456186297434707288030077778903407875658977,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.78030270974740846260394659259018512118094522746151168566241600928575900826775","seed":78030270974740846260394659259018512118094522746151168566241600928575900826775,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3906419863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3906419863' seed=78030270974740846260394659259018512118094522746151168566241600928575900826775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78030270974740846260394659259018512118094522746151168566241600928575900826775 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"20.xbar_smoke.4032793011991660530310752643893790684818582904603105123961015881322088806589","seed":4032793011991660530310752643893790684818582904603105123961015881322088806589,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1206827197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1206827197' seed=4032793011991660530310752643893790684818582904603105123961015881322088806589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4032793011991660530310752643893790684818582904603105123961015881322088806589 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"20.xbar_smoke_zero_delays.89047401269798013864182693007729721285433481473100059797537786297344889334728","seed":89047401269798013864182693007729721285433481473100059797537786297344889334728,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=500837320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.500837320' seed=89047401269798013864182693007729721285433481473100059797537786297344889334728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89047401269798013864182693007729721285433481473100059797537786297344889334728 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"20.xbar_smoke_large_delays.5237066588538089811006550513017692031186723258671413145036356846150654402477","seed":5237066588538089811006550513017692031186723258671413145036356846150654402477,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3907559341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3907559341' seed=5237066588538089811006550513017692031186723258671413145036356846150654402477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5237066588538089811006550513017692031186723258671413145036356846150654402477 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"20.xbar_smoke_slow_rsp.6754008829726741933049712604312762753601371208882470761969257630936274949060","seed":6754008829726741933049712604312762753601371208882470761969257630936274949060,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16110532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.16110532' seed=6754008829726741933049712604312762753601371208882470761969257630936274949060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6754008829726741933049712604312762753601371208882470761969257630936274949060 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"20.xbar_random.70496726206642431299880674082937148606714555953143869995023238973242165107124","seed":70496726206642431299880674082937148606714555953143869995023238973242165107124,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2028935604 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2028935604' seed=70496726206642431299880674082937148606714555953143869995023238973242165107124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70496726206642431299880674082937148606714555953143869995023238973242165107124 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"20.xbar_random_zero_delays.63178354178573585164034748477537144412614881437726506386618121334990902096084","seed":63178354178573585164034748477537144412614881437726506386618121334990902096084,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=909340884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.909340884' seed=63178354178573585164034748477537144412614881437726506386618121334990902096084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63178354178573585164034748477537144412614881437726506386618121334990902096084 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"20.xbar_random_large_delays.67233167007393114647208563004464187846860796145901952802865434723901714811032","seed":67233167007393114647208563004464187846860796145901952802865434723901714811032,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1664698520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1664698520' seed=67233167007393114647208563004464187846860796145901952802865434723901714811032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67233167007393114647208563004464187846860796145901952802865434723901714811032 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"20.xbar_random_slow_rsp.70989729974448807852756844347964673168497932490475634713658533756637775751645","seed":70989729974448807852756844347964673168497932490475634713658533756637775751645,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2211015133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2211015133' seed=70989729974448807852756844347964673168497932490475634713658533756637775751645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70989729974448807852756844347964673168497932490475634713658533756637775751645 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"20.xbar_access_same_device.23777699601263949388595083722155268174815838002887307328644047306386398813211","seed":23777699601263949388595083722155268174815838002887307328644047306386398813211,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611884059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.611884059' seed=23777699601263949388595083722155268174815838002887307328644047306386398813211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23777699601263949388595083722155268174815838002887307328644047306386398813211 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"20.xbar_access_same_device_slow_rsp.97657071299706866148695795631158910565418885762269505111537526973838396508385","seed":97657071299706866148695795631158910565418885762269505111537526973838396508385,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2226145505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.2226145505' seed=97657071299706866148695795631158910565418885762269505111537526973838396508385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97657071299706866148695795631158910565418885762269505111537526973838396508385 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"20.xbar_same_source.21213788345231513353439336225980340640790422225578961889389557251105433470752","seed":21213788345231513353439336225980340640790422225578961889389557251105433470752,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1940014880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1940014880' seed=21213788345231513353439336225980340640790422225578961889389557251105433470752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21213788345231513353439336225980340640790422225578961889389557251105433470752 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"20.xbar_error_random.93268184266160946935801123911641767648999657349865839610483472036317466078581","seed":93268184266160946935801123911641767648999657349865839610483472036317466078581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113364853 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3113364853' seed=93268184266160946935801123911641767648999657349865839610483472036317466078581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93268184266160946935801123911641767648999657349865839610483472036317466078581 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"20.xbar_unmapped_addr.50907640091022839697384265597111663230341770121024406908029625627983341728863","seed":50907640091022839697384265597111663230341770121024406908029625627983341728863,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168397919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4168397919' seed=50907640091022839697384265597111663230341770121024406908029625627983341728863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50907640091022839697384265597111663230341770121024406908029625627983341728863 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"20.xbar_error_and_unmapped_addr.20734295066178701714468902443014150206796455474744598767846780369376487766819","seed":20734295066178701714468902443014150206796455474744598767846780369376487766819,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989690659 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.989690659' seed=20734295066178701714468902443014150206796455474744598767846780369376487766819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20734295066178701714468902443014150206796455474744598767846780369376487766819 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"20.xbar_stress_all.30257823829743364345333620468057181794487941738322879344245979620848985540194","seed":30257823829743364345333620468057181794487941738322879344245979620848985540194,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1192068706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1192068706' seed=30257823829743364345333620468057181794487941738322879344245979620848985540194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30257823829743364345333620468057181794487941738322879344245979620848985540194 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"20.xbar_stress_all_with_rand_reset.9065999899963338417490957071383389020874070835521025410077064519067210361809","seed":9065999899963338417490957071383389020874070835521025410077064519067210361809,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2024025041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2024025041' seed=9065999899963338417490957071383389020874070835521025410077064519067210361809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9065999899963338417490957071383389020874070835521025410077064519067210361809 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"20.xbar_stress_all_with_error.77620099744198045745588907245568063477814041316364656085508447734990506350633","seed":77620099744198045745588907245568063477814041316364656085508447734990506350633,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2352273449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2352273449' seed=77620099744198045745588907245568063477814041316364656085508447734990506350633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77620099744198045745588907245568063477814041316364656085508447734990506350633 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"20.xbar_stress_all_with_reset_error.66926937111863645090296496613400695961032349624143882241413314551635768381368","seed":66926937111863645090296496613400695961032349624143882241413314551635768381368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3161591736 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3161591736' seed=66926937111863645090296496613400695961032349624143882241413314551635768381368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66926937111863645090296496613400695961032349624143882241413314551635768381368 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"21.chip_sw_all_escalation_resets.110326416982331349517342548143681942836827884773937810012858954225269191707828","seed":110326416982331349517342548143681942836827884773937810012858954225269191707828,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3834088628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3834088628' seed=110326416982331349517342548143681942836827884773937810012858954225269191707828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110326416982331349517342548143681942836827884773937810012858954225269191707828 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.53406876572671717981331942537775569516619277408902555579606520263201354940010","seed":53406876572671717981331942537775569516619277408902555579606520263201354940010,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.9030535127008397787897701212910889072124636136624785597847665232402185336614","seed":9030535127008397787897701212910889072124636136624785597847665232402185336614,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2438084390 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2438084390' seed=9030535127008397787897701212910889072124636136624785597847665232402185336614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9030535127008397787897701212910889072124636136624785597847665232402185336614 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"21.xbar_smoke.102736575145065120571348590419483236739884981629238743405528064235964662372642","seed":102736575145065120571348590419483236739884981629238743405528064235964662372642,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816563490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2816563490' seed=102736575145065120571348590419483236739884981629238743405528064235964662372642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102736575145065120571348590419483236739884981629238743405528064235964662372642 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"21.xbar_smoke_zero_delays.29379340400590485041837362385625551720124632516961366607022766230178999936538","seed":29379340400590485041837362385625551720124632516961366607022766230178999936538,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=426878490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.426878490' seed=29379340400590485041837362385625551720124632516961366607022766230178999936538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29379340400590485041837362385625551720124632516961366607022766230178999936538 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"21.xbar_smoke_large_delays.30725389558768581663094131372667276838163846070627708463320506622383925256516","seed":30725389558768581663094131372667276838163846070627708463320506622383925256516,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2575327556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2575327556' seed=30725389558768581663094131372667276838163846070627708463320506622383925256516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30725389558768581663094131372667276838163846070627708463320506622383925256516 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"21.xbar_smoke_slow_rsp.101124303371074363422324083536232332495349455606989787402892006192995954040172","seed":101124303371074363422324083536232332495349455606989787402892006192995954040172,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466567020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3466567020' seed=101124303371074363422324083536232332495349455606989787402892006192995954040172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101124303371074363422324083536232332495349455606989787402892006192995954040172 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"21.xbar_random.11152063710908013871245891078487551692374283772512742214404391792259147993782","seed":11152063710908013871245891078487551692374283772512742214404391792259147993782,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3386086070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3386086070' seed=11152063710908013871245891078487551692374283772512742214404391792259147993782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11152063710908013871245891078487551692374283772512742214404391792259147993782 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"21.xbar_random_zero_delays.50826380198095159930297252046802098504950785307290723867973068605775801549864","seed":50826380198095159930297252046802098504950785307290723867973068605775801549864,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1646593064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1646593064' seed=50826380198095159930297252046802098504950785307290723867973068605775801549864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50826380198095159930297252046802098504950785307290723867973068605775801549864 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"21.xbar_random_large_delays.38720672267617080369475967118095253236781287107323276224649305620906990132176","seed":38720672267617080369475967118095253236781287107323276224649305620906990132176,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979552208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2979552208' seed=38720672267617080369475967118095253236781287107323276224649305620906990132176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38720672267617080369475967118095253236781287107323276224649305620906990132176 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"21.xbar_random_slow_rsp.44438863741582817245591489109455738729063612279361919435301805474059444616267","seed":44438863741582817245591489109455738729063612279361919435301805474059444616267,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2926640203 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2926640203' seed=44438863741582817245591489109455738729063612279361919435301805474059444616267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44438863741582817245591489109455738729063612279361919435301805474059444616267 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"21.xbar_access_same_device.40980685409585568850113685111846753590822292523834343513882413002095836183825","seed":40980685409585568850113685111846753590822292523834343513882413002095836183825,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3925261585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3925261585' seed=40980685409585568850113685111846753590822292523834343513882413002095836183825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40980685409585568850113685111846753590822292523834343513882413002095836183825 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"21.xbar_access_same_device_slow_rsp.101160805199475222186393759696295771748207131784908968123133876772081733265610","seed":101160805199475222186393759696295771748207131784908968123133876772081733265610,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3062163658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3062163658' seed=101160805199475222186393759696295771748207131784908968123133876772081733265610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101160805199475222186393759696295771748207131784908968123133876772081733265610 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"21.xbar_same_source.51274336975078117572964362115874678332633261860217965803105280422378049021374","seed":51274336975078117572964362115874678332633261860217965803105280422378049021374,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1267901886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1267901886' seed=51274336975078117572964362115874678332633261860217965803105280422378049021374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51274336975078117572964362115874678332633261860217965803105280422378049021374 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"21.xbar_error_random.19606502874900547913228418216274954300539279035816349686529581504350639454052","seed":19606502874900547913228418216274954300539279035816349686529581504350639454052,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1922660196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1922660196' seed=19606502874900547913228418216274954300539279035816349686529581504350639454052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19606502874900547913228418216274954300539279035816349686529581504350639454052 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"21.xbar_unmapped_addr.107506222871037743387049561406586552769651691204854081673674294579243079842274","seed":107506222871037743387049561406586552769651691204854081673674294579243079842274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2665626082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2665626082' seed=107506222871037743387049561406586552769651691204854081673674294579243079842274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107506222871037743387049561406586552769651691204854081673674294579243079842274 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"21.xbar_error_and_unmapped_addr.86856488145435667748176334090625224954868019104661266232896034667660729011229","seed":86856488145435667748176334090625224954868019104661266232896034667660729011229,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3019000861 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3019000861' seed=86856488145435667748176334090625224954868019104661266232896034667660729011229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86856488145435667748176334090625224954868019104661266232896034667660729011229 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"21.xbar_stress_all.37500280935479540785634151362237188530083977235111573384426279778161825112008","seed":37500280935479540785634151362237188530083977235111573384426279778161825112008,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2967953352 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2967953352' seed=37500280935479540785634151362237188530083977235111573384426279778161825112008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=37500280935479540785634151362237188530083977235111573384426279778161825112008 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"21.xbar_stress_all_with_rand_reset.50943732747332577746006762210854928192770340246380054001184335298434723844090","seed":50943732747332577746006762210854928192770340246380054001184335298434723844090,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1677037562 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1677037562' seed=50943732747332577746006762210854928192770340246380054001184335298434723844090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50943732747332577746006762210854928192770340246380054001184335298434723844090 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"21.xbar_stress_all_with_error.28598373276890442352787858887879722936193599249963789767048808566469723116587","seed":28598373276890442352787858887879722936193599249963789767048808566469723116587,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641946667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.641946667' seed=28598373276890442352787858887879722936193599249963789767048808566469723116587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28598373276890442352787858887879722936193599249963789767048808566469723116587 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"21.xbar_stress_all_with_reset_error.26905098819513039500925383751374528358707718779185990182493374793314237932946","seed":26905098819513039500925383751374528358707718779185990182493374793314237932946,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1051452818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1051452818' seed=26905098819513039500925383751374528358707718779185990182493374793314237932946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26905098819513039500925383751374528358707718779185990182493374793314237932946 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"22.chip_sw_all_escalation_resets.20518829593987583197328408516290588498547685994782587271474348031511033614747","seed":20518829593987583197328408516290588498547685994782587271474348031511033614747,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2941587867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2941587867' seed=20518829593987583197328408516290588498547685994782587271474348031511033614747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20518829593987583197328408516290588498547685994782587271474348031511033614747 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.104527692450784499061630435553554768521226582832204564100572578298153252788340","seed":104527692450784499061630435553554768521226582832204564100572578298153252788340,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.107683476928411681690135002285334871449772872975626987251495995598144790411764","seed":107683476928411681690135002285334871449772872975626987251495995598144790411764,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608937460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2608937460' seed=107683476928411681690135002285334871449772872975626987251495995598144790411764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107683476928411681690135002285334871449772872975626987251495995598144790411764 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"22.xbar_smoke.26257254415013703799823648372725071433938500154662982913056582299672668941410","seed":26257254415013703799823648372725071433938500154662982913056582299672668941410,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=851586146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.851586146' seed=26257254415013703799823648372725071433938500154662982913056582299672668941410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26257254415013703799823648372725071433938500154662982913056582299672668941410 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"22.xbar_smoke_zero_delays.56522703713428675799748335032638569096375661203301832022605547121960505883493","seed":56522703713428675799748335032638569096375661203301832022605547121960505883493,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3117988709 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3117988709' seed=56522703713428675799748335032638569096375661203301832022605547121960505883493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56522703713428675799748335032638569096375661203301832022605547121960505883493 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"22.xbar_smoke_large_delays.45379638678815826228151779582881677489425780383547963718580683075143476769017","seed":45379638678815826228151779582881677489425780383547963718580683075143476769017,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=270856441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.270856441' seed=45379638678815826228151779582881677489425780383547963718580683075143476769017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45379638678815826228151779582881677489425780383547963718580683075143476769017 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"22.xbar_smoke_slow_rsp.80186091992485458523668831740465856175462522486686566102486038083050384147843","seed":80186091992485458523668831740465856175462522486686566102486038083050384147843,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3283371395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3283371395' seed=80186091992485458523668831740465856175462522486686566102486038083050384147843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80186091992485458523668831740465856175462522486686566102486038083050384147843 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"22.xbar_random.69558134490203314164266841357264930692380686293131496304721115592611912516302","seed":69558134490203314164266841357264930692380686293131496304721115592611912516302,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065886926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.4065886926' seed=69558134490203314164266841357264930692380686293131496304721115592611912516302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69558134490203314164266841357264930692380686293131496304721115592611912516302 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"22.xbar_random_zero_delays.44621124815255193193091550670070015746159528210830336860308055956219204519540","seed":44621124815255193193091550670070015746159528210830336860308055956219204519540,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464021620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3464021620' seed=44621124815255193193091550670070015746159528210830336860308055956219204519540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44621124815255193193091550670070015746159528210830336860308055956219204519540 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"22.xbar_random_large_delays.92833272923572053969334829309040390349581553235134181898527414659095140178463","seed":92833272923572053969334829309040390349581553235134181898527414659095140178463,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379422239 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2379422239' seed=92833272923572053969334829309040390349581553235134181898527414659095140178463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92833272923572053969334829309040390349581553235134181898527414659095140178463 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"22.xbar_random_slow_rsp.15702150039145424182589639554131247343162564538616755603210941011626044424024","seed":15702150039145424182589639554131247343162564538616755603210941011626044424024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654025048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3654025048' seed=15702150039145424182589639554131247343162564538616755603210941011626044424024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15702150039145424182589639554131247343162564538616755603210941011626044424024 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"22.xbar_access_same_device.87916203439194217901230097911182525342886437797592301378622448747472238040765","seed":87916203439194217901230097911182525342886437797592301378622448747472238040765,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1188189885 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1188189885' seed=87916203439194217901230097911182525342886437797592301378622448747472238040765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87916203439194217901230097911182525342886437797592301378622448747472238040765 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"22.xbar_access_same_device_slow_rsp.10716632887083268903700126691766668493870903601170577466202497914621188644956","seed":10716632887083268903700126691766668493870903601170577466202497914621188644956,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1100226652 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1100226652' seed=10716632887083268903700126691766668493870903601170577466202497914621188644956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10716632887083268903700126691766668493870903601170577466202497914621188644956 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"22.xbar_same_source.28258959706497522070674914896991416337848574741102348998948141765025887550771","seed":28258959706497522070674914896991416337848574741102348998948141765025887550771,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2276064563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2276064563' seed=28258959706497522070674914896991416337848574741102348998948141765025887550771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28258959706497522070674914896991416337848574741102348998948141765025887550771 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"22.xbar_error_random.51936956922282680888917884823193098952199935225091985843121720540679091128890","seed":51936956922282680888917884823193098952199935225091985843121720540679091128890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2140539450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2140539450' seed=51936956922282680888917884823193098952199935225091985843121720540679091128890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51936956922282680888917884823193098952199935225091985843121720540679091128890 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"22.xbar_unmapped_addr.76836701385343834983580796425058439238946685665809313830234074904355956246585","seed":76836701385343834983580796425058439238946685665809313830234074904355956246585,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980680249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1980680249' seed=76836701385343834983580796425058439238946685665809313830234074904355956246585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76836701385343834983580796425058439238946685665809313830234074904355956246585 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"22.xbar_error_and_unmapped_addr.62686440332305877582969254497071648391061816611368941645124448589537229580087","seed":62686440332305877582969254497071648391061816611368941645124448589537229580087,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3138823991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3138823991' seed=62686440332305877582969254497071648391061816611368941645124448589537229580087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62686440332305877582969254497071648391061816611368941645124448589537229580087 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"22.xbar_stress_all.90949099650936745055041395158147258710091716637357547829385330153029956268154","seed":90949099650936745055041395158147258710091716637357547829385330153029956268154,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3969118330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3969118330' seed=90949099650936745055041395158147258710091716637357547829385330153029956268154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90949099650936745055041395158147258710091716637357547829385330153029956268154 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"22.xbar_stress_all_with_rand_reset.10746241509283908218776609441951754866505488008001905365141097535841718789671","seed":10746241509283908218776609441951754866505488008001905365141097535841718789671,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075682343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.2075682343' seed=10746241509283908218776609441951754866505488008001905365141097535841718789671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10746241509283908218776609441951754866505488008001905365141097535841718789671 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"22.xbar_stress_all_with_error.89744057229474306140267848737670249458121860987514517251054483259680356135136","seed":89744057229474306140267848737670249458121860987514517251054483259680356135136,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101520096 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3101520096' seed=89744057229474306140267848737670249458121860987514517251054483259680356135136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89744057229474306140267848737670249458121860987514517251054483259680356135136 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"22.xbar_stress_all_with_reset_error.29729051118674092724259852054652293354488992664667672942800490199113921546219","seed":29729051118674092724259852054652293354488992664667672942800490199113921546219,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2546026475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2546026475' seed=29729051118674092724259852054652293354488992664667672942800490199113921546219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29729051118674092724259852054652293354488992664667672942800490199113921546219 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"23.chip_sw_all_escalation_resets.6960386769395914651382289166135887826137279806937625818007656106784168087710","seed":6960386769395914651382289166135887826137279806937625818007656106784168087710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2232160414 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2232160414' seed=6960386769395914651382289166135887826137279806937625818007656106784168087710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6960386769395914651382289166135887826137279806937625818007656106784168087710 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3277242069434865551244454385601883279302940566966685929459347689878201959719","seed":3277242069434865551244454385601883279302940566966685929459347689878201959719,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.100619950403821279580926916453527726074204659736709580954313522488187248211241","seed":100619950403821279580926916453527726074204659736709580954313522488187248211241,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2244506921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2244506921' seed=100619950403821279580926916453527726074204659736709580954313522488187248211241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100619950403821279580926916453527726074204659736709580954313522488187248211241 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"23.xbar_smoke.30202378194296920345597140837541264066576301904248031965916116379782163995581","seed":30202378194296920345597140837541264066576301904248031965916116379782163995581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4175174589 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4175174589' seed=30202378194296920345597140837541264066576301904248031965916116379782163995581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30202378194296920345597140837541264066576301904248031965916116379782163995581 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"23.xbar_smoke_zero_delays.43600745810940304446315424806568981092426500317489253329003005316681928365096","seed":43600745810940304446315424806568981092426500317489253329003005316681928365096,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=277173288 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.277173288' seed=43600745810940304446315424806568981092426500317489253329003005316681928365096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43600745810940304446315424806568981092426500317489253329003005316681928365096 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"23.xbar_smoke_large_delays.20828097680040105744088422228882015531613956711968452435059112494092860466154","seed":20828097680040105744088422228882015531613956711968452435059112494092860466154,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=775103466 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.775103466' seed=20828097680040105744088422228882015531613956711968452435059112494092860466154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20828097680040105744088422228882015531613956711968452435059112494092860466154 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"23.xbar_smoke_slow_rsp.54578819706254479459171506180603840159927722549962604911149829435328997015012","seed":54578819706254479459171506180603840159927722549962604911149829435328997015012,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=429571556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.429571556' seed=54578819706254479459171506180603840159927722549962604911149829435328997015012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54578819706254479459171506180603840159927722549962604911149829435328997015012 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"23.xbar_random.46397631970965353807960822149567431823472879972111295589354424331217911835589","seed":46397631970965353807960822149567431823472879972111295589354424331217911835589,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1680239557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1680239557' seed=46397631970965353807960822149567431823472879972111295589354424331217911835589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46397631970965353807960822149567431823472879972111295589354424331217911835589 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"23.xbar_random_zero_delays.93779615574045343240849034374992945956010733541031292310169421045804955612955","seed":93779615574045343240849034374992945956010733541031292310169421045804955612955,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3645912859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3645912859' seed=93779615574045343240849034374992945956010733541031292310169421045804955612955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93779615574045343240849034374992945956010733541031292310169421045804955612955 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"23.xbar_random_large_delays.46465238307129963708844066843893110534188072541697495504404351496774065760246","seed":46465238307129963708844066843893110534188072541697495504404351496774065760246,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3518146550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3518146550' seed=46465238307129963708844066843893110534188072541697495504404351496774065760246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46465238307129963708844066843893110534188072541697495504404351496774065760246 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"23.xbar_random_slow_rsp.64706824448639045685180872908376724522112632990265356833120868339629715759390","seed":64706824448639045685180872908376724522112632990265356833120868339629715759390,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1327112478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1327112478' seed=64706824448639045685180872908376724522112632990265356833120868339629715759390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64706824448639045685180872908376724522112632990265356833120868339629715759390 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"23.xbar_access_same_device.24196247830089094820593306417842036458287941994447142843816671251116651583478","seed":24196247830089094820593306417842036458287941994447142843816671251116651583478,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=414849014 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.414849014' seed=24196247830089094820593306417842036458287941994447142843816671251116651583478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24196247830089094820593306417842036458287941994447142843816671251116651583478 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"23.xbar_access_same_device_slow_rsp.12365540712468267213242860589258754986401084527520184020321669371972126837385","seed":12365540712468267213242860589258754986401084527520184020321669371972126837385,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=505219721 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.505219721' seed=12365540712468267213242860589258754986401084527520184020321669371972126837385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12365540712468267213242860589258754986401084527520184020321669371972126837385 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"23.xbar_same_source.44386984215269648054157882363757309381360003814162515944034435880752678839420","seed":44386984215269648054157882363757309381360003814162515944034435880752678839420,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2418156668 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2418156668' seed=44386984215269648054157882363757309381360003814162515944034435880752678839420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44386984215269648054157882363757309381360003814162515944034435880752678839420 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"23.xbar_error_random.2816435092449553683513771477804555026574939852050972659986106979852607314573","seed":2816435092449553683513771477804555026574939852050972659986106979852607314573,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506826893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1506826893' seed=2816435092449553683513771477804555026574939852050972659986106979852607314573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2816435092449553683513771477804555026574939852050972659986106979852607314573 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"23.xbar_unmapped_addr.106785065809218005691494060163431774094093540502273517901983469020724889050697","seed":106785065809218005691494060163431774094093540502273517901983469020724889050697,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590694985 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2590694985' seed=106785065809218005691494060163431774094093540502273517901983469020724889050697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106785065809218005691494060163431774094093540502273517901983469020724889050697 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"23.xbar_error_and_unmapped_addr.78632683594921928684972616507218512485376598162421227378944641253619471341050","seed":78632683594921928684972616507218512485376598162421227378944641253619471341050,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3146110458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3146110458' seed=78632683594921928684972616507218512485376598162421227378944641253619471341050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78632683594921928684972616507218512485376598162421227378944641253619471341050 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"23.xbar_stress_all.63146605414356272568271827103797059306672447534536298542026004482130167187123","seed":63146605414356272568271827103797059306672447534536298542026004482130167187123,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1096533683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1096533683' seed=63146605414356272568271827103797059306672447534536298542026004482130167187123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63146605414356272568271827103797059306672447534536298542026004482130167187123 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"23.xbar_stress_all_with_rand_reset.1341316935549084900439733064905184316768598457447340001318055835135138170284","seed":1341316935549084900439733064905184316768598457447340001318055835135138170284,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1824359852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.1824359852' seed=1341316935549084900439733064905184316768598457447340001318055835135138170284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1341316935549084900439733064905184316768598457447340001318055835135138170284 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"23.xbar_stress_all_with_error.32746396554232067240157938840833507774548849206870274785707373989438838062201","seed":32746396554232067240157938840833507774548849206870274785707373989438838062201,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4152147065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4152147065' seed=32746396554232067240157938840833507774548849206870274785707373989438838062201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32746396554232067240157938840833507774548849206870274785707373989438838062201 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"23.xbar_stress_all_with_reset_error.22133907207886756657716477388947078929535639477097859186094622625699493413687","seed":22133907207886756657716477388947078929535639477097859186094622625699493413687,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165829431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.4165829431' seed=22133907207886756657716477388947078929535639477097859186094622625699493413687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22133907207886756657716477388947078929535639477097859186094622625699493413687 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"24.chip_sw_all_escalation_resets.24390288425097771791516058606194940566516617934446010558385075397700500932506","seed":24390288425097771791516058606194940566516617934446010558385075397700500932506,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=459360154 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.459360154' seed=24390288425097771791516058606194940566516617934446010558385075397700500932506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24390288425097771791516058606194940566516617934446010558385075397700500932506 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.22495826615367565823687166819232181756862198232424083612986162467205783103779","seed":22495826615367565823687166819232181756862198232424083612986162467205783103779,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.52928206824880587718133440633203368647357274267636257419648827650889349000911","seed":52928206824880587718133440633203368647357274267636257419648827650889349000911,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531558095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.531558095' seed=52928206824880587718133440633203368647357274267636257419648827650889349000911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52928206824880587718133440633203368647357274267636257419648827650889349000911 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"24.xbar_smoke.36676965447138270407593954180780674041500617703856852368437944747833823509597","seed":36676965447138270407593954180780674041500617703856852368437944747833823509597,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1427291229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1427291229' seed=36676965447138270407593954180780674041500617703856852368437944747833823509597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36676965447138270407593954180780674041500617703856852368437944747833823509597 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"24.xbar_smoke_zero_delays.100636669360581902367862329841730384300561560044179544468948000410267624610698","seed":100636669360581902367862329841730384300561560044179544468948000410267624610698,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=316087178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.316087178' seed=100636669360581902367862329841730384300561560044179544468948000410267624610698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100636669360581902367862329841730384300561560044179544468948000410267624610698 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"24.xbar_smoke_large_delays.32197233853117313998424340315286469771460829291949916247585471700333428950559","seed":32197233853117313998424340315286469771460829291949916247585471700333428950559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1784366623 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1784366623' seed=32197233853117313998424340315286469771460829291949916247585471700333428950559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32197233853117313998424340315286469771460829291949916247585471700333428950559 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"24.xbar_smoke_slow_rsp.68805228689807154590398640567365829576887952425592958295378316792924879324427","seed":68805228689807154590398640567365829576887952425592958295378316792924879324427,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2362574091 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2362574091' seed=68805228689807154590398640567365829576887952425592958295378316792924879324427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68805228689807154590398640567365829576887952425592958295378316792924879324427 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"24.xbar_random.52369387774965420322353759376303033261255111124486983815108461153146331644964","seed":52369387774965420322353759376303033261255111124486983815108461153146331644964,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3870737444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3870737444' seed=52369387774965420322353759376303033261255111124486983815108461153146331644964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52369387774965420322353759376303033261255111124486983815108461153146331644964 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"24.xbar_random_zero_delays.104822428453470447372651910598656061455035419146493535104159961874462517702035","seed":104822428453470447372651910598656061455035419146493535104159961874462517702035,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1610558867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1610558867' seed=104822428453470447372651910598656061455035419146493535104159961874462517702035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104822428453470447372651910598656061455035419146493535104159961874462517702035 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"24.xbar_random_large_delays.21905359900388487011423873574083203550949838997489449261368425477382447967740","seed":21905359900388487011423873574083203550949838997489449261368425477382447967740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=849751548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.849751548' seed=21905359900388487011423873574083203550949838997489449261368425477382447967740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21905359900388487011423873574083203550949838997489449261368425477382447967740 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"24.xbar_random_slow_rsp.81812020764117396438634014020828914044873209095069503442929495679173322440652","seed":81812020764117396438634014020828914044873209095069503442929495679173322440652,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1771405260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1771405260' seed=81812020764117396438634014020828914044873209095069503442929495679173322440652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81812020764117396438634014020828914044873209095069503442929495679173322440652 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"24.xbar_access_same_device.18605218209678379442966855008007259561881893537121937693903486843201992823378","seed":18605218209678379442966855008007259561881893537121937693903486843201992823378,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576309330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1576309330' seed=18605218209678379442966855008007259561881893537121937693903486843201992823378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18605218209678379442966855008007259561881893537121937693903486843201992823378 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"24.xbar_access_same_device_slow_rsp.112719371558448152673664792813347347755990695095466817005197291992203678817740","seed":112719371558448152673664792813347347755990695095466817005197291992203678817740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3280575948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3280575948' seed=112719371558448152673664792813347347755990695095466817005197291992203678817740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112719371558448152673664792813347347755990695095466817005197291992203678817740 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"24.xbar_same_source.10820260955284724436760338912850920720011100603749848498731261859668308310869","seed":10820260955284724436760338912850920720011100603749848498731261859668308310869,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=72399701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.72399701' seed=10820260955284724436760338912850920720011100603749848498731261859668308310869 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10820260955284724436760338912850920720011100603749848498731261859668308310869 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"24.xbar_error_random.83818475793582016711063895098708176258172424620326711229805854722895378936029","seed":83818475793582016711063895098708176258172424620326711229805854722895378936029,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4194857181 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4194857181' seed=83818475793582016711063895098708176258172424620326711229805854722895378936029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83818475793582016711063895098708176258172424620326711229805854722895378936029 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"24.xbar_unmapped_addr.97317112164669016122571767567884509490727282629814883406522494054632947121076","seed":97317112164669016122571767567884509490727282629814883406522494054632947121076,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608869812 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3608869812' seed=97317112164669016122571767567884509490727282629814883406522494054632947121076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97317112164669016122571767567884509490727282629814883406522494054632947121076 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"24.xbar_error_and_unmapped_addr.114480693769428211122435869089427254682266349625776041856727174793922808775703","seed":114480693769428211122435869089427254682266349625776041856727174793922808775703,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2598765591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2598765591' seed=114480693769428211122435869089427254682266349625776041856727174793922808775703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114480693769428211122435869089427254682266349625776041856727174793922808775703 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"24.xbar_stress_all.80517812618929003775343554584213058708452901708488119668641751633762789719454","seed":80517812618929003775343554584213058708452901708488119668641751633762789719454,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3928587678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3928587678' seed=80517812618929003775343554584213058708452901708488119668641751633762789719454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80517812618929003775343554584213058708452901708488119668641751633762789719454 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"24.xbar_stress_all_with_rand_reset.69983485043685057210849659748291563916599868332352798399936590115008212909092","seed":69983485043685057210849659748291563916599868332352798399936590115008212909092,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271072292 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.271072292' seed=69983485043685057210849659748291563916599868332352798399936590115008212909092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69983485043685057210849659748291563916599868332352798399936590115008212909092 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"24.xbar_stress_all_with_error.75641487964990523408847606535882285666316747286793075569418637476687654918471","seed":75641487964990523408847606535882285666316747286793075569418637476687654918471,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4130052423 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4130052423' seed=75641487964990523408847606535882285666316747286793075569418637476687654918471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75641487964990523408847606535882285666316747286793075569418637476687654918471 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"24.xbar_stress_all_with_reset_error.104200773551739098160147394600751479598030938547294488668497784156589312228004","seed":104200773551739098160147394600751479598030938547294488668497784156589312228004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692449444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1692449444' seed=104200773551739098160147394600751479598030938547294488668497784156589312228004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=104200773551739098160147394600751479598030938547294488668497784156589312228004 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"25.chip_sw_all_escalation_resets.14656760392136279699411027779253979348910452608513788213371657612936824209949","seed":14656760392136279699411027779253979348910452608513788213371657612936824209949,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2821177885 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2821177885' seed=14656760392136279699411027779253979348910452608513788213371657612936824209949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14656760392136279699411027779253979348910452608513788213371657612936824209949 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.115669511294252397641468817255088785929489629830922113784746542856752818741934","seed":115669511294252397641468817255088785929489629830922113784746542856752818741934,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.67593841556513993042256174513465255132749822280106323093915362203401404635349","seed":67593841556513993042256174513465255132749822280106323093915362203401404635349,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1924487381 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1924487381' seed=67593841556513993042256174513465255132749822280106323093915362203401404635349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67593841556513993042256174513465255132749822280106323093915362203401404635349 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"25.xbar_smoke.36830248339583603270845226719360480896115568528547724137900514842731642381349","seed":36830248339583603270845226719360480896115568528547724137900514842731642381349,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1106011173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1106011173' seed=36830248339583603270845226719360480896115568528547724137900514842731642381349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36830248339583603270845226719360480896115568528547724137900514842731642381349 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"25.xbar_smoke_zero_delays.75199671389483571441287645536247746678516433411576143496766358446914353189682","seed":75199671389483571441287645536247746678516433411576143496766358446914353189682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870170418 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2870170418' seed=75199671389483571441287645536247746678516433411576143496766358446914353189682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75199671389483571441287645536247746678516433411576143496766358446914353189682 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"25.xbar_smoke_large_delays.58251107412427094758540658657993373090321616278662934557259838378874120058662","seed":58251107412427094758540658657993373090321616278662934557259838378874120058662,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1969895206 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1969895206' seed=58251107412427094758540658657993373090321616278662934557259838378874120058662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58251107412427094758540658657993373090321616278662934557259838378874120058662 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"25.xbar_smoke_slow_rsp.12189936172244113399649917877392171627702905799317092007194895809384566530118","seed":12189936172244113399649917877392171627702905799317092007194895809384566530118,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840554054 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1840554054' seed=12189936172244113399649917877392171627702905799317092007194895809384566530118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12189936172244113399649917877392171627702905799317092007194895809384566530118 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"25.xbar_random.112404986879683777707594829866282500619346599916197994879086170591959659743152","seed":112404986879683777707594829866282500619346599916197994879086170591959659743152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=302417840 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.302417840' seed=112404986879683777707594829866282500619346599916197994879086170591959659743152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112404986879683777707594829866282500619346599916197994879086170591959659743152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"25.xbar_random_zero_delays.112500696079361931553985460551687894732570226692880574763812371446458887610303","seed":112500696079361931553985460551687894732570226692880574763812371446458887610303,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287481791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.287481791' seed=112500696079361931553985460551687894732570226692880574763812371446458887610303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112500696079361931553985460551687894732570226692880574763812371446458887610303 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"25.xbar_random_large_delays.6645286640131932044382211044030809638849345188508463532490027632215528463158","seed":6645286640131932044382211044030809638849345188508463532490027632215528463158,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=534141750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.534141750' seed=6645286640131932044382211044030809638849345188508463532490027632215528463158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6645286640131932044382211044030809638849345188508463532490027632215528463158 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"25.xbar_random_slow_rsp.69316208365127960253863714518647773834353852842969805716120498436202031590669","seed":69316208365127960253863714518647773834353852842969805716120498436202031590669,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3366563085 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3366563085' seed=69316208365127960253863714518647773834353852842969805716120498436202031590669 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69316208365127960253863714518647773834353852842969805716120498436202031590669 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"25.xbar_access_same_device.8798071082423206325329755708344722625299869895120505792727955682497024792825","seed":8798071082423206325329755708344722625299869895120505792727955682497024792825,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=506763513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.506763513' seed=8798071082423206325329755708344722625299869895120505792727955682497024792825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8798071082423206325329755708344722625299869895120505792727955682497024792825 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"25.xbar_access_same_device_slow_rsp.2557707901941182834967459796346713435368202116024478196373618421854529323773","seed":2557707901941182834967459796346713435368202116024478196373618421854529323773,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=633537277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.633537277' seed=2557707901941182834967459796346713435368202116024478196373618421854529323773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2557707901941182834967459796346713435368202116024478196373618421854529323773 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"25.xbar_same_source.50309691735425070171360123467127354063949063508386797978977749448075053739339","seed":50309691735425070171360123467127354063949063508386797978977749448075053739339,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336702795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.336702795' seed=50309691735425070171360123467127354063949063508386797978977749448075053739339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50309691735425070171360123467127354063949063508386797978977749448075053739339 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"25.xbar_error_random.101944230474309431259166168773869010473797079826472036176372704054732632546104","seed":101944230474309431259166168773869010473797079826472036176372704054732632546104,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3226393400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3226393400' seed=101944230474309431259166168773869010473797079826472036176372704054732632546104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101944230474309431259166168773869010473797079826472036176372704054732632546104 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"25.xbar_unmapped_addr.46027207836963074266380004438770099329127838138661989074158274044472668533880","seed":46027207836963074266380004438770099329127838138661989074158274044472668533880,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=621360248 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.621360248' seed=46027207836963074266380004438770099329127838138661989074158274044472668533880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46027207836963074266380004438770099329127838138661989074158274044472668533880 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"25.xbar_error_and_unmapped_addr.60235625258177812879272391165786488096778264319297180061082734393231616488712","seed":60235625258177812879272391165786488096778264319297180061082734393231616488712,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518398216 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2518398216' seed=60235625258177812879272391165786488096778264319297180061082734393231616488712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60235625258177812879272391165786488096778264319297180061082734393231616488712 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"25.xbar_stress_all.50326150186482795808424802960551103100443675362927066775459620143453392730773","seed":50326150186482795808424802960551103100443675362927066775459620143453392730773,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2582510229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2582510229' seed=50326150186482795808424802960551103100443675362927066775459620143453392730773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50326150186482795808424802960551103100443675362927066775459620143453392730773 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"25.xbar_stress_all_with_rand_reset.93674747990731064440482600364675209256353689905500048963957734026884713144553","seed":93674747990731064440482600364675209256353689905500048963957734026884713144553,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416121577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.3416121577' seed=93674747990731064440482600364675209256353689905500048963957734026884713144553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93674747990731064440482600364675209256353689905500048963957734026884713144553 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"25.xbar_stress_all_with_error.21000483498021410420467375342080649474590093656747145535064866784860917389233","seed":21000483498021410420467375342080649474590093656747145535064866784860917389233,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1443551153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1443551153' seed=21000483498021410420467375342080649474590093656747145535064866784860917389233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21000483498021410420467375342080649474590093656747145535064866784860917389233 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"25.xbar_stress_all_with_reset_error.91055347126727684134629691610295450016897202480617110393819547051545263157968","seed":91055347126727684134629691610295450016897202480617110393819547051545263157968,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=63517392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.63517392' seed=91055347126727684134629691610295450016897202480617110393819547051545263157968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91055347126727684134629691610295450016897202480617110393819547051545263157968 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"26.chip_sw_all_escalation_resets.81851354871273091183298667117122724168782861871141022354470655341229775732216","seed":81851354871273091183298667117122724168782861871141022354470655341229775732216,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3763027448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3763027448' seed=81851354871273091183298667117122724168782861871141022354470655341229775732216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81851354871273091183298667117122724168782861871141022354470655341229775732216 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.87460058038895269754938364400511776401141448664256197659409199552932479253120","seed":87460058038895269754938364400511776401141448664256197659409199552932479253120,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.112703305197576347845205057565084652245489850816360313354294861722364061700768","seed":112703305197576347845205057565084652245489850816360313354294861722364061700768,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691008672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3691008672' seed=112703305197576347845205057565084652245489850816360313354294861722364061700768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112703305197576347845205057565084652245489850816360313354294861722364061700768 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"26.xbar_smoke.14666185406104520902208177565838384001107701734003145381381265150748239276815","seed":14666185406104520902208177565838384001107701734003145381381265150748239276815,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034889999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1034889999' seed=14666185406104520902208177565838384001107701734003145381381265150748239276815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14666185406104520902208177565838384001107701734003145381381265150748239276815 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"26.xbar_smoke_zero_delays.54214804222984574464125520856253762978683253444978167372054441538652751541101","seed":54214804222984574464125520856253762978683253444978167372054441538652751541101,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3732157293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3732157293' seed=54214804222984574464125520856253762978683253444978167372054441538652751541101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54214804222984574464125520856253762978683253444978167372054441538652751541101 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"26.xbar_smoke_large_delays.9015680374395354101342932431376561381530624495530168330021898965459196360656","seed":9015680374395354101342932431376561381530624495530168330021898965459196360656,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3929192400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3929192400' seed=9015680374395354101342932431376561381530624495530168330021898965459196360656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9015680374395354101342932431376561381530624495530168330021898965459196360656 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"26.xbar_smoke_slow_rsp.107583327963345578868428921248386423559704610474459423302344790277132233110806","seed":107583327963345578868428921248386423559704610474459423302344790277132233110806,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1795061014 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1795061014' seed=107583327963345578868428921248386423559704610474459423302344790277132233110806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107583327963345578868428921248386423559704610474459423302344790277132233110806 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"26.xbar_random.95327428787114237049321496477539827468729127250556048745719524242423538916224","seed":95327428787114237049321496477539827468729127250556048745719524242423538916224,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025200512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2025200512' seed=95327428787114237049321496477539827468729127250556048745719524242423538916224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95327428787114237049321496477539827468729127250556048745719524242423538916224 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"26.xbar_random_zero_delays.16101057237441086673103764056693944678658114784986957818062447019379029401354","seed":16101057237441086673103764056693944678658114784986957818062447019379029401354,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289103626 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.289103626' seed=16101057237441086673103764056693944678658114784986957818062447019379029401354 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16101057237441086673103764056693944678658114784986957818062447019379029401354 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"26.xbar_random_large_delays.91782823729870118116914800621027104276381015659162133573522562808094425167896","seed":91782823729870118116914800621027104276381015659162133573522562808094425167896,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3019192344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3019192344' seed=91782823729870118116914800621027104276381015659162133573522562808094425167896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91782823729870118116914800621027104276381015659162133573522562808094425167896 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"26.xbar_random_slow_rsp.48830968774278314024167857405320600931558065075093267099607629233688343108630","seed":48830968774278314024167857405320600931558065075093267099607629233688343108630,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2606914582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2606914582' seed=48830968774278314024167857405320600931558065075093267099607629233688343108630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48830968774278314024167857405320600931558065075093267099607629233688343108630 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"26.xbar_access_same_device.31057296743494851604275808429937724137624099474820713570568341802427719237224","seed":31057296743494851604275808429937724137624099474820713570568341802427719237224,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1588739688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1588739688' seed=31057296743494851604275808429937724137624099474820713570568341802427719237224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31057296743494851604275808429937724137624099474820713570568341802427719237224 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"26.xbar_access_same_device_slow_rsp.4487322657833950249386475231949196583681131611930163180059520886072818718100","seed":4487322657833950249386475231949196583681131611930163180059520886072818718100,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394950548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.3394950548' seed=4487322657833950249386475231949196583681131611930163180059520886072818718100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4487322657833950249386475231949196583681131611930163180059520886072818718100 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"26.xbar_same_source.24686032376987072209149285474040701079810684990913920682417417321455431580867","seed":24686032376987072209149285474040701079810684990913920682417417321455431580867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1414134979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1414134979' seed=24686032376987072209149285474040701079810684990913920682417417321455431580867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24686032376987072209149285474040701079810684990913920682417417321455431580867 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"26.xbar_error_random.21960129020794287254085542825911465498971333554343094746894802919865484826205","seed":21960129020794287254085542825911465498971333554343094746894802919865484826205,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3637237341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3637237341' seed=21960129020794287254085542825911465498971333554343094746894802919865484826205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21960129020794287254085542825911465498971333554343094746894802919865484826205 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"26.xbar_unmapped_addr.52595628707185341990039481152013101129599514858202857021135531488785321262906","seed":52595628707185341990039481152013101129599514858202857021135531488785321262906,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218726202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.218726202' seed=52595628707185341990039481152013101129599514858202857021135531488785321262906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52595628707185341990039481152013101129599514858202857021135531488785321262906 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"26.xbar_error_and_unmapped_addr.115191683831005693126890817217235230375403228651867337836337107076979959853138","seed":115191683831005693126890817217235230375403228651867337836337107076979959853138,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4031049810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.4031049810' seed=115191683831005693126890817217235230375403228651867337836337107076979959853138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=115191683831005693126890817217235230375403228651867337836337107076979959853138 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"26.xbar_stress_all.51041820066765141525408143317440415454696063719514711435977015695402699544351","seed":51041820066765141525408143317440415454696063719514711435977015695402699544351,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2349291295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2349291295' seed=51041820066765141525408143317440415454696063719514711435977015695402699544351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51041820066765141525408143317440415454696063719514711435977015695402699544351 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"26.xbar_stress_all_with_rand_reset.3731008591006732003605940040849210834947551245312712158149083199675229587014","seed":3731008591006732003605940040849210834947551245312712158149083199675229587014,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2339423814 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2339423814' seed=3731008591006732003605940040849210834947551245312712158149083199675229587014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3731008591006732003605940040849210834947551245312712158149083199675229587014 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"26.xbar_stress_all_with_error.95880476832363900871667793069881021756057115426119077970642418612790953143868","seed":95880476832363900871667793069881021756057115426119077970642418612790953143868,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2805624380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2805624380' seed=95880476832363900871667793069881021756057115426119077970642418612790953143868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95880476832363900871667793069881021756057115426119077970642418612790953143868 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"26.xbar_stress_all_with_reset_error.106269344166467186735208227117648348400018319083221378184287241892433156946065","seed":106269344166467186735208227117648348400018319083221378184287241892433156946065,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1447606417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.1447606417' seed=106269344166467186735208227117648348400018319083221378184287241892433156946065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106269344166467186735208227117648348400018319083221378184287241892433156946065 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"27.chip_sw_all_escalation_resets.58190464709605658703551233040296536021928164432726686982087522119448911944489","seed":58190464709605658703551233040296536021928164432726686982087522119448911944489,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507414313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2507414313' seed=58190464709605658703551233040296536021928164432726686982087522119448911944489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58190464709605658703551233040296536021928164432726686982087522119448911944489 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.40382934959504209868219716857604128916852795402971772443785659505208243777789","seed":40382934959504209868219716857604128916852795402971772443785659505208243777789,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.9635458738148007606413653037484597447706743049571008739840247808905301381840","seed":9635458738148007606413653037484597447706743049571008739840247808905301381840,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2494223056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2494223056' seed=9635458738148007606413653037484597447706743049571008739840247808905301381840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9635458738148007606413653037484597447706743049571008739840247808905301381840 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"27.xbar_smoke.55065814505053527266593554028903401149818285611048681466309034692327272550496","seed":55065814505053527266593554028903401149818285611048681466309034692327272550496,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3078033504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3078033504' seed=55065814505053527266593554028903401149818285611048681466309034692327272550496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55065814505053527266593554028903401149818285611048681466309034692327272550496 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"27.xbar_smoke_zero_delays.50478392637727181818285862120006447229861056442967637203530204707631373352216","seed":50478392637727181818285862120006447229861056442967637203530204707631373352216,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498728216 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.498728216' seed=50478392637727181818285862120006447229861056442967637203530204707631373352216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50478392637727181818285862120006447229861056442967637203530204707631373352216 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"27.xbar_smoke_large_delays.14032134314279502920063669809295070618397567073523448123659521891454898971269","seed":14032134314279502920063669809295070618397567073523448123659521891454898971269,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=836543109 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.836543109' seed=14032134314279502920063669809295070618397567073523448123659521891454898971269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14032134314279502920063669809295070618397567073523448123659521891454898971269 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"27.xbar_smoke_slow_rsp.10068241038782914766931228358989620304359353836657582506997403717272196335747","seed":10068241038782914766931228358989620304359353836657582506997403717272196335747,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3047671939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3047671939' seed=10068241038782914766931228358989620304359353836657582506997403717272196335747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10068241038782914766931228358989620304359353836657582506997403717272196335747 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"27.xbar_random.23643269997842498903348100177722770902497125471544636888434799738672260809290","seed":23643269997842498903348100177722770902497125471544636888434799738672260809290,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412216906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2412216906' seed=23643269997842498903348100177722770902497125471544636888434799738672260809290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23643269997842498903348100177722770902497125471544636888434799738672260809290 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"27.xbar_random_zero_delays.78562237199228180256514758356180364829215663717233199054949699931889109807867","seed":78562237199228180256514758356180364829215663717233199054949699931889109807867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271902971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1271902971' seed=78562237199228180256514758356180364829215663717233199054949699931889109807867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78562237199228180256514758356180364829215663717233199054949699931889109807867 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"27.xbar_random_large_delays.58490283224479953146623241394681022889264473888776778825459996582952141055796","seed":58490283224479953146623241394681022889264473888776778825459996582952141055796,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1333782324 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1333782324' seed=58490283224479953146623241394681022889264473888776778825459996582952141055796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58490283224479953146623241394681022889264473888776778825459996582952141055796 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"27.xbar_random_slow_rsp.75784111514280954758174582349020344216975875881985945089709887275241287012119","seed":75784111514280954758174582349020344216975875881985945089709887275241287012119,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179106071 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3179106071' seed=75784111514280954758174582349020344216975875881985945089709887275241287012119 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=75784111514280954758174582349020344216975875881985945089709887275241287012119 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"27.xbar_access_same_device.91106148949717762373665179541727624921608183451482192206606354160620957417920","seed":91106148949717762373665179541727624921608183451482192206606354160620957417920,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=152125888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.152125888' seed=91106148949717762373665179541727624921608183451482192206606354160620957417920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91106148949717762373665179541727624921608183451482192206606354160620957417920 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"27.xbar_access_same_device_slow_rsp.83533694734984440157039689997807376484013086242319883765371126908925090017638","seed":83533694734984440157039689997807376484013086242319883765371126908925090017638,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2078093670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2078093670' seed=83533694734984440157039689997807376484013086242319883765371126908925090017638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83533694734984440157039689997807376484013086242319883765371126908925090017638 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"27.xbar_same_source.86536605841513411610648051875702703170566423291415339721563335781823486483894","seed":86536605841513411610648051875702703170566423291415339721563335781823486483894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132322230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1132322230' seed=86536605841513411610648051875702703170566423291415339721563335781823486483894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86536605841513411610648051875702703170566423291415339721563335781823486483894 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"27.xbar_error_random.96111556522809874096685140247114550343451722139767633828658298543090920385674","seed":96111556522809874096685140247114550343451722139767633828658298543090920385674,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1107094666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1107094666' seed=96111556522809874096685140247114550343451722139767633828658298543090920385674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96111556522809874096685140247114550343451722139767633828658298543090920385674 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"27.xbar_unmapped_addr.2981032658024808554917935235623417204254988196646830053770943980597049324559","seed":2981032658024808554917935235623417204254988196646830053770943980597049324559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31749135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.31749135' seed=2981032658024808554917935235623417204254988196646830053770943980597049324559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2981032658024808554917935235623417204254988196646830053770943980597049324559 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"27.xbar_error_and_unmapped_addr.66650795267338717182505292815553560002028157243882589035696516805315362116678","seed":66650795267338717182505292815553560002028157243882589035696516805315362116678,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1022448710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1022448710' seed=66650795267338717182505292815553560002028157243882589035696516805315362116678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66650795267338717182505292815553560002028157243882589035696516805315362116678 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"27.xbar_stress_all.110300818492012978629275317670675278417433168772524049849223934779049714675245","seed":110300818492012978629275317670675278417433168772524049849223934779049714675245,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2742316589 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2742316589' seed=110300818492012978629275317670675278417433168772524049849223934779049714675245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110300818492012978629275317670675278417433168772524049849223934779049714675245 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"27.xbar_stress_all_with_rand_reset.80809659910497225892770213409784197582937126476109830114575409943103144429574","seed":80809659910497225892770213409784197582937126476109830114575409943103144429574,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1944553478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1944553478' seed=80809659910497225892770213409784197582937126476109830114575409943103144429574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80809659910497225892770213409784197582937126476109830114575409943103144429574 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"27.xbar_stress_all_with_error.88959118792453851930382515297909985683165512936010155207041948275036362892494","seed":88959118792453851930382515297909985683165512936010155207041948275036362892494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1898702030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1898702030' seed=88959118792453851930382515297909985683165512936010155207041948275036362892494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88959118792453851930382515297909985683165512936010155207041948275036362892494 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"27.xbar_stress_all_with_reset_error.106035513769955355293893612327707339428582925783831598210410760564229492009301","seed":106035513769955355293893612327707339428582925783831598210410760564229492009301,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3139791189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3139791189' seed=106035513769955355293893612327707339428582925783831598210410760564229492009301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106035513769955355293893612327707339428582925783831598210410760564229492009301 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"28.chip_sw_all_escalation_resets.73289508851369206389500024982949468764767220132612519533993407106624071497277","seed":73289508851369206389500024982949468764767220132612519533993407106624071497277,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646018621 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.646018621' seed=73289508851369206389500024982949468764767220132612519533993407106624071497277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73289508851369206389500024982949468764767220132612519533993407106624071497277 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.98589869206080543210815133546213169745704241210160638203054622117586120724227","seed":98589869206080543210815133546213169745704241210160638203054622117586120724227,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.72960633628302655435917220627015013653134054776730543920594864307679924217273","seed":72960633628302655435917220627015013653134054776730543920594864307679924217273,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4069418425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.4069418425' seed=72960633628302655435917220627015013653134054776730543920594864307679924217273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72960633628302655435917220627015013653134054776730543920594864307679924217273 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"28.xbar_smoke.35020801436584760938492251067100768662367662073356413591092976399294415926917","seed":35020801436584760938492251067100768662367662073356413591092976399294415926917,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3874125445 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3874125445' seed=35020801436584760938492251067100768662367662073356413591092976399294415926917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35020801436584760938492251067100768662367662073356413591092976399294415926917 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"28.xbar_smoke_zero_delays.36562936265865692328779745749479959572193219411503234376625198562575957834843","seed":36562936265865692328779745749479959572193219411503234376625198562575957834843,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3318430811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3318430811' seed=36562936265865692328779745749479959572193219411503234376625198562575957834843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36562936265865692328779745749479959572193219411503234376625198562575957834843 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"28.xbar_smoke_large_delays.80490499545690273194303015538921810926861144193557520794389860349894663534527","seed":80490499545690273194303015538921810926861144193557520794389860349894663534527,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2771056575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2771056575' seed=80490499545690273194303015538921810926861144193557520794389860349894663534527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80490499545690273194303015538921810926861144193557520794389860349894663534527 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"28.xbar_smoke_slow_rsp.114808909462944457292296529047306235698040519920728048967595110996737232347608","seed":114808909462944457292296529047306235698040519920728048967595110996737232347608,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2982289880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2982289880' seed=114808909462944457292296529047306235698040519920728048967595110996737232347608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114808909462944457292296529047306235698040519920728048967595110996737232347608 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"28.xbar_random.33005300495934586576228640445597698465652821188068616145218761885274750845882","seed":33005300495934586576228640445597698465652821188068616145218761885274750845882,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2498233274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2498233274' seed=33005300495934586576228640445597698465652821188068616145218761885274750845882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33005300495934586576228640445597698465652821188068616145218761885274750845882 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"28.xbar_random_zero_delays.93188418335879266780174093569284804444806111231371398583575731044901937446380","seed":93188418335879266780174093569284804444806111231371398583575731044901937446380,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1288928748 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1288928748' seed=93188418335879266780174093569284804444806111231371398583575731044901937446380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93188418335879266780174093569284804444806111231371398583575731044901937446380 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"28.xbar_random_large_delays.42088900327723112903178950318482972851169466492949777808360449601436106682784","seed":42088900327723112903178950318482972851169466492949777808360449601436106682784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2152001952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2152001952' seed=42088900327723112903178950318482972851169466492949777808360449601436106682784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42088900327723112903178950318482972851169466492949777808360449601436106682784 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"28.xbar_random_slow_rsp.90986770996546031779581351058596058669632773345579330338135129647253000942717","seed":90986770996546031779581351058596058669632773345579330338135129647253000942717,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=339080317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.339080317' seed=90986770996546031779581351058596058669632773345579330338135129647253000942717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90986770996546031779581351058596058669632773345579330338135129647253000942717 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"28.xbar_access_same_device.46504784663000485932096729883099251861746032127215684833919855339199658079886","seed":46504784663000485932096729883099251861746032127215684833919855339199658079886,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2024945294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2024945294' seed=46504784663000485932096729883099251861746032127215684833919855339199658079886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46504784663000485932096729883099251861746032127215684833919855339199658079886 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"28.xbar_access_same_device_slow_rsp.74542291066093269400425543147657030168505732222309516421869840786784845771454","seed":74542291066093269400425543147657030168505732222309516421869840786784845771454,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854695614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2854695614' seed=74542291066093269400425543147657030168505732222309516421869840786784845771454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74542291066093269400425543147657030168505732222309516421869840786784845771454 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"28.xbar_same_source.92990862804460257166652005894716537586446571941699310313722385169722556433187","seed":92990862804460257166652005894716537586446571941699310313722385169722556433187,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1658733347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1658733347' seed=92990862804460257166652005894716537586446571941699310313722385169722556433187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92990862804460257166652005894716537586446571941699310313722385169722556433187 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"28.xbar_error_random.5890987361398043043429775670898277377588127172126684605632822715909706261646","seed":5890987361398043043429775670898277377588127172126684605632822715909706261646,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2283447438 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2283447438' seed=5890987361398043043429775670898277377588127172126684605632822715909706261646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5890987361398043043429775670898277377588127172126684605632822715909706261646 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"28.xbar_unmapped_addr.49828159082003766966505381670936584524912517329870228497545476360854025418727","seed":49828159082003766966505381670936584524912517329870228497545476360854025418727,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852089319 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3852089319' seed=49828159082003766966505381670936584524912517329870228497545476360854025418727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49828159082003766966505381670936584524912517329870228497545476360854025418727 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"28.xbar_error_and_unmapped_addr.40402442417503894419396673177312809919979944202919810248989099390488113176258","seed":40402442417503894419396673177312809919979944202919810248989099390488113176258,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818091202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1818091202' seed=40402442417503894419396673177312809919979944202919810248989099390488113176258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40402442417503894419396673177312809919979944202919810248989099390488113176258 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"28.xbar_stress_all.78777984345905235867951571229922735290924721593755313006163349227785585452022","seed":78777984345905235867951571229922735290924721593755313006163349227785585452022,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=921723894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.921723894' seed=78777984345905235867951571229922735290924721593755313006163349227785585452022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78777984345905235867951571229922735290924721593755313006163349227785585452022 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"28.xbar_stress_all_with_rand_reset.36149086334794475908475633346931266090594100265892372051781469283587169865004","seed":36149086334794475908475633346931266090594100265892372051781469283587169865004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1109544236 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1109544236' seed=36149086334794475908475633346931266090594100265892372051781469283587169865004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36149086334794475908475633346931266090594100265892372051781469283587169865004 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"28.xbar_stress_all_with_error.724054543016010575933881667541696354534163053899373879214943569135984687581","seed":724054543016010575933881667541696354534163053899373879214943569135984687581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=626768349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.626768349' seed=724054543016010575933881667541696354534163053899373879214943569135984687581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=724054543016010575933881667541696354534163053899373879214943569135984687581 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"28.xbar_stress_all_with_reset_error.85471345976148738112708926021346347574629375582486435813743188580490136924647","seed":85471345976148738112708926021346347574629375582486435813743188580490136924647,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1049244135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1049244135' seed=85471345976148738112708926021346347574629375582486435813743188580490136924647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85471345976148738112708926021346347574629375582486435813743188580490136924647 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"29.chip_sw_all_escalation_resets.94116326467180912266267767726893694236927101876012332566546800045101430380409","seed":94116326467180912266267767726893694236927101876012332566546800045101430380409,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491010425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3491010425' seed=94116326467180912266267767726893694236927101876012332566546800045101430380409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94116326467180912266267767726893694236927101876012332566546800045101430380409 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.97374427175515016628868361222617975714565497923427383749031466734225196634204","seed":97374427175515016628868361222617975714565497923427383749031466734225196634204,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.3624406705410885607094929678168039367602147426838554475627435487763618091431","seed":3624406705410885607094929678168039367602147426838554475627435487763618091431,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_tl_errors/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_tl_errors/latest run_opts='+run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3041415591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3041415591' seed=3624406705410885607094929678168039367602147426838554475627435487763618091431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3624406705410885607094929678168039367602147426838554475627435487763618091431 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_tl_errors/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"29.xbar_smoke.26447081900195257292261698854002143652998733489831687538778045057307454663386","seed":26447081900195257292261698854002143652998733489831687538778045057307454663386,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3733383898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3733383898' seed=26447081900195257292261698854002143652998733489831687538778045057307454663386 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26447081900195257292261698854002143652998733489831687538778045057307454663386 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"29.xbar_smoke_zero_delays.109659916867955387335744309739914492887643108486232223946231469713062265582789","seed":109659916867955387335744309739914492887643108486232223946231469713062265582789,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1412396229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1412396229' seed=109659916867955387335744309739914492887643108486232223946231469713062265582789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109659916867955387335744309739914492887643108486232223946231469713062265582789 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"29.xbar_smoke_large_delays.100617395737697058619721571328347030630088515959747474480934773002478663524917","seed":100617395737697058619721571328347030630088515959747474480934773002478663524917,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618581557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2618581557' seed=100617395737697058619721571328347030630088515959747474480934773002478663524917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100617395737697058619721571328347030630088515959747474480934773002478663524917 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"29.xbar_smoke_slow_rsp.12857435025154167617206330699662869421214573534996070188816845338824083395033","seed":12857435025154167617206330699662869421214573534996070188816845338824083395033,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3063304665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3063304665' seed=12857435025154167617206330699662869421214573534996070188816845338824083395033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12857435025154167617206330699662869421214573534996070188816845338824083395033 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"29.xbar_random.28263865662494895387420666501368142622422440441590076742928186551737554622622","seed":28263865662494895387420666501368142622422440441590076742928186551737554622622,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3949779102 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3949779102' seed=28263865662494895387420666501368142622422440441590076742928186551737554622622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28263865662494895387420666501368142622422440441590076742928186551737554622622 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"29.xbar_random_zero_delays.100567013256183893266610632688154820964011432452622676690991569581533065870761","seed":100567013256183893266610632688154820964011432452622676690991569581533065870761,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3495919017 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3495919017' seed=100567013256183893266610632688154820964011432452622676690991569581533065870761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100567013256183893266610632688154820964011432452622676690991569581533065870761 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"29.xbar_random_large_delays.49245182783752816396093799975709780215783296830535562161398808678787520681428","seed":49245182783752816396093799975709780215783296830535562161398808678787520681428,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2779272660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2779272660' seed=49245182783752816396093799975709780215783296830535562161398808678787520681428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49245182783752816396093799975709780215783296830535562161398808678787520681428 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"29.xbar_random_slow_rsp.103779955543477029425128964856907836801743961280634690036484875503850874424876","seed":103779955543477029425128964856907836801743961280634690036484875503850874424876,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1751862828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1751862828' seed=103779955543477029425128964856907836801743961280634690036484875503850874424876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103779955543477029425128964856907836801743961280634690036484875503850874424876 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"29.xbar_access_same_device.3915497890838660707807732375387879193009624874737752088064255978862932063595","seed":3915497890838660707807732375387879193009624874737752088064255978862932063595,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=588445035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.588445035' seed=3915497890838660707807732375387879193009624874737752088064255978862932063595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3915497890838660707807732375387879193009624874737752088064255978862932063595 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"29.xbar_access_same_device_slow_rsp.54123592518811255497453886434557487622116847798399232547091615233807538696157","seed":54123592518811255497453886434557487622116847798399232547091615233807538696157,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2559815645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2559815645' seed=54123592518811255497453886434557487622116847798399232547091615233807538696157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54123592518811255497453886434557487622116847798399232547091615233807538696157 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"29.xbar_same_source.24269058273355516692035288484194098202717211401872938251293355361303201125047","seed":24269058273355516692035288484194098202717211401872938251293355361303201125047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=982323895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.982323895' seed=24269058273355516692035288484194098202717211401872938251293355361303201125047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24269058273355516692035288484194098202717211401872938251293355361303201125047 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"29.xbar_error_random.71458925091939960501150679454834696774319270653609541054297273855005697291031","seed":71458925091939960501150679454834696774319270653609541054297273855005697291031,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3427840791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3427840791' seed=71458925091939960501150679454834696774319270653609541054297273855005697291031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71458925091939960501150679454834696774319270653609541054297273855005697291031 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"29.xbar_unmapped_addr.41750358529486772855170870302033374769475787825776939881240200423009417320276","seed":41750358529486772855170870302033374769475787825776939881240200423009417320276,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1719818068 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1719818068' seed=41750358529486772855170870302033374769475787825776939881240200423009417320276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=41750358529486772855170870302033374769475787825776939881240200423009417320276 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"29.xbar_error_and_unmapped_addr.2289379497323205140640771603616899742671739010404962074673237532424176371482","seed":2289379497323205140640771603616899742671739010404962074673237532424176371482,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1070565146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1070565146' seed=2289379497323205140640771603616899742671739010404962074673237532424176371482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2289379497323205140640771603616899742671739010404962074673237532424176371482 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"29.xbar_stress_all.42549894478374804674696853613191923447411610834194319088726833683873594722106","seed":42549894478374804674696853613191923447411610834194319088726833683873594722106,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271435578 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.271435578' seed=42549894478374804674696853613191923447411610834194319088726833683873594722106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42549894478374804674696853613191923447411610834194319088726833683873594722106 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"29.xbar_stress_all_with_rand_reset.15395348452538470810956411546446898204146470275842880269745419764796523220294","seed":15395348452538470810956411546446898204146470275842880269745419764796523220294,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=304024902 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.304024902' seed=15395348452538470810956411546446898204146470275842880269745419764796523220294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15395348452538470810956411546446898204146470275842880269745419764796523220294 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"29.xbar_stress_all_with_error.58384569400770675001294725993013564554087878795066463527114632204986851335528","seed":58384569400770675001294725993013564554087878795066463527114632204986851335528,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540248424 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2540248424' seed=58384569400770675001294725993013564554087878795066463527114632204986851335528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58384569400770675001294725993013564554087878795066463527114632204986851335528 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"29.xbar_stress_all_with_reset_error.103150713881172079681682409999271265586383971157044152760797552798040516634845","seed":103150713881172079681682409999271265586383971157044152760797552798040516634845,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1524279517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.1524279517' seed=103150713881172079681682409999271265586383971157044152760797552798040516634845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103150713881172079681682409999271265586383971157044152760797552798040516634845 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"30.chip_sw_all_escalation_resets.13483395043889710761814672945347664683299067150453302702537384113702837260636","seed":13483395043889710761814672945347664683299067150453302702537384113702837260636,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014862172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1014862172' seed=13483395043889710761814672945347664683299067150453302702537384113702837260636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13483395043889710761814672945347664683299067150453302702537384113702837260636 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.38724300932181000365631200041696761315627992287872316002189198054492750774832","seed":38724300932181000365631200041696761315627992287872316002189198054492750774832,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"30.xbar_smoke.17410725111825305490663011948584880459817976163206430653989377899188175615168","seed":17410725111825305490663011948584880459817976163206430653989377899188175615168,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710680768 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2710680768' seed=17410725111825305490663011948584880459817976163206430653989377899188175615168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17410725111825305490663011948584880459817976163206430653989377899188175615168 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"30.xbar_smoke_zero_delays.67519279743548249731561753426432908411815857542272217858007801051313788522677","seed":67519279743548249731561753426432908411815857542272217858007801051313788522677,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=775262389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.775262389' seed=67519279743548249731561753426432908411815857542272217858007801051313788522677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67519279743548249731561753426432908411815857542272217858007801051313788522677 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"30.xbar_smoke_large_delays.11486953390038659848238959723637634434215894280607468606019313761540589639722","seed":11486953390038659848238959723637634434215894280607468606019313761540589639722,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244813354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1244813354' seed=11486953390038659848238959723637634434215894280607468606019313761540589639722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11486953390038659848238959723637634434215894280607468606019313761540589639722 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"30.xbar_smoke_slow_rsp.79611722992295859142445194887924836325459118244715035293421472915335415020060","seed":79611722992295859142445194887924836325459118244715035293421472915335415020060,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292033052 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4292033052' seed=79611722992295859142445194887924836325459118244715035293421472915335415020060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79611722992295859142445194887924836325459118244715035293421472915335415020060 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"30.xbar_random.4273481502055551997807410231679286796562223282490583673407335372833625153650","seed":4273481502055551997807410231679286796562223282490583673407335372833625153650,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1361518706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1361518706' seed=4273481502055551997807410231679286796562223282490583673407335372833625153650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4273481502055551997807410231679286796562223282490583673407335372833625153650 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"30.xbar_random_zero_delays.6159251630116214387079918646277185517679202016217183300427226746978768948152","seed":6159251630116214387079918646277185517679202016217183300427226746978768948152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652619192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3652619192' seed=6159251630116214387079918646277185517679202016217183300427226746978768948152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6159251630116214387079918646277185517679202016217183300427226746978768948152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"30.xbar_random_large_delays.997131000712469869501998832265225119938663047477471026393303836241233290349","seed":997131000712469869501998832265225119938663047477471026393303836241233290349,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1885185133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1885185133' seed=997131000712469869501998832265225119938663047477471026393303836241233290349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=997131000712469869501998832265225119938663047477471026393303836241233290349 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"30.xbar_random_slow_rsp.52374680628683926510972068024136555538830832542463610063665427219833308743408","seed":52374680628683926510972068024136555538830832542463610063665427219833308743408,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=461539056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.461539056' seed=52374680628683926510972068024136555538830832542463610063665427219833308743408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52374680628683926510972068024136555538830832542463610063665427219833308743408 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"30.xbar_access_same_device.12056530112243570110460475026044198915009480106108981632451506800284146158344","seed":12056530112243570110460475026044198915009480106108981632451506800284146158344,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=835013384 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.835013384' seed=12056530112243570110460475026044198915009480106108981632451506800284146158344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12056530112243570110460475026044198915009480106108981632451506800284146158344 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"30.xbar_access_same_device_slow_rsp.111241688017493771061557811629210714784311051881514270006824224257940136638839","seed":111241688017493771061557811629210714784311051881514270006824224257940136638839,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1804056951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.1804056951' seed=111241688017493771061557811629210714784311051881514270006824224257940136638839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111241688017493771061557811629210714784311051881514270006824224257940136638839 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"30.xbar_same_source.94627490038047549992573115349758520932942606634564953844903408817837179216437","seed":94627490038047549992573115349758520932942606634564953844903408817837179216437,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2368021045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2368021045' seed=94627490038047549992573115349758520932942606634564953844903408817837179216437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94627490038047549992573115349758520932942606634564953844903408817837179216437 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"30.xbar_error_random.17930461788488523317479148984322482533749249693555326770444805954148036551735","seed":17930461788488523317479148984322482533749249693555326770444805954148036551735,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=933798967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.933798967' seed=17930461788488523317479148984322482533749249693555326770444805954148036551735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17930461788488523317479148984322482533749249693555326770444805954148036551735 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"30.xbar_unmapped_addr.35502580776853583965605491215130617229094712697829730030897104473993973439473","seed":35502580776853583965605491215130617229094712697829730030897104473993973439473,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2167512049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2167512049' seed=35502580776853583965605491215130617229094712697829730030897104473993973439473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35502580776853583965605491215130617229094712697829730030897104473993973439473 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"30.xbar_error_and_unmapped_addr.108498009914408235861443830231931424570452628439079161852102865828786511600498","seed":108498009914408235861443830231931424570452628439079161852102865828786511600498,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3752647538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3752647538' seed=108498009914408235861443830231931424570452628439079161852102865828786511600498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108498009914408235861443830231931424570452628439079161852102865828786511600498 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"30.xbar_stress_all.40692336684394920110091625518270775591120152849006557647643392616718718613972","seed":40692336684394920110091625518270775591120152849006557647643392616718718613972,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1738947028 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1738947028' seed=40692336684394920110091625518270775591120152849006557647643392616718718613972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40692336684394920110091625518270775591120152849006557647643392616718718613972 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"30.xbar_stress_all_with_rand_reset.94580713925466988407965160733730935178869484509983113001003484943727777281475","seed":94580713925466988407965160733730935178869484509983113001003484943727777281475,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141110211 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1141110211' seed=94580713925466988407965160733730935178869484509983113001003484943727777281475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94580713925466988407965160733730935178869484509983113001003484943727777281475 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"30.xbar_stress_all_with_error.26981900854410289948230683570964847052961946328606795821117527840016294621963","seed":26981900854410289948230683570964847052961946328606795821117527840016294621963,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1615737611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1615737611' seed=26981900854410289948230683570964847052961946328606795821117527840016294621963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26981900854410289948230683570964847052961946328606795821117527840016294621963 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"30.xbar_stress_all_with_reset_error.55046860307774090897784969840273764218234771047747116539453843104796779384891","seed":55046860307774090897784969840273764218234771047747116539453843104796779384891,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457871419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.457871419' seed=55046860307774090897784969840273764218234771047747116539453843104796779384891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55046860307774090897784969840273764218234771047747116539453843104796779384891 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"31.chip_sw_all_escalation_resets.51066469604948100703134093555201581180441639549885785506774827242437285909023","seed":51066469604948100703134093555201581180441639549885785506774827242437285909023,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=992350751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.992350751' seed=51066469604948100703134093555201581180441639549885785506774827242437285909023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51066469604948100703134093555201581180441639549885785506774827242437285909023 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.10081554455618565092711586869872166959775395853920038877764531259182313890344","seed":10081554455618565092711586869872166959775395853920038877764531259182313890344,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"31.xbar_smoke.15037591304095003722401367390189191770304719289115766794101421369682463818264","seed":15037591304095003722401367390189191770304719289115766794101421369682463818264,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=521404952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.521404952' seed=15037591304095003722401367390189191770304719289115766794101421369682463818264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15037591304095003722401367390189191770304719289115766794101421369682463818264 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"31.xbar_smoke_zero_delays.73931092586246427588482395657434738872429189043315344301719904976920500665729","seed":73931092586246427588482395657434738872429189043315344301719904976920500665729,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1482325377 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1482325377' seed=73931092586246427588482395657434738872429189043315344301719904976920500665729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73931092586246427588482395657434738872429189043315344301719904976920500665729 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"31.xbar_smoke_large_delays.60454702077586698934375643144535554516466600884584599883541154371797049633722","seed":60454702077586698934375643144535554516466600884584599883541154371797049633722,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1974430650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1974430650' seed=60454702077586698934375643144535554516466600884584599883541154371797049633722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60454702077586698934375643144535554516466600884584599883541154371797049633722 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"31.xbar_smoke_slow_rsp.93232064704447009494389474219473656425935392724685589779310008233795427187102","seed":93232064704447009494389474219473656425935392724685589779310008233795427187102,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1016019358 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1016019358' seed=93232064704447009494389474219473656425935392724685589779310008233795427187102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93232064704447009494389474219473656425935392724685589779310008233795427187102 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"31.xbar_random.91809861923098479303457332200179056886886193871712343714077554321403343072141","seed":91809861923098479303457332200179056886886193871712343714077554321403343072141,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=469560205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.469560205' seed=91809861923098479303457332200179056886886193871712343714077554321403343072141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91809861923098479303457332200179056886886193871712343714077554321403343072141 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"31.xbar_random_zero_delays.64300746147950098893370761487169592526247850412199821933813751721734816249968","seed":64300746147950098893370761487169592526247850412199821933813751721734816249968,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6142064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.6142064' seed=64300746147950098893370761487169592526247850412199821933813751721734816249968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64300746147950098893370761487169592526247850412199821933813751721734816249968 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"31.xbar_random_large_delays.19588989262388518114974084257694273485794751173646036512246801449895021384640","seed":19588989262388518114974084257694273485794751173646036512246801449895021384640,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478366144 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1478366144' seed=19588989262388518114974084257694273485794751173646036512246801449895021384640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19588989262388518114974084257694273485794751173646036512246801449895021384640 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"31.xbar_random_slow_rsp.39828728336409867039398535843213950517839056510682713735837338650982956509837","seed":39828728336409867039398535843213950517839056510682713735837338650982956509837,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3326716557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3326716557' seed=39828728336409867039398535843213950517839056510682713735837338650982956509837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39828728336409867039398535843213950517839056510682713735837338650982956509837 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"31.xbar_access_same_device.70607407899436665424891453984947801646458720302174035013508766732185970664064","seed":70607407899436665424891453984947801646458720302174035013508766732185970664064,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171172480 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.171172480' seed=70607407899436665424891453984947801646458720302174035013508766732185970664064 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70607407899436665424891453984947801646458720302174035013508766732185970664064 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"31.xbar_access_same_device_slow_rsp.107184044037793429643585220394424784930009542785249602795897410513187235945873","seed":107184044037793429643585220394424784930009542785249602795897410513187235945873,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4279491985 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.4279491985' seed=107184044037793429643585220394424784930009542785249602795897410513187235945873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107184044037793429643585220394424784930009542785249602795897410513187235945873 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"31.xbar_same_source.88117389829017192579946093169111276822136422510856916620388285480324337627875","seed":88117389829017192579946093169111276822136422510856916620388285480324337627875,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3717329635 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3717329635' seed=88117389829017192579946093169111276822136422510856916620388285480324337627875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88117389829017192579946093169111276822136422510856916620388285480324337627875 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"31.xbar_error_random.17032476142119616725749404974110846145229294275121842689648201783266066717138","seed":17032476142119616725749404974110846145229294275121842689648201783266066717138,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2336643538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2336643538' seed=17032476142119616725749404974110846145229294275121842689648201783266066717138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17032476142119616725749404974110846145229294275121842689648201783266066717138 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"31.xbar_unmapped_addr.103308373698644753919980455573054668183834845716929702920630621917808277937920","seed":103308373698644753919980455573054668183834845716929702920630621917808277937920,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4278017792 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4278017792' seed=103308373698644753919980455573054668183834845716929702920630621917808277937920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103308373698644753919980455573054668183834845716929702920630621917808277937920 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"31.xbar_error_and_unmapped_addr.84497894329897312997439750905589972556552419953518765290259026510069918285847","seed":84497894329897312997439750905589972556552419953518765290259026510069918285847,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4242489367 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.4242489367' seed=84497894329897312997439750905589972556552419953518765290259026510069918285847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84497894329897312997439750905589972556552419953518765290259026510069918285847 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"31.xbar_stress_all.16221918181448230196239459718934555569148985973067714985109954915431114033146","seed":16221918181448230196239459718934555569148985973067714985109954915431114033146,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1397442554 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1397442554' seed=16221918181448230196239459718934555569148985973067714985109954915431114033146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16221918181448230196239459718934555569148985973067714985109954915431114033146 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"31.xbar_stress_all_with_rand_reset.47730700615649190154804592710710814905227717890786777428776199439532985618961","seed":47730700615649190154804592710710814905227717890786777428776199439532985618961,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3915846161 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3915846161' seed=47730700615649190154804592710710814905227717890786777428776199439532985618961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47730700615649190154804592710710814905227717890786777428776199439532985618961 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"31.xbar_stress_all_with_error.108905409363878875206007173528521785008596453701398739005030278939297233412417","seed":108905409363878875206007173528521785008596453701398739005030278939297233412417,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3344343361 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3344343361' seed=108905409363878875206007173528521785008596453701398739005030278939297233412417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=108905409363878875206007173528521785008596453701398739005030278939297233412417 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"31.xbar_stress_all_with_reset_error.15613209503016726280728147132198907491491109106664687364985156054923866563183","seed":15613209503016726280728147132198907491491109106664687364985156054923866563183,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221091951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.1221091951' seed=15613209503016726280728147132198907491491109106664687364985156054923866563183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15613209503016726280728147132198907491491109106664687364985156054923866563183 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"32.chip_sw_all_escalation_resets.95679553636232433977613221639222953063305373243089590464126262267493353384842","seed":95679553636232433977613221639222953063305373243089590464126262267493353384842,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2762861450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2762861450' seed=95679553636232433977613221639222953063305373243089590464126262267493353384842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95679553636232433977613221639222953063305373243089590464126262267493353384842 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.10278085855618931434965924060852116653623005258837227635676881889950035914413","seed":10278085855618931434965924060852116653623005258837227635676881889950035914413,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"32.xbar_smoke.19806905486877345993712575000538923167709857711681004663102867054577036227368","seed":19806905486877345993712575000538923167709857711681004663102867054577036227368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4015452968 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4015452968' seed=19806905486877345993712575000538923167709857711681004663102867054577036227368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19806905486877345993712575000538923167709857711681004663102867054577036227368 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"32.xbar_smoke_zero_delays.95827748980726552302101508915444052507478997645620930543710518511100823698023","seed":95827748980726552302101508915444052507478997645620930543710518511100823698023,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3479796327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3479796327' seed=95827748980726552302101508915444052507478997645620930543710518511100823698023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95827748980726552302101508915444052507478997645620930543710518511100823698023 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"32.xbar_smoke_large_delays.36323504714419162539500448830043397014989980910119753508838767727731219097687","seed":36323504714419162539500448830043397014989980910119753508838767727731219097687,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1868556375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1868556375' seed=36323504714419162539500448830043397014989980910119753508838767727731219097687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36323504714419162539500448830043397014989980910119753508838767727731219097687 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"32.xbar_smoke_slow_rsp.2947360381629515301601749199174464724723393374776134564985192624034750901926","seed":2947360381629515301601749199174464724723393374776134564985192624034750901926,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2362158758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2362158758' seed=2947360381629515301601749199174464724723393374776134564985192624034750901926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2947360381629515301601749199174464724723393374776134564985192624034750901926 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"32.xbar_random.45426610213394877238899246060123250350085858293943655937378884811839796509230","seed":45426610213394877238899246060123250350085858293943655937378884811839796509230,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4100553262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4100553262' seed=45426610213394877238899246060123250350085858293943655937378884811839796509230 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45426610213394877238899246060123250350085858293943655937378884811839796509230 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"32.xbar_random_zero_delays.16668897088842570466299095733297164267047464469817763174225927331064794642267","seed":16668897088842570466299095733297164267047464469817763174225927331064794642267,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2766731099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2766731099' seed=16668897088842570466299095733297164267047464469817763174225927331064794642267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16668897088842570466299095733297164267047464469817763174225927331064794642267 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"32.xbar_random_large_delays.22457439581240434483849421554020621012532352014174565061584409987427397772867","seed":22457439581240434483849421554020621012532352014174565061584409987427397772867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162244163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.162244163' seed=22457439581240434483849421554020621012532352014174565061584409987427397772867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22457439581240434483849421554020621012532352014174565061584409987427397772867 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"32.xbar_random_slow_rsp.94278276123765370131576934456438059179594705871117859019710709759903176202551","seed":94278276123765370131576934456438059179594705871117859019710709759903176202551,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772389687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3772389687' seed=94278276123765370131576934456438059179594705871117859019710709759903176202551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94278276123765370131576934456438059179594705871117859019710709759903176202551 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"32.xbar_access_same_device.82867475839345861052099595045299028215334852519686818922791585668548802758055","seed":82867475839345861052099595045299028215334852519686818922791585668548802758055,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=331204007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.331204007' seed=82867475839345861052099595045299028215334852519686818922791585668548802758055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82867475839345861052099595045299028215334852519686818922791585668548802758055 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"32.xbar_access_same_device_slow_rsp.25012093098332403465016870514974036283742710505512689170992206946991825887602","seed":25012093098332403465016870514974036283742710505512689170992206946991825887602,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1507729778 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1507729778' seed=25012093098332403465016870514974036283742710505512689170992206946991825887602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25012093098332403465016870514974036283742710505512689170992206946991825887602 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"32.xbar_same_source.23485687541790172645932136701163979165887810777906006376215943217953137781562","seed":23485687541790172645932136701163979165887810777906006376215943217953137781562,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3364383546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3364383546' seed=23485687541790172645932136701163979165887810777906006376215943217953137781562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23485687541790172645932136701163979165887810777906006376215943217953137781562 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"32.xbar_error_random.27291113988779960497298014924450827823330110413739122686821009754101037381509","seed":27291113988779960497298014924450827823330110413739122686821009754101037381509,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051599749 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3051599749' seed=27291113988779960497298014924450827823330110413739122686821009754101037381509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27291113988779960497298014924450827823330110413739122686821009754101037381509 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"32.xbar_unmapped_addr.114176710829883673944872849656116298784466977887379360493611576375657528894933","seed":114176710829883673944872849656116298784466977887379360493611576375657528894933,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=838673877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.838673877' seed=114176710829883673944872849656116298784466977887379360493611576375657528894933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114176710829883673944872849656116298784466977887379360493611576375657528894933 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"32.xbar_error_and_unmapped_addr.30860902058123862217639929926230194614827979464996524875420840816341745653667","seed":30860902058123862217639929926230194614827979464996524875420840816341745653667,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288848291 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3288848291' seed=30860902058123862217639929926230194614827979464996524875420840816341745653667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30860902058123862217639929926230194614827979464996524875420840816341745653667 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"32.xbar_stress_all.26560919185751302936530463731166021144722590929987634182073158410351630761381","seed":26560919185751302936530463731166021144722590929987634182073158410351630761381,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2499165605 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2499165605' seed=26560919185751302936530463731166021144722590929987634182073158410351630761381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26560919185751302936530463731166021144722590929987634182073158410351630761381 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"32.xbar_stress_all_with_rand_reset.73229697163162642505375375324905506894329628187416957212563343038111183951073","seed":73229697163162642505375375324905506894329628187416957212563343038111183951073,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1408652513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.1408652513' seed=73229697163162642505375375324905506894329628187416957212563343038111183951073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73229697163162642505375375324905506894329628187416957212563343038111183951073 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"32.xbar_stress_all_with_error.113514226909779808402763737914006272385559434408344970890565158008466268497556","seed":113514226909779808402763737914006272385559434408344970890565158008466268497556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=425993876 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.425993876' seed=113514226909779808402763737914006272385559434408344970890565158008466268497556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113514226909779808402763737914006272385559434408344970890565158008466268497556 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"32.xbar_stress_all_with_reset_error.4399784251876971311375281638968383523830387430686993902851628895012399968365","seed":4399784251876971311375281638968383523830387430686993902851628895012399968365,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290025581 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.290025581' seed=4399784251876971311375281638968383523830387430686993902851628895012399968365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4399784251876971311375281638968383523830387430686993902851628895012399968365 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"33.chip_sw_all_escalation_resets.80609382073401901648676947984673593599225816537787674241778696015998782192303","seed":80609382073401901648676947984673593599225816537787674241778696015998782192303,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716777135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2716777135' seed=80609382073401901648676947984673593599225816537787674241778696015998782192303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=80609382073401901648676947984673593599225816537787674241778696015998782192303 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.14956363586071685050471524193773803793332836559709667256533693531613717435024","seed":14956363586071685050471524193773803793332836559709667256533693531613717435024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"33.xbar_smoke.59301663952453997990108801934531160162133616130309731455070970423714899759897","seed":59301663952453997990108801934531160162133616130309731455070970423714899759897,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3740209945 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3740209945' seed=59301663952453997990108801934531160162133616130309731455070970423714899759897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59301663952453997990108801934531160162133616130309731455070970423714899759897 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"33.xbar_smoke_zero_delays.63809637583553693752019602094650573191141037698360294123522645685832221294661","seed":63809637583553693752019602094650573191141037698360294123522645685832221294661,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3637870661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3637870661' seed=63809637583553693752019602094650573191141037698360294123522645685832221294661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63809637583553693752019602094650573191141037698360294123522645685832221294661 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"33.xbar_smoke_large_delays.40630912597603818116051519584691157557309146453915122691086190259813680953069","seed":40630912597603818116051519584691157557309146453915122691086190259813680953069,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=955528941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.955528941' seed=40630912597603818116051519584691157557309146453915122691086190259813680953069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40630912597603818116051519584691157557309146453915122691086190259813680953069 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"33.xbar_smoke_slow_rsp.103129371864261092331523912124674642315054106518531495512545778708592380813131","seed":103129371864261092331523912124674642315054106518531495512545778708592380813131,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1800085323 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1800085323' seed=103129371864261092331523912124674642315054106518531495512545778708592380813131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103129371864261092331523912124674642315054106518531495512545778708592380813131 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"33.xbar_random.31969083605510820896995660755824866071280902880035129363360106993291652354759","seed":31969083605510820896995660755824866071280902880035129363360106993291652354759,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771323079 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3771323079' seed=31969083605510820896995660755824866071280902880035129363360106993291652354759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31969083605510820896995660755824866071280902880035129363360106993291652354759 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"33.xbar_random_zero_delays.99751621244962917597094578609038342620093764561044736537594914492617017186686","seed":99751621244962917597094578609038342620093764561044736537594914492617017186686,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112122238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.112122238' seed=99751621244962917597094578609038342620093764561044736537594914492617017186686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99751621244962917597094578609038342620093764561044736537594914492617017186686 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"33.xbar_random_large_delays.92618537989305907641078336899309184999144276546142506695073618672276396551536","seed":92618537989305907641078336899309184999144276546142506695073618672276396551536,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3705908592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3705908592' seed=92618537989305907641078336899309184999144276546142506695073618672276396551536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92618537989305907641078336899309184999144276546142506695073618672276396551536 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"33.xbar_random_slow_rsp.76478876574923719498552351620858500358064019078975816128284972584015042932506","seed":76478876574923719498552351620858500358064019078975816128284972584015042932506,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2244701978 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2244701978' seed=76478876574923719498552351620858500358064019078975816128284972584015042932506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=76478876574923719498552351620858500358064019078975816128284972584015042932506 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"33.xbar_access_same_device.25152259818376425389314079735274964896851719508581782389076500233212568496938","seed":25152259818376425389314079735274964896851719508581782389076500233212568496938,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=751790890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.751790890' seed=25152259818376425389314079735274964896851719508581782389076500233212568496938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25152259818376425389314079735274964896851719508581782389076500233212568496938 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"33.xbar_access_same_device_slow_rsp.10010268567699001287567182417654830227479762203513214616287932836122234254799","seed":10010268567699001287567182417654830227479762203513214616287932836122234254799,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1535702479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1535702479' seed=10010268567699001287567182417654830227479762203513214616287932836122234254799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10010268567699001287567182417654830227479762203513214616287932836122234254799 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"33.xbar_same_source.73030484521893647168488465286400338028628205013146744717985226568714227097509","seed":73030484521893647168488465286400338028628205013146744717985226568714227097509,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2661097381 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2661097381' seed=73030484521893647168488465286400338028628205013146744717985226568714227097509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73030484521893647168488465286400338028628205013146744717985226568714227097509 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"33.xbar_error_random.83178364932029320031110120341011194141902347506980845853953949387720267428654","seed":83178364932029320031110120341011194141902347506980845853953949387720267428654,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4161565486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4161565486' seed=83178364932029320031110120341011194141902347506980845853953949387720267428654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83178364932029320031110120341011194141902347506980845853953949387720267428654 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"33.xbar_unmapped_addr.39030543130430394376518975273576729728919728214880693357467172096767292977596","seed":39030543130430394376518975273576729728919728214880693357467172096767292977596,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3205083580 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3205083580' seed=39030543130430394376518975273576729728919728214880693357467172096767292977596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39030543130430394376518975273576729728919728214880693357467172096767292977596 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"33.xbar_error_and_unmapped_addr.100830997959769006375485878071029177645704960943724991741822766977700516058263","seed":100830997959769006375485878071029177645704960943724991741822766977700516058263,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2904544407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2904544407' seed=100830997959769006375485878071029177645704960943724991741822766977700516058263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100830997959769006375485878071029177645704960943724991741822766977700516058263 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"33.xbar_stress_all.107395103272548619488135862717844555303810614372283351485220633698746994204036","seed":107395103272548619488135862717844555303810614372283351485220633698746994204036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4215479684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4215479684' seed=107395103272548619488135862717844555303810614372283351485220633698746994204036 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107395103272548619488135862717844555303810614372283351485220633698746994204036 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"33.xbar_stress_all_with_rand_reset.79138106181085063085931416166233703262399741671510042999026676677680041355331","seed":79138106181085063085931416166233703262399741671510042999026676677680041355331,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3872712771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3872712771' seed=79138106181085063085931416166233703262399741671510042999026676677680041355331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79138106181085063085931416166233703262399741671510042999026676677680041355331 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"33.xbar_stress_all_with_error.97583674107330560705059627356931414615735762761347073446476210093516932823420","seed":97583674107330560705059627356931414615735762761347073446476210093516932823420,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2148841852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2148841852' seed=97583674107330560705059627356931414615735762761347073446476210093516932823420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97583674107330560705059627356931414615735762761347073446476210093516932823420 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"33.xbar_stress_all_with_reset_error.29183780148147294273590885534508735840092005125151102752322242657542032692962","seed":29183780148147294273590885534508735840092005125151102752322242657542032692962,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1924503266 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.1924503266' seed=29183780148147294273590885534508735840092005125151102752322242657542032692962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29183780148147294273590885534508735840092005125151102752322242657542032692962 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"34.chip_sw_all_escalation_resets.106407251218367772108262611159625803281103942129697046665551828622307249317178","seed":106407251218367772108262611159625803281103942129697046665551828622307249317178,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422957370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2422957370' seed=106407251218367772108262611159625803281103942129697046665551828622307249317178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106407251218367772108262611159625803281103942129697046665551828622307249317178 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.50741682848634443353261252687457429338940677791342047438813793299949613216775","seed":50741682848634443353261252687457429338940677791342047438813793299949613216775,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"34.xbar_smoke.39951698122709701749472982056340368011313338230753170552441903695079803864711","seed":39951698122709701749472982056340368011313338230753170552441903695079803864711,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1329481351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1329481351' seed=39951698122709701749472982056340368011313338230753170552441903695079803864711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39951698122709701749472982056340368011313338230753170552441903695079803864711 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"34.xbar_smoke_zero_delays.100469199754800581198802864717756483720639951347886629675761636376689108067273","seed":100469199754800581198802864717756483720639951347886629675761636376689108067273,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4274267081 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.4274267081' seed=100469199754800581198802864717756483720639951347886629675761636376689108067273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100469199754800581198802864717756483720639951347886629675761636376689108067273 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"34.xbar_smoke_large_delays.12367457307507453517371978896458758735481870659811605606835425658118846004090","seed":12367457307507453517371978896458758735481870659811605606835425658118846004090,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169120634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4169120634' seed=12367457307507453517371978896458758735481870659811605606835425658118846004090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12367457307507453517371978896458758735481870659811605606835425658118846004090 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"34.xbar_smoke_slow_rsp.65243556958100236294124541595164124246268633991850371811035125795733888293494","seed":65243556958100236294124541595164124246268633991850371811035125795733888293494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=993516150 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.993516150' seed=65243556958100236294124541595164124246268633991850371811035125795733888293494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65243556958100236294124541595164124246268633991850371811035125795733888293494 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"34.xbar_random.681080361313405247330950088388592147007442138142524510092150741597587444478","seed":681080361313405247330950088388592147007442138142524510092150741597587444478,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2546143998 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2546143998' seed=681080361313405247330950088388592147007442138142524510092150741597587444478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=681080361313405247330950088388592147007442138142524510092150741597587444478 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"34.xbar_random_zero_delays.39133184464796081310314125528737347300659615994349488068066484748478309372098","seed":39133184464796081310314125528737347300659615994349488068066484748478309372098,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=827494594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.827494594' seed=39133184464796081310314125528737347300659615994349488068066484748478309372098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=39133184464796081310314125528737347300659615994349488068066484748478309372098 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"34.xbar_random_large_delays.66300029121715019491158420312148788463338274382005625995666964211164245414431","seed":66300029121715019491158420312148788463338274382005625995666964211164245414431,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3629666847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3629666847' seed=66300029121715019491158420312148788463338274382005625995666964211164245414431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66300029121715019491158420312148788463338274382005625995666964211164245414431 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"34.xbar_random_slow_rsp.5948207077568207282985148819156101019481078034320001464144290128436228068295","seed":5948207077568207282985148819156101019481078034320001464144290128436228068295,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1474106311 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1474106311' seed=5948207077568207282985148819156101019481078034320001464144290128436228068295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5948207077568207282985148819156101019481078034320001464144290128436228068295 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"34.xbar_access_same_device.112622458307235670671180290416645149001667549629001848827691991496946813119773","seed":112622458307235670671180290416645149001667549629001848827691991496946813119773,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3363450141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3363450141' seed=112622458307235670671180290416645149001667549629001848827691991496946813119773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112622458307235670671180290416645149001667549629001848827691991496946813119773 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"34.xbar_access_same_device_slow_rsp.95763885949640516891305215955902992329608220488092202802540881487509551889952","seed":95763885949640516891305215955902992329608220488092202802540881487509551889952,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=720944672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.720944672' seed=95763885949640516891305215955902992329608220488092202802540881487509551889952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95763885949640516891305215955902992329608220488092202802540881487509551889952 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"34.xbar_same_source.48050849226654432408794307473560241903248895424100473575197429631262795096270","seed":48050849226654432408794307473560241903248895424100473575197429631262795096270,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1705107662 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1705107662' seed=48050849226654432408794307473560241903248895424100473575197429631262795096270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48050849226654432408794307473560241903248895424100473575197429631262795096270 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"34.xbar_error_random.1704664132705147437586731693603632390870333257560415402265536330598270432942","seed":1704664132705147437586731693603632390870333257560415402265536330598270432942,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81327790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.81327790' seed=1704664132705147437586731693603632390870333257560415402265536330598270432942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1704664132705147437586731693603632390870333257560415402265536330598270432942 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"34.xbar_unmapped_addr.38986450613166268026946660957387090406117076476759032739757885989524391227752","seed":38986450613166268026946660957387090406117076476759032739757885989524391227752,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3600970088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3600970088' seed=38986450613166268026946660957387090406117076476759032739757885989524391227752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38986450613166268026946660957387090406117076476759032739757885989524391227752 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"34.xbar_error_and_unmapped_addr.2523544451765427422822818451467218583570261981534332846936267006034919943292","seed":2523544451765427422822818451467218583570261981534332846936267006034919943292,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2930371708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2930371708' seed=2523544451765427422822818451467218583570261981534332846936267006034919943292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2523544451765427422822818451467218583570261981534332846936267006034919943292 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"34.xbar_stress_all.74304740270731885902415505795967649469742799462295958313670644194971670607297","seed":74304740270731885902415505795967649469742799462295958313670644194971670607297,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212296129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2212296129' seed=74304740270731885902415505795967649469742799462295958313670644194971670607297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74304740270731885902415505795967649469742799462295958313670644194971670607297 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"34.xbar_stress_all_with_rand_reset.3846607044489971330542597869161831227892631613170115522037730317838727433180","seed":3846607044489971330542597869161831227892631613170115522037730317838727433180,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1026477020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1026477020' seed=3846607044489971330542597869161831227892631613170115522037730317838727433180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3846607044489971330542597869161831227892631613170115522037730317838727433180 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"34.xbar_stress_all_with_error.53833496830078392607254500452545434517169089215181049439992510551957470927089","seed":53833496830078392607254500452545434517169089215181049439992510551957470927089,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3780073713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3780073713' seed=53833496830078392607254500452545434517169089215181049439992510551957470927089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53833496830078392607254500452545434517169089215181049439992510551957470927089 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"34.xbar_stress_all_with_reset_error.79387817958725943042611230538227413353939059062151493028454627469166497954807","seed":79387817958725943042611230538227413353939059062151493028454627469166497954807,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2188835831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2188835831' seed=79387817958725943042611230538227413353939059062151493028454627469166497954807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79387817958725943042611230538227413353939059062151493028454627469166497954807 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"35.chip_sw_all_escalation_resets.42890119984365727027065439050582137978000986696371650017543275883949061948264","seed":42890119984365727027065439050582137978000986696371650017543275883949061948264,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1187890024 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1187890024' seed=42890119984365727027065439050582137978000986696371650017543275883949061948264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42890119984365727027065439050582137978000986696371650017543275883949061948264 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.29101100189160695528381811699599736164990026738976447278643721952728466294897","seed":29101100189160695528381811699599736164990026738976447278643721952728466294897,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"35.xbar_smoke.111007259041434900486582208928480797922905159771776682494313892694960866785672","seed":111007259041434900486582208928480797922905159771776682494313892694960866785672,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2135095688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2135095688' seed=111007259041434900486582208928480797922905159771776682494313892694960866785672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=111007259041434900486582208928480797922905159771776682494313892694960866785672 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"35.xbar_smoke_zero_delays.31132376061857899281223425304456504912897478997541553982056754009403536702647","seed":31132376061857899281223425304456504912897478997541553982056754009403536702647,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2814114999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2814114999' seed=31132376061857899281223425304456504912897478997541553982056754009403536702647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31132376061857899281223425304456504912897478997541553982056754009403536702647 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"35.xbar_smoke_large_delays.58031536012594148295472305284694056014920631121924041833525656731268809923440","seed":58031536012594148295472305284694056014920631121924041833525656731268809923440,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=503487344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.503487344' seed=58031536012594148295472305284694056014920631121924041833525656731268809923440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58031536012594148295472305284694056014920631121924041833525656731268809923440 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"35.xbar_smoke_slow_rsp.86112047382708547879956725312671655879244029750717043129581743964495491717066","seed":86112047382708547879956725312671655879244029750717043129581743964495491717066,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3202176970 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3202176970' seed=86112047382708547879956725312671655879244029750717043129581743964495491717066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86112047382708547879956725312671655879244029750717043129581743964495491717066 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"35.xbar_random.14229464083580661340287301900416439179200222673800202747376008237920145605092","seed":14229464083580661340287301900416439179200222673800202747376008237920145605092,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28803556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.28803556' seed=14229464083580661340287301900416439179200222673800202747376008237920145605092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14229464083580661340287301900416439179200222673800202747376008237920145605092 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"35.xbar_random_zero_delays.96663850202938998466621430814116778648426926362522800495574087881976745353997","seed":96663850202938998466621430814116778648426926362522800495574087881976745353997,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2947080973 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2947080973' seed=96663850202938998466621430814116778648426926362522800495574087881976745353997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96663850202938998466621430814116778648426926362522800495574087881976745353997 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"35.xbar_random_large_delays.90281727242558219406925630655657562023260357653267308362029569850277153345556","seed":90281727242558219406925630655657562023260357653267308362029569850277153345556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2171998228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2171998228' seed=90281727242558219406925630655657562023260357653267308362029569850277153345556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90281727242558219406925630655657562023260357653267308362029569850277153345556 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"35.xbar_random_slow_rsp.87819285202219837214339771020034051005769854307373033936055070628955854019927","seed":87819285202219837214339771020034051005769854307373033936055070628955854019927,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3104120151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3104120151' seed=87819285202219837214339771020034051005769854307373033936055070628955854019927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87819285202219837214339771020034051005769854307373033936055070628955854019927 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"35.xbar_access_same_device.87925417865997109714067106331920368629568395973777964269491551365054374577077","seed":87925417865997109714067106331920368629568395973777964269491551365054374577077,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=645628853 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.645628853' seed=87925417865997109714067106331920368629568395973777964269491551365054374577077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87925417865997109714067106331920368629568395973777964269491551365054374577077 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"35.xbar_access_same_device_slow_rsp.56028175920682520526178573528793651236834254656252555415764197343945847214477","seed":56028175920682520526178573528793651236834254656252555415764197343945847214477,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3449557389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3449557389' seed=56028175920682520526178573528793651236834254656252555415764197343945847214477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56028175920682520526178573528793651236834254656252555415764197343945847214477 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"35.xbar_same_source.38322686024555836133329284989551423797227796565318846409005048828741557458952","seed":38322686024555836133329284989551423797227796565318846409005048828741557458952,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3287324680 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3287324680' seed=38322686024555836133329284989551423797227796565318846409005048828741557458952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=38322686024555836133329284989551423797227796565318846409005048828741557458952 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"35.xbar_error_random.40007056543567299939851176598145039581905827368843419462527533500371088452999","seed":40007056543567299939851176598145039581905827368843419462527533500371088452999,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2699046279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2699046279' seed=40007056543567299939851176598145039581905827368843419462527533500371088452999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40007056543567299939851176598145039581905827368843419462527533500371088452999 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"35.xbar_unmapped_addr.60239119181654398140487149708773761013181071888807806472965171344521150534346","seed":60239119181654398140487149708773761013181071888807806472965171344521150534346,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596030666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3596030666' seed=60239119181654398140487149708773761013181071888807806472965171344521150534346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60239119181654398140487149708773761013181071888807806472965171344521150534346 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"35.xbar_error_and_unmapped_addr.82313959673350746118545828984207536193440435440327888936154473525325161619067","seed":82313959673350746118545828984207536193440435440327888936154473525325161619067,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113279099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3113279099' seed=82313959673350746118545828984207536193440435440327888936154473525325161619067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82313959673350746118545828984207536193440435440327888936154473525325161619067 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"35.xbar_stress_all.47897533990817168638954449393668217290890410517955514227510531125239565120459","seed":47897533990817168638954449393668217290890410517955514227510531125239565120459,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1050538955 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1050538955' seed=47897533990817168638954449393668217290890410517955514227510531125239565120459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=47897533990817168638954449393668217290890410517955514227510531125239565120459 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"35.xbar_stress_all_with_rand_reset.16048499707495621363711633184030680674025004732845830004632591148389293577987","seed":16048499707495621363711633184030680674025004732845830004632591148389293577987,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026067715 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2026067715' seed=16048499707495621363711633184030680674025004732845830004632591148389293577987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16048499707495621363711633184030680674025004732845830004632591148389293577987 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"35.xbar_stress_all_with_error.86497948276165103115115858660504548665839350755660676843317232239002767887866","seed":86497948276165103115115858660504548665839350755660676843317232239002767887866,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802959354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3802959354' seed=86497948276165103115115858660504548665839350755660676843317232239002767887866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86497948276165103115115858660504548665839350755660676843317232239002767887866 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"35.xbar_stress_all_with_reset_error.102368046028897900432044957467908247344770131364023495435182040113295911659792","seed":102368046028897900432044957467908247344770131364023495435182040113295911659792,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4086147344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.4086147344' seed=102368046028897900432044957467908247344770131364023495435182040113295911659792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102368046028897900432044957467908247344770131364023495435182040113295911659792 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"36.chip_sw_all_escalation_resets.24918373991450429653244036284217770542149814459064028062178157265971849367040","seed":24918373991450429653244036284217770542149814459064028062178157265971849367040,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=496930304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.496930304' seed=24918373991450429653244036284217770542149814459064028062178157265971849367040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=24918373991450429653244036284217770542149814459064028062178157265971849367040 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.101368224856192913140760898366212377096327578672233202624600092843750239596000","seed":101368224856192913140760898366212377096327578672233202624600092843750239596000,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"36.xbar_smoke.14139453928196617554608635750130111933244944989941231160193077490805203762200","seed":14139453928196617554608635750130111933244944989941231160193077490805203762200,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3001777176 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3001777176' seed=14139453928196617554608635750130111933244944989941231160193077490805203762200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14139453928196617554608635750130111933244944989941231160193077490805203762200 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"36.xbar_smoke_zero_delays.93395823376559259306652623182961379924058668696435501129449237983747452679712","seed":93395823376559259306652623182961379924058668696435501129449237983747452679712,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=725595680 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.725595680' seed=93395823376559259306652623182961379924058668696435501129449237983747452679712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93395823376559259306652623182961379924058668696435501129449237983747452679712 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"36.xbar_smoke_large_delays.98795956883238285548866231922360927331801071677151528403997406439065176002881","seed":98795956883238285548866231922360927331801071677151528403997406439065176002881,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2902217025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2902217025' seed=98795956883238285548866231922360927331801071677151528403997406439065176002881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98795956883238285548866231922360927331801071677151528403997406439065176002881 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"36.xbar_smoke_slow_rsp.69422495311349051679001747175425942855800073038791741797338216539442236108983","seed":69422495311349051679001747175425942855800073038791741797338216539442236108983,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=763375799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.763375799' seed=69422495311349051679001747175425942855800073038791741797338216539442236108983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69422495311349051679001747175425942855800073038791741797338216539442236108983 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"36.xbar_random.92080749231810587786816117388935070170733266790284938383863230791492817256556","seed":92080749231810587786816117388935070170733266790284938383863230791492817256556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4161405036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4161405036' seed=92080749231810587786816117388935070170733266790284938383863230791492817256556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92080749231810587786816117388935070170733266790284938383863230791492817256556 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"36.xbar_random_zero_delays.25786459995356961841329457016914775630712584762658231416397783368843389490253","seed":25786459995356961841329457016914775630712584762658231416397783368843389490253,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003489869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2003489869' seed=25786459995356961841329457016914775630712584762658231416397783368843389490253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25786459995356961841329457016914775630712584762658231416397783368843389490253 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"36.xbar_random_large_delays.11549400590887651848302919460844306803952467699191372577048533912060679311637","seed":11549400590887651848302919460844306803952467699191372577048533912060679311637,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3010875669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3010875669' seed=11549400590887651848302919460844306803952467699191372577048533912060679311637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11549400590887651848302919460844306803952467699191372577048533912060679311637 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"36.xbar_random_slow_rsp.4424489739468834993729863839613945136705504057830569236991392372135222420353","seed":4424489739468834993729863839613945136705504057830569236991392372135222420353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1280156545 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1280156545' seed=4424489739468834993729863839613945136705504057830569236991392372135222420353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4424489739468834993729863839613945136705504057830569236991392372135222420353 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"36.xbar_access_same_device.33605042429886855686155035327121000051324704397102741689365534300145560050439","seed":33605042429886855686155035327121000051324704397102741689365534300145560050439,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1455414023 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1455414023' seed=33605042429886855686155035327121000051324704397102741689365534300145560050439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33605042429886855686155035327121000051324704397102741689365534300145560050439 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"36.xbar_access_same_device_slow_rsp.91102290738148290945477766537247868491267087108276609844296922565659320763171","seed":91102290738148290945477766537247868491267087108276609844296922565659320763171,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924411171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3924411171' seed=91102290738148290945477766537247868491267087108276609844296922565659320763171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91102290738148290945477766537247868491267087108276609844296922565659320763171 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"36.xbar_same_source.19073843889230022951475463316838632998735397741672867708106358288869659857089","seed":19073843889230022951475463316838632998735397741672867708106358288869659857089,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2817872065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2817872065' seed=19073843889230022951475463316838632998735397741672867708106358288869659857089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19073843889230022951475463316838632998735397741672867708106358288869659857089 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"36.xbar_error_random.40875131996014770740931128334013129066740077603708250968372140897917289813142","seed":40875131996014770740931128334013129066740077603708250968372140897917289813142,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1777783958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1777783958' seed=40875131996014770740931128334013129066740077603708250968372140897917289813142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40875131996014770740931128334013129066740077603708250968372140897917289813142 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"36.xbar_unmapped_addr.97263327813617151072763524306702117691350483950571575770155381131612332066256","seed":97263327813617151072763524306702117691350483950571575770155381131612332066256,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730170832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.730170832' seed=97263327813617151072763524306702117691350483950571575770155381131612332066256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97263327813617151072763524306702117691350483950571575770155381131612332066256 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"36.xbar_error_and_unmapped_addr.90327383123520555315170449434851000044585936807871917997966947005114626635317","seed":90327383123520555315170449434851000044585936807871917997966947005114626635317,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3611588149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3611588149' seed=90327383123520555315170449434851000044585936807871917997966947005114626635317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90327383123520555315170449434851000044585936807871917997966947005114626635317 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"36.xbar_stress_all.96986547767845303813381926320301615387526857794034596164724606041899900298150","seed":96986547767845303813381926320301615387526857794034596164724606041899900298150,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3420414886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3420414886' seed=96986547767845303813381926320301615387526857794034596164724606041899900298150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96986547767845303813381926320301615387526857794034596164724606041899900298150 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"36.xbar_stress_all_with_rand_reset.103686298470957095680520762811784448641703493968545718434805871763699217563601","seed":103686298470957095680520762811784448641703493968545718434805871763699217563601,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1923448785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1923448785' seed=103686298470957095680520762811784448641703493968545718434805871763699217563601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103686298470957095680520762811784448641703493968545718434805871763699217563601 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"36.xbar_stress_all_with_error.113398120779273422329078082315304749415991543034601309055818543932316754009853","seed":113398120779273422329078082315304749415991543034601309055818543932316754009853,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2564972285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2564972285' seed=113398120779273422329078082315304749415991543034601309055818543932316754009853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113398120779273422329078082315304749415991543034601309055818543932316754009853 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"36.xbar_stress_all_with_reset_error.74971762300743564799547360222213305717388955499715848075426569017817914822690","seed":74971762300743564799547360222213305717388955499715848075426569017817914822690,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2566279202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.2566279202' seed=74971762300743564799547360222213305717388955499715848075426569017817914822690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74971762300743564799547360222213305717388955499715848075426569017817914822690 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"37.chip_sw_all_escalation_resets.2004259192026307519150416729175500347330544643816979140896038280027750185473","seed":2004259192026307519150416729175500347330544643816979140896038280027750185473,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=277527041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.277527041' seed=2004259192026307519150416729175500347330544643816979140896038280027750185473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2004259192026307519150416729175500347330544643816979140896038280027750185473 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.48836854026439362246820115419881301838001132887503292815341644229092110157678","seed":48836854026439362246820115419881301838001132887503292815341644229092110157678,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=361614) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"37.xbar_smoke.112617705841187743062666431984240964825679675408179842968930827367996436131402","seed":112617705841187743062666431984240964825679675408179842968930827367996436131402,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3462540874 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3462540874' seed=112617705841187743062666431984240964825679675408179842968930827367996436131402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112617705841187743062666431984240964825679675408179842968930827367996436131402 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"37.xbar_smoke_zero_delays.65960593647627657390493980860075202561901069949953342390801955624575132610535","seed":65960593647627657390493980860075202561901069949953342390801955624575132610535,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507335143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3507335143' seed=65960593647627657390493980860075202561901069949953342390801955624575132610535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65960593647627657390493980860075202561901069949953342390801955624575132610535 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"37.xbar_smoke_large_delays.101082981933767539184158460767979660330652831951476457973912198892988452847021","seed":101082981933767539184158460767979660330652831951476457973912198892988452847021,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2288795053 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2288795053' seed=101082981933767539184158460767979660330652831951476457973912198892988452847021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101082981933767539184158460767979660330652831951476457973912198892988452847021 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"37.xbar_smoke_slow_rsp.4277953865537359032555801833720748972436428179116866948561543952193110886242","seed":4277953865537359032555801833720748972436428179116866948561543952193110886242,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4191111010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4191111010' seed=4277953865537359032555801833720748972436428179116866948561543952193110886242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4277953865537359032555801833720748972436428179116866948561543952193110886242 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"37.xbar_random.67976461210207427115591015498517157779297320881371681247842566920188683025163","seed":67976461210207427115591015498517157779297320881371681247842566920188683025163,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2327509771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2327509771' seed=67976461210207427115591015498517157779297320881371681247842566920188683025163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67976461210207427115591015498517157779297320881371681247842566920188683025163 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"37.xbar_random_zero_delays.6858117119277893094137427912619122674555359950226417884365065828318518629316","seed":6858117119277893094137427912619122674555359950226417884365065828318518629316,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230323652 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3230323652' seed=6858117119277893094137427912619122674555359950226417884365065828318518629316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6858117119277893094137427912619122674555359950226417884365065828318518629316 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"37.xbar_random_large_delays.35380297043014591628344344864131494941629572553806986612687514875187301078366","seed":35380297043014591628344344864131494941629572553806986612687514875187301078366,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023380318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2023380318' seed=35380297043014591628344344864131494941629572553806986612687514875187301078366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35380297043014591628344344864131494941629572553806986612687514875187301078366 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"37.xbar_random_slow_rsp.29993436204842428718297945716120625228721051712276396002548517686353623215884","seed":29993436204842428718297945716120625228721051712276396002548517686353623215884,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=672624396 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.672624396' seed=29993436204842428718297945716120625228721051712276396002548517686353623215884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29993436204842428718297945716120625228721051712276396002548517686353623215884 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"37.xbar_access_same_device.96095215939673226791957187952409768452000976807180775486126699485696120261116","seed":96095215939673226791957187952409768452000976807180775486126699485696120261116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=682559996 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.682559996' seed=96095215939673226791957187952409768452000976807180775486126699485696120261116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96095215939673226791957187952409768452000976807180775486126699485696120261116 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"37.xbar_access_same_device_slow_rsp.96731139284006063717435321614994569942087909672965460522759477851239579794806","seed":96731139284006063717435321614994569942087909672965460522759477851239579794806,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193847158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3193847158' seed=96731139284006063717435321614994569942087909672965460522759477851239579794806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=96731139284006063717435321614994569942087909672965460522759477851239579794806 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"37.xbar_same_source.78677308182537084672097598188743422800686395338663236801500550719963636909149","seed":78677308182537084672097598188743422800686395338663236801500550719963636909149,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778757725 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3778757725' seed=78677308182537084672097598188743422800686395338663236801500550719963636909149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78677308182537084672097598188743422800686395338663236801500550719963636909149 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"37.xbar_error_random.66119470815670065358177121099422773000455439769654912549299966743183641137178","seed":66119470815670065358177121099422773000455439769654912549299966743183641137178,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551669786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.551669786' seed=66119470815670065358177121099422773000455439769654912549299966743183641137178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66119470815670065358177121099422773000455439769654912549299966743183641137178 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"37.xbar_unmapped_addr.72745459511255053064018516804525213767425815364886450081724722297662174577654","seed":72745459511255053064018516804525213767425815364886450081724722297662174577654,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1634911222 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1634911222' seed=72745459511255053064018516804525213767425815364886450081724722297662174577654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72745459511255053064018516804525213767425815364886450081724722297662174577654 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"37.xbar_error_and_unmapped_addr.25130662816778367097063781452020053740634758337484008286407271191184445764926","seed":25130662816778367097063781452020053740634758337484008286407271191184445764926,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3319231806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3319231806' seed=25130662816778367097063781452020053740634758337484008286407271191184445764926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25130662816778367097063781452020053740634758337484008286407271191184445764926 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"37.xbar_stress_all.33495669735865905568196664773488463829961381078321083158137272180495079586755","seed":33495669735865905568196664773488463829961381078321083158137272180495079586755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1917205443 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1917205443' seed=33495669735865905568196664773488463829961381078321083158137272180495079586755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33495669735865905568196664773488463829961381078321083158137272180495079586755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"37.xbar_stress_all_with_rand_reset.56945762009471670269264729316845007192915788957376929816916572901828950717318","seed":56945762009471670269264729316845007192915788957376929816916572901828950717318,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1721201542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.1721201542' seed=56945762009471670269264729316845007192915788957376929816916572901828950717318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56945762009471670269264729316845007192915788957376929816916572901828950717318 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"37.xbar_stress_all_with_error.107445234653083144460645545022693869447370826340296272749792514607401208624383","seed":107445234653083144460645545022693869447370826340296272749792514607401208624383,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4216567039 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.4216567039' seed=107445234653083144460645545022693869447370826340296272749792514607401208624383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107445234653083144460645545022693869447370826340296272749792514607401208624383 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"37.xbar_stress_all_with_reset_error.28095364171764117772711345921403773506202935776890432511348159985408717666575","seed":28095364171764117772711345921403773506202935776890432511348159985408717666575,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3710695695 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3710695695' seed=28095364171764117772711345921403773506202935776890432511348159985408717666575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28095364171764117772711345921403773506202935776890432511348159985408717666575 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"38.chip_sw_all_escalation_resets.70748378588980580238984112662261945436365592150858674937185999595289792933306","seed":70748378588980580238984112662261945436365592150858674937185999595289792933306,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2015817146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2015817146' seed=70748378588980580238984112662261945436365592150858674937185999595289792933306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70748378588980580238984112662261945436365592150858674937185999595289792933306 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.54880401924070731848570347481097104927012375610193627550903779902643124575451","seed":54880401924070731848570347481097104927012375610193627550903779902643124575451,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"38.xbar_smoke.63644442520308302973425386275750573418584713818757908763429545449649253142960","seed":63644442520308302973425386275750573418584713818757908763429545449649253142960,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2282508720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2282508720' seed=63644442520308302973425386275750573418584713818757908763429545449649253142960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63644442520308302973425386275750573418584713818757908763429545449649253142960 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"38.xbar_smoke_zero_delays.36473664692016189942996542938950548408325855831952494560208599511409498555551","seed":36473664692016189942996542938950548408325855831952494560208599511409498555551,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268365983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2268365983' seed=36473664692016189942996542938950548408325855831952494560208599511409498555551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36473664692016189942996542938950548408325855831952494560208599511409498555551 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"38.xbar_smoke_large_delays.59794618933368449879704450529497640405872572944878188890199052690334137952394","seed":59794618933368449879704450529497640405872572944878188890199052690334137952394,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818208394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1818208394' seed=59794618933368449879704450529497640405872572944878188890199052690334137952394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59794618933368449879704450529497640405872572944878188890199052690334137952394 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"38.xbar_smoke_slow_rsp.107215346438726940862471365949006449469801213960720690889639759806241703799116","seed":107215346438726940862471365949006449469801213960720690889639759806241703799116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2904369484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2904369484' seed=107215346438726940862471365949006449469801213960720690889639759806241703799116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107215346438726940862471365949006449469801213960720690889639759806241703799116 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"38.xbar_random.9088454918218824625875561372127738730106912130693696970851576491962942815763","seed":9088454918218824625875561372127738730106912130693696970851576491962942815763,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113180179 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.113180179' seed=9088454918218824625875561372127738730106912130693696970851576491962942815763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9088454918218824625875561372127738730106912130693696970851576491962942815763 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"38.xbar_random_zero_delays.93595291271246172524754888678564707658356011114272422414830192372967396030416","seed":93595291271246172524754888678564707658356011114272422414830192372967396030416,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4110366672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.4110366672' seed=93595291271246172524754888678564707658356011114272422414830192372967396030416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93595291271246172524754888678564707658356011114272422414830192372967396030416 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"38.xbar_random_large_delays.102021915540818415396861147632166505944258051267199148550776291844649885199890","seed":102021915540818415396861147632166505944258051267199148550776291844649885199890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2363584018 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2363584018' seed=102021915540818415396861147632166505944258051267199148550776291844649885199890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102021915540818415396861147632166505944258051267199148550776291844649885199890 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"38.xbar_random_slow_rsp.5221719778368952381503555798184179701640626005383650447536921882437431154359","seed":5221719778368952381503555798184179701640626005383650447536921882437431154359,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2625722039 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2625722039' seed=5221719778368952381503555798184179701640626005383650447536921882437431154359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=5221719778368952381503555798184179701640626005383650447536921882437431154359 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"38.xbar_access_same_device.106525339201418375770032219967704916078732226647959561758325216811232830125781","seed":106525339201418375770032219967704916078732226647959561758325216811232830125781,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1021015765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1021015765' seed=106525339201418375770032219967704916078732226647959561758325216811232830125781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106525339201418375770032219967704916078732226647959561758325216811232830125781 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"38.xbar_access_same_device_slow_rsp.60896016769365476800187648681272687047128979333493965964326564942209121513407","seed":60896016769365476800187648681272687047128979333493965964326564942209121513407,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519199679 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2519199679' seed=60896016769365476800187648681272687047128979333493965964326564942209121513407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60896016769365476800187648681272687047128979333493965964326564942209121513407 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"38.xbar_same_source.17756484046312212934487768504672923045038353919935841391707440838967113957973","seed":17756484046312212934487768504672923045038353919935841391707440838967113957973,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3330687573 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3330687573' seed=17756484046312212934487768504672923045038353919935841391707440838967113957973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17756484046312212934487768504672923045038353919935841391707440838967113957973 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"38.xbar_error_random.14331225457640072380492589231954207825387651128474143171726029221531311181598","seed":14331225457640072380492589231954207825387651128474143171726029221531311181598,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675295518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3675295518' seed=14331225457640072380492589231954207825387651128474143171726029221531311181598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14331225457640072380492589231954207825387651128474143171726029221531311181598 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"38.xbar_unmapped_addr.11169773093069488054882294644341805052271641537385311399500221449387823044337","seed":11169773093069488054882294644341805052271641537385311399500221449387823044337,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=714839793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.714839793' seed=11169773093069488054882294644341805052271641537385311399500221449387823044337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11169773093069488054882294644341805052271641537385311399500221449387823044337 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"38.xbar_error_and_unmapped_addr.50728466316373681228659316534311205045560146896068751224800204567737372424605","seed":50728466316373681228659316534311205045560146896068751224800204567737372424605,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3390486941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3390486941' seed=50728466316373681228659316534311205045560146896068751224800204567737372424605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50728466316373681228659316534311205045560146896068751224800204567737372424605 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"38.xbar_stress_all.30099197437721397092760178268187608719840975443946212649812867501756924331001","seed":30099197437721397092760178268187608719840975443946212649812867501756924331001,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=676365305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.676365305' seed=30099197437721397092760178268187608719840975443946212649812867501756924331001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30099197437721397092760178268187608719840975443946212649812867501756924331001 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"38.xbar_stress_all_with_rand_reset.28550732542796432428783962789652664576081325379414720860744036276820629480062","seed":28550732542796432428783962789652664576081325379414720860744036276820629480062,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2605933182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2605933182' seed=28550732542796432428783962789652664576081325379414720860744036276820629480062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28550732542796432428783962789652664576081325379414720860744036276820629480062 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"38.xbar_stress_all_with_error.8650367384778870517771973938689977467468900597367773850253012537305516760060","seed":8650367384778870517771973938689977467468900597367773850253012537305516760060,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2211994620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2211994620' seed=8650367384778870517771973938689977467468900597367773850253012537305516760060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8650367384778870517771973938689977467468900597367773850253012537305516760060 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"38.xbar_stress_all_with_reset_error.83060668683824673451501679846853039181799685502875568578983915911583461522393","seed":83060668683824673451501679846853039181799685502875568578983915911583461522393,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2552216537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2552216537' seed=83060668683824673451501679846853039181799685502875568578983915911583461522393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83060668683824673451501679846853039181799685502875568578983915911583461522393 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"39.chip_sw_all_escalation_resets.57555054216474718108425355305884968719927975107205299962446604525490872646546","seed":57555054216474718108425355305884968719927975107205299962446604525490872646546,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3986291602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3986291602' seed=57555054216474718108425355305884968719927975107205299962446604525490872646546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=57555054216474718108425355305884968719927975107205299962446604525490872646546 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.22275375661181156627222176141819920684585666687712775567543445397240027735151","seed":22275375661181156627222176141819920684585666687712775567543445397240027735151,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=362209) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"39.xbar_smoke.81167196036682734982489576504943755216701202281798742040667607652695594043164","seed":81167196036682734982489576504943755216701202281798742040667607652695594043164,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010632476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1010632476' seed=81167196036682734982489576504943755216701202281798742040667607652695594043164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81167196036682734982489576504943755216701202281798742040667607652695594043164 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"39.xbar_smoke_zero_delays.23714045844981534702701507189713837238887583045590940151126034653159979406662","seed":23714045844981534702701507189713837238887583045590940151126034653159979406662,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1518523718 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1518523718' seed=23714045844981534702701507189713837238887583045590940151126034653159979406662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23714045844981534702701507189713837238887583045590940151126034653159979406662 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"39.xbar_smoke_large_delays.50037533752460197062420818320596502389127095577623125657386998113431926738957","seed":50037533752460197062420818320596502389127095577623125657386998113431926738957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4260499469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.4260499469' seed=50037533752460197062420818320596502389127095577623125657386998113431926738957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50037533752460197062420818320596502389127095577623125657386998113431926738957 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"39.xbar_smoke_slow_rsp.97751366132723496967046547687469911383609105682048491897205304302435768259319","seed":97751366132723496967046547687469911383609105682048491897205304302435768259319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3774141175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3774141175' seed=97751366132723496967046547687469911383609105682048491897205304302435768259319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97751366132723496967046547687469911383609105682048491897205304302435768259319 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"39.xbar_random.102500760378705490416860052218448579033359182900496578663739086003612004206386","seed":102500760378705490416860052218448579033359182900496578663739086003612004206386,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=519391026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.519391026' seed=102500760378705490416860052218448579033359182900496578663739086003612004206386 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102500760378705490416860052218448579033359182900496578663739086003612004206386 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"39.xbar_random_zero_delays.77261687057355878336785586679542693960232003395020598407949172198203694108813","seed":77261687057355878336785586679542693960232003395020598407949172198203694108813,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=104452237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.104452237' seed=77261687057355878336785586679542693960232003395020598407949172198203694108813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77261687057355878336785586679542693960232003395020598407949172198203694108813 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"39.xbar_random_large_delays.112282124162310300586908107258009901100464561500782368630153201948228873798986","seed":112282124162310300586908107258009901100464561500782368630153201948228873798986,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=630113610 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.630113610' seed=112282124162310300586908107258009901100464561500782368630153201948228873798986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112282124162310300586908107258009901100464561500782368630153201948228873798986 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"39.xbar_random_slow_rsp.71101753964354883009870267274184764618701613038922879758075454042002858983604","seed":71101753964354883009870267274184764618701613038922879758075454042002858983604,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3700441268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3700441268' seed=71101753964354883009870267274184764618701613038922879758075454042002858983604 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71101753964354883009870267274184764618701613038922879758075454042002858983604 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"39.xbar_access_same_device.6604926153887370381266316020593692857882539309533469452926981392557698282045","seed":6604926153887370381266316020593692857882539309533469452926981392557698282045,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2919854653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2919854653' seed=6604926153887370381266316020593692857882539309533469452926981392557698282045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6604926153887370381266316020593692857882539309533469452926981392557698282045 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"39.xbar_access_same_device_slow_rsp.68406728262710129456085264756030915123182099504457084387333675659531783705761","seed":68406728262710129456085264756030915123182099504457084387333675659531783705761,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4060550305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.4060550305' seed=68406728262710129456085264756030915123182099504457084387333675659531783705761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=68406728262710129456085264756030915123182099504457084387333675659531783705761 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"39.xbar_same_source.78080637898165526459940488233963794136129598724853823598015700538965065852392","seed":78080637898165526459940488233963794136129598724853823598015700538965065852392,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2611865064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2611865064' seed=78080637898165526459940488233963794136129598724853823598015700538965065852392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78080637898165526459940488233963794136129598724853823598015700538965065852392 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"39.xbar_error_random.16906519124010882459629650935839872672482992952946966711914109026918607512644","seed":16906519124010882459629650935839872672482992952946966711914109026918607512644,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1777755204 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1777755204' seed=16906519124010882459629650935839872672482992952946966711914109026918607512644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16906519124010882459629650935839872672482992952946966711914109026918607512644 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"39.xbar_unmapped_addr.78189311398205596964554978401228818786699999303014404469261214001857440932209","seed":78189311398205596964554978401228818786699999303014404469261214001857440932209,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042178417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1042178417' seed=78189311398205596964554978401228818786699999303014404469261214001857440932209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=78189311398205596964554978401228818786699999303014404469261214001857440932209 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"39.xbar_error_and_unmapped_addr.95436324214456813614582742881440752869383216729184406658610108220410457237396","seed":95436324214456813614582742881440752869383216729184406658610108220410457237396,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011361684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1011361684' seed=95436324214456813614582742881440752869383216729184406658610108220410457237396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95436324214456813614582742881440752869383216729184406658610108220410457237396 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"39.xbar_stress_all.101025758852323316894656257508966589367650266420224108488314280594729566572920","seed":101025758852323316894656257508966589367650266420224108488314280594729566572920,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=458330488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.458330488' seed=101025758852323316894656257508966589367650266420224108488314280594729566572920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101025758852323316894656257508966589367650266420224108488314280594729566572920 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"39.xbar_stress_all_with_rand_reset.65403146395399298373429941316151964486089603479386065629071878452146112247956","seed":65403146395399298373429941316151964486089603479386065629071878452146112247956,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980709012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.1980709012' seed=65403146395399298373429941316151964486089603479386065629071878452146112247956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65403146395399298373429941316151964486089603479386065629071878452146112247956 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"39.xbar_stress_all_with_error.22635474474896402331241623892468346860060877996320543430686463749478701426856","seed":22635474474896402331241623892468346860060877996320543430686463749478701426856,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2625464488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2625464488' seed=22635474474896402331241623892468346860060877996320543430686463749478701426856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22635474474896402331241623892468346860060877996320543430686463749478701426856 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"39.xbar_stress_all_with_reset_error.106360195870267027501157357329809676336549134359423440064474758499564017277991","seed":106360195870267027501157357329809676336549134359423440064474758499564017277991,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=447863847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.447863847' seed=106360195870267027501157357329809676336549134359423440064474758499564017277991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106360195870267027501157357329809676336549134359423440064474758499564017277991 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"40.chip_sw_all_escalation_resets.63167312761802663652627835191178020195575363092951094676479322670382752272495","seed":63167312761802663652627835191178020195575363092951094676479322670382752272495,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028174447 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.4028174447' seed=63167312761802663652627835191178020195575363092951094676479322670382752272495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63167312761802663652627835191178020195575363092951094676479322670382752272495 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.88119396495154753810517241498662422182070941578927891175439555915302389654413","seed":88119396495154753810517241498662422182070941578927891175439555915302389654413,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"40.xbar_smoke.14539907782503721117124196199612516298222119830777183848715401565624811490478","seed":14539907782503721117124196199612516298222119830777183848715401565624811490478,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2586938542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2586938542' seed=14539907782503721117124196199612516298222119830777183848715401565624811490478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14539907782503721117124196199612516298222119830777183848715401565624811490478 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"40.xbar_smoke_zero_delays.107333377914896811939309407453632531441104840160225790716553933612218424699498","seed":107333377914896811939309407453632531441104840160225790716553933612218424699498,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3115264618 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3115264618' seed=107333377914896811939309407453632531441104840160225790716553933612218424699498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107333377914896811939309407453632531441104840160225790716553933612218424699498 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"40.xbar_smoke_large_delays.83496561095223653627907294914972699898079488425219341456558062823664129214851","seed":83496561095223653627907294914972699898079488425219341456558062823664129214851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3185641859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3185641859' seed=83496561095223653627907294914972699898079488425219341456558062823664129214851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83496561095223653627907294914972699898079488425219341456558062823664129214851 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"40.xbar_smoke_slow_rsp.82354542169456846725405546382148658615331837301697466028111873917956447840388","seed":82354542169456846725405546382148658615331837301697466028111873917956447840388,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=885303428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.885303428' seed=82354542169456846725405546382148658615331837301697466028111873917956447840388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82354542169456846725405546382148658615331837301697466028111873917956447840388 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"40.xbar_random.32561712151549340059408058018760815214341019627166183909081925412099319769740","seed":32561712151549340059408058018760815214341019627166183909081925412099319769740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1989257868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1989257868' seed=32561712151549340059408058018760815214341019627166183909081925412099319769740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32561712151549340059408058018760815214341019627166183909081925412099319769740 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"40.xbar_random_zero_delays.94261324563006482029446358130603477274877683670675020966207734625706653914978","seed":94261324563006482029446358130603477274877683670675020966207734625706653914978,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435899746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1435899746' seed=94261324563006482029446358130603477274877683670675020966207734625706653914978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94261324563006482029446358130603477274877683670675020966207734625706653914978 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"40.xbar_random_large_delays.70677278867563723654651378406856813594789079138965943884418567518568864209852","seed":70677278867563723654651378406856813594789079138965943884418567518568864209852,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579763644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3579763644' seed=70677278867563723654651378406856813594789079138965943884418567518568864209852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70677278867563723654651378406856813594789079138965943884418567518568864209852 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"40.xbar_random_slow_rsp.56215404565492070210861776765993379780172763387661690771329643760008138999492","seed":56215404565492070210861776765993379780172763387661690771329643760008138999492,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1662928580 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1662928580' seed=56215404565492070210861776765993379780172763387661690771329643760008138999492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56215404565492070210861776765993379780172763387661690771329643760008138999492 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"40.xbar_access_same_device.32503861475725610067947599006379190914796940990149770622020617277248661660302","seed":32503861475725610067947599006379190914796940990149770622020617277248661660302,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3841499790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3841499790' seed=32503861475725610067947599006379190914796940990149770622020617277248661660302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32503861475725610067947599006379190914796940990149770622020617277248661660302 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"40.xbar_access_same_device_slow_rsp.9894260117560661729404662762474048796081962888969844337599892675149942359921","seed":9894260117560661729404662762474048796081962888969844337599892675149942359921,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1807615857 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1807615857' seed=9894260117560661729404662762474048796081962888969844337599892675149942359921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9894260117560661729404662762474048796081962888969844337599892675149942359921 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"40.xbar_same_source.740951151506817025966887030459959793044651283036539901528068026981401181132","seed":740951151506817025966887030459959793044651283036539901528068026981401181132,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4293868492 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.4293868492' seed=740951151506817025966887030459959793044651283036539901528068026981401181132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=740951151506817025966887030459959793044651283036539901528068026981401181132 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"40.xbar_error_random.79562753976773885417501767533743257071451095141684957281595222303156787268731","seed":79562753976773885417501767533743257071451095141684957281595222303156787268731,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2093796475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2093796475' seed=79562753976773885417501767533743257071451095141684957281595222303156787268731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79562753976773885417501767533743257071451095141684957281595222303156787268731 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"40.xbar_unmapped_addr.87461352146285635980446923715460692500018088581541085542416499442996576524469","seed":87461352146285635980446923715460692500018088581541085542416499442996576524469,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2998933685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2998933685' seed=87461352146285635980446923715460692500018088581541085542416499442996576524469 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87461352146285635980446923715460692500018088581541085542416499442996576524469 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"40.xbar_error_and_unmapped_addr.50092918747579694636706804100375619536227714046493721166004293436144747884153","seed":50092918747579694636706804100375619536227714046493721166004293436144747884153,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=642068089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.642068089' seed=50092918747579694636706804100375619536227714046493721166004293436144747884153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50092918747579694636706804100375619536227714046493721166004293436144747884153 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"40.xbar_stress_all.4665170495765830817259924072709732564437852818835590810050405735832895967378","seed":4665170495765830817259924072709732564437852818835590810050405735832895967378,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2117161106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2117161106' seed=4665170495765830817259924072709732564437852818835590810050405735832895967378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4665170495765830817259924072709732564437852818835590810050405735832895967378 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"40.xbar_stress_all_with_rand_reset.92140525885716966265835419150634764695121349535918106690306518270316710931528","seed":92140525885716966265835419150634764695121349535918106690306518270316710931528,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3891735624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.3891735624' seed=92140525885716966265835419150634764695121349535918106690306518270316710931528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92140525885716966265835419150634764695121349535918106690306518270316710931528 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"40.xbar_stress_all_with_error.1253344700187984643915233142049281622137592629347916734851716728627191653001","seed":1253344700187984643915233142049281622137592629347916734851716728627191653001,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=608739977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.608739977' seed=1253344700187984643915233142049281622137592629347916734851716728627191653001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1253344700187984643915233142049281622137592629347916734851716728627191653001 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"40.xbar_stress_all_with_reset_error.13776506202521125112651602986063759812152100934936587143921732200176300959824","seed":13776506202521125112651602986063759812152100934936587143921732200176300959824,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3523848272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3523848272' seed=13776506202521125112651602986063759812152100934936587143921732200176300959824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=13776506202521125112651602986063759812152100934936587143921732200176300959824 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"41.chip_sw_all_escalation_resets.70531516867549176914094041211827575818754881967035424052245016294373936593854","seed":70531516867549176914094041211827575818754881967035424052245016294373936593854,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=495451070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.495451070' seed=70531516867549176914094041211827575818754881967035424052245016294373936593854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70531516867549176914094041211827575818754881967035424052245016294373936593854 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.45260252465005442567904269753336267048879485471463834875970450519195914274230","seed":45260252465005442567904269753336267048879485471463834875970450519195914274230,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"41.xbar_smoke.98198491791842374088729075301419467982708972967195044496324942122978758677118","seed":98198491791842374088729075301419467982708972967195044496324942122978758677118,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3761558142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3761558142' seed=98198491791842374088729075301419467982708972967195044496324942122978758677118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98198491791842374088729075301419467982708972967195044496324942122978758677118 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"41.xbar_smoke_zero_delays.87844023295951561546134770679450099079376578990420816395719964918650383406121","seed":87844023295951561546134770679450099079376578990420816395719964918650383406121,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1677497385 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1677497385' seed=87844023295951561546134770679450099079376578990420816395719964918650383406121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87844023295951561546134770679450099079376578990420816395719964918650383406121 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"41.xbar_smoke_large_delays.95085466464030239396279278617561527896584306442390550108323687510677834413231","seed":95085466464030239396279278617561527896584306442390550108323687510677834413231,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2554836143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2554836143' seed=95085466464030239396279278617561527896584306442390550108323687510677834413231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=95085466464030239396279278617561527896584306442390550108323687510677834413231 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"41.xbar_smoke_slow_rsp.20716276379218363996913370030484152874930869205499088068041967139576784924388","seed":20716276379218363996913370030484152874930869205499088068041967139576784924388,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3959467748 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3959467748' seed=20716276379218363996913370030484152874930869205499088068041967139576784924388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20716276379218363996913370030484152874930869205499088068041967139576784924388 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"41.xbar_random.98121680565266290542588969523535528429004556470170225150886993658184962841290","seed":98121680565266290542588969523535528429004556470170225150886993658184962841290,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2645990090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2645990090' seed=98121680565266290542588969523535528429004556470170225150886993658184962841290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98121680565266290542588969523535528429004556470170225150886993658184962841290 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"41.xbar_random_zero_delays.32401906948078980142275118569264875618858444767496445768511989252428254729532","seed":32401906948078980142275118569264875618858444767496445768511989252428254729532,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3102528828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3102528828' seed=32401906948078980142275118569264875618858444767496445768511989252428254729532 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32401906948078980142275118569264875618858444767496445768511989252428254729532 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"41.xbar_random_large_delays.16477335250294798720895953262465530847781199033379917760314056787109515272490","seed":16477335250294798720895953262465530847781199033379917760314056787109515272490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3944915242 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3944915242' seed=16477335250294798720895953262465530847781199033379917760314056787109515272490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16477335250294798720895953262465530847781199033379917760314056787109515272490 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"41.xbar_random_slow_rsp.27371058196091791010505250677155009492455015639803334937158957563909326683168","seed":27371058196091791010505250677155009492455015639803334937158957563909326683168,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=108968992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.108968992' seed=27371058196091791010505250677155009492455015639803334937158957563909326683168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27371058196091791010505250677155009492455015639803334937158957563909326683168 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"41.xbar_access_same_device.30197845904050175292799359498937829303872787826087769427210292382747759119515","seed":30197845904050175292799359498937829303872787826087769427210292382747759119515,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169829531 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4169829531' seed=30197845904050175292799359498937829303872787826087769427210292382747759119515 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30197845904050175292799359498937829303872787826087769427210292382747759119515 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"41.xbar_access_same_device_slow_rsp.56648513136390313432291170691698494882808719529988882133341875443673201608176","seed":56648513136390313432291170691698494882808719529988882133341875443673201608176,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714024944 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3714024944' seed=56648513136390313432291170691698494882808719529988882133341875443673201608176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56648513136390313432291170691698494882808719529988882133341875443673201608176 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"41.xbar_same_source.50352049439196009779153348237189858100735346057836317880714858146998078888766","seed":50352049439196009779153348237189858100735346057836317880714858146998078888766,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1232558910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1232558910' seed=50352049439196009779153348237189858100735346057836317880714858146998078888766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50352049439196009779153348237189858100735346057836317880714858146998078888766 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"41.xbar_error_random.94925177094665727207258200452377562648498032944727093098633690480422568558875","seed":94925177094665727207258200452377562648498032944727093098633690480422568558875,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2886959387 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2886959387' seed=94925177094665727207258200452377562648498032944727093098633690480422568558875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94925177094665727207258200452377562648498032944727093098633690480422568558875 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"41.xbar_unmapped_addr.87625086982559798516107796977205386805870624442895338122672006531480604401496","seed":87625086982559798516107796977205386805870624442895338122672006531480604401496,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2114477912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2114477912' seed=87625086982559798516107796977205386805870624442895338122672006531480604401496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87625086982559798516107796977205386805870624442895338122672006531480604401496 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"41.xbar_error_and_unmapped_addr.67275448675903143813316725256091346189308951447580135722575099677332548721801","seed":67275448675903143813316725256091346189308951447580135722575099677332548721801,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2660605065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2660605065' seed=67275448675903143813316725256091346189308951447580135722575099677332548721801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=67275448675903143813316725256091346189308951447580135722575099677332548721801 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"41.xbar_stress_all.1198972911621050136504545672356920375305985422853245690612742943641657290877","seed":1198972911621050136504545672356920375305985422853245690612742943641657290877,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=476983421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.476983421' seed=1198972911621050136504545672356920375305985422853245690612742943641657290877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1198972911621050136504545672356920375305985422853245690612742943641657290877 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"41.xbar_stress_all_with_rand_reset.73080279087660672266650781693566835693300049662258453543228781717644639670572","seed":73080279087660672266650781693566835693300049662258453543228781717644639670572,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3671527724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3671527724' seed=73080279087660672266650781693566835693300049662258453543228781717644639670572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73080279087660672266650781693566835693300049662258453543228781717644639670572 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"41.xbar_stress_all_with_error.40818922950918320355650700823778099159848056058490901030619984119053564766898","seed":40818922950918320355650700823778099159848056058490901030619984119053564766898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3069700786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3069700786' seed=40818922950918320355650700823778099159848056058490901030619984119053564766898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40818922950918320355650700823778099159848056058490901030619984119053564766898 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"41.xbar_stress_all_with_reset_error.30177519725188845893799611893200371339358046277069538471768236276317933797358","seed":30177519725188845893799611893200371339358046277069538471768236276317933797358,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363331566 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.363331566' seed=30177519725188845893799611893200371339358046277069538471768236276317933797358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30177519725188845893799611893200371339358046277069538471768236276317933797358 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"42.chip_sw_all_escalation_resets.12195668943319336628696097558446821720855051454171566878560650488858771329540","seed":12195668943319336628696097558446821720855051454171566878560650488858771329540,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3471446532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.3471446532' seed=12195668943319336628696097558446821720855051454171566878560650488858771329540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12195668943319336628696097558446821720855051454171566878560650488858771329540 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.37436834907280043485876755877555305409897652398567070099853610486260085673209","seed":37436834907280043485876755877555305409897652398567070099853610486260085673209,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"42.xbar_smoke.105363168432176005886997667893486337914098657295033684561820169407898287051096","seed":105363168432176005886997667893486337914098657295033684561820169407898287051096,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3699085656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3699085656' seed=105363168432176005886997667893486337914098657295033684561820169407898287051096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105363168432176005886997667893486337914098657295033684561820169407898287051096 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"42.xbar_smoke_zero_delays.19754635502951590136486827349000033835226693542052099943880366611080680598434","seed":19754635502951590136486827349000033835226693542052099943880366611080680598434,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1020292002 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1020292002' seed=19754635502951590136486827349000033835226693542052099943880366611080680598434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19754635502951590136486827349000033835226693542052099943880366611080680598434 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"42.xbar_smoke_large_delays.109266241500961354052665035784733168538195024049609918737624911416430352163837","seed":109266241500961354052665035784733168538195024049609918737624911416430352163837,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2314757117 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2314757117' seed=109266241500961354052665035784733168538195024049609918737624911416430352163837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109266241500961354052665035784733168538195024049609918737624911416430352163837 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"42.xbar_smoke_slow_rsp.59344675383273158500858404387656411864929504417291485580828813609534284496604","seed":59344675383273158500858404387656411864929504417291485580828813609534284496604,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406533340 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1406533340' seed=59344675383273158500858404387656411864929504417291485580828813609534284496604 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59344675383273158500858404387656411864929504417291485580828813609534284496604 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"42.xbar_random.100204821046945105629253734595606576749074978909449181844836485352156757882553","seed":100204821046945105629253734595606576749074978909449181844836485352156757882553,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778068665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2778068665' seed=100204821046945105629253734595606576749074978909449181844836485352156757882553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100204821046945105629253734595606576749074978909449181844836485352156757882553 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"42.xbar_random_zero_delays.106467793252232336497686424065811665582392276302993905100690015153421454646218","seed":106467793252232336497686424065811665582392276302993905100690015153421454646218,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448923594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2448923594' seed=106467793252232336497686424065811665582392276302993905100690015153421454646218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106467793252232336497686424065811665582392276302993905100690015153421454646218 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"42.xbar_random_large_delays.48977499941214464866401229590151058506319083170960230102271779743911721813658","seed":48977499941214464866401229590151058506319083170960230102271779743911721813658,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3868182170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3868182170' seed=48977499941214464866401229590151058506319083170960230102271779743911721813658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48977499941214464866401229590151058506319083170960230102271779743911721813658 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"42.xbar_random_slow_rsp.35587228872703415577341985890408169564296402423328370871069622093382786246780","seed":35587228872703415577341985890408169564296402423328370871069622093382786246780,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4234963068 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4234963068' seed=35587228872703415577341985890408169564296402423328370871069622093382786246780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35587228872703415577341985890408169564296402423328370871069622093382786246780 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"42.xbar_access_same_device.92907445319325770715978834599198180392309623032789304580404749128217449763729","seed":92907445319325770715978834599198180392309623032789304580404749128217449763729,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3500184465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3500184465' seed=92907445319325770715978834599198180392309623032789304580404749128217449763729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92907445319325770715978834599198180392309623032789304580404749128217449763729 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"42.xbar_access_same_device_slow_rsp.42722481814290675608049780157599885554194191167556315163012489033651158424994","seed":42722481814290675608049780157599885554194191167556315163012489033651158424994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=403873186 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.403873186' seed=42722481814290675608049780157599885554194191167556315163012489033651158424994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42722481814290675608049780157599885554194191167556315163012489033651158424994 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"42.xbar_same_source.48260748782021120487649947830851087273152324627187633852976332232901973097760","seed":48260748782021120487649947830851087273152324627187633852976332232901973097760,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3549281568 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3549281568' seed=48260748782021120487649947830851087273152324627187633852976332232901973097760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48260748782021120487649947830851087273152324627187633852976332232901973097760 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"42.xbar_error_random.87246745196914335164004756770559851527227963988491652941116289977032177905461","seed":87246745196914335164004756770559851527227963988491652941116289977032177905461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=996962101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.996962101' seed=87246745196914335164004756770559851527227963988491652941116289977032177905461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87246745196914335164004756770559851527227963988491652941116289977032177905461 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"42.xbar_unmapped_addr.1466778194228784093191501739631045206873356632809961868003192893837035536082","seed":1466778194228784093191501739631045206873356632809961868003192893837035536082,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2441707218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2441707218' seed=1466778194228784093191501739631045206873356632809961868003192893837035536082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1466778194228784093191501739631045206873356632809961868003192893837035536082 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"42.xbar_error_and_unmapped_addr.46000320095839597322483834406709099441848093766128950291279251250643756281152","seed":46000320095839597322483834406709099441848093766128950291279251250643756281152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391436608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2391436608' seed=46000320095839597322483834406709099441848093766128950291279251250643756281152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46000320095839597322483834406709099441848093766128950291279251250643756281152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"42.xbar_stress_all.87405566312340787406051182647807820646498585498785115959087473538874050242395","seed":87405566312340787406051182647807820646498585498785115959087473538874050242395,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4000737115 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4000737115' seed=87405566312340787406051182647807820646498585498785115959087473538874050242395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=87405566312340787406051182647807820646498585498785115959087473538874050242395 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"42.xbar_stress_all_with_rand_reset.42596851242589644477847986841303200876616695465679062128212103781910239320669","seed":42596851242589644477847986841303200876616695465679062128212103781910239320669,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2059213405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2059213405' seed=42596851242589644477847986841303200876616695465679062128212103781910239320669 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42596851242589644477847986841303200876616695465679062128212103781910239320669 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"42.xbar_stress_all_with_error.34257846810529110571140382426653512385455315739755724521685525136152558598579","seed":34257846810529110571140382426653512385455315739755724521685525136152558598579,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2922150323 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2922150323' seed=34257846810529110571140382426653512385455315739755724521685525136152558598579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34257846810529110571140382426653512385455315739755724521685525136152558598579 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"42.xbar_stress_all_with_reset_error.86129582782623637384987427478371359711904558425961426194438866031881766199573","seed":86129582782623637384987427478371359711904558425961426194438866031881766199573,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704171285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2704171285' seed=86129582782623637384987427478371359711904558425961426194438866031881766199573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86129582782623637384987427478371359711904558425961426194438866031881766199573 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"43.chip_sw_all_escalation_resets.21857597559690782323761083955713960306541092228019531956481112973966589127908","seed":21857597559690782323761083955713960306541092228019531956481112973966589127908,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1724738788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1724738788' seed=21857597559690782323761083955713960306541092228019531956481112973966589127908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21857597559690782323761083955713960306541092228019531956481112973966589127908 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.84866085979245743505122890158102524187864010356539693688674230062419846985319","seed":84866085979245743505122890158102524187864010356539693688674230062419846985319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"43.xbar_smoke.82122360392080530567483731262646862344072677977376722238859069597742681069266","seed":82122360392080530567483731262646862344072677977376722238859069597742681069266,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4042823378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.4042823378' seed=82122360392080530567483731262646862344072677977376722238859069597742681069266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82122360392080530567483731262646862344072677977376722238859069597742681069266 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"43.xbar_smoke_zero_delays.66276706603967176659313181578043740563687069244091710445436072974380280736333","seed":66276706603967176659313181578043740563687069244091710445436072974380280736333,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4274416205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.4274416205' seed=66276706603967176659313181578043740563687069244091710445436072974380280736333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66276706603967176659313181578043740563687069244091710445436072974380280736333 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"43.xbar_smoke_large_delays.81169958323697183294918095574253269557315868681888858789471804364071755275094","seed":81169958323697183294918095574253269557315868681888858789471804364071755275094,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1160469334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1160469334' seed=81169958323697183294918095574253269557315868681888858789471804364071755275094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81169958323697183294918095574253269557315868681888858789471804364071755275094 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"43.xbar_smoke_slow_rsp.10802217446885945814292830708810170405756039065808559048398148179574006263152","seed":10802217446885945814292830708810170405756039065808559048398148179574006263152,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2719264112 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2719264112' seed=10802217446885945814292830708810170405756039065808559048398148179574006263152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10802217446885945814292830708810170405756039065808559048398148179574006263152 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"43.xbar_random.58612312400139110063275668053443624887915552745561485973369091449346060716466","seed":58612312400139110063275668053443624887915552745561485973369091449346060716466,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=891816370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.891816370' seed=58612312400139110063275668053443624887915552745561485973369091449346060716466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=58612312400139110063275668053443624887915552745561485973369091449346060716466 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"43.xbar_random_zero_delays.31558864821233743759470276362029986924935583728425513160206688375467412514843","seed":31558864821233743759470276362029986924935583728425513160206688375467412514843,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3333384219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3333384219' seed=31558864821233743759470276362029986924935583728425513160206688375467412514843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31558864821233743759470276362029986924935583728425513160206688375467412514843 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"43.xbar_random_large_delays.112713459546689292839595592318189858388131990515691418714869725197892233995894","seed":112713459546689292839595592318189858388131990515691418714869725197892233995894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19670646 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.19670646' seed=112713459546689292839595592318189858388131990515691418714869725197892233995894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112713459546689292839595592318189858388131990515691418714869725197892233995894 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"43.xbar_random_slow_rsp.79781883108653997146779466338640460038486502558645891390272204227219356714580","seed":79781883108653997146779466338640460038486502558645891390272204227219356714580,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1413023316 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1413023316' seed=79781883108653997146779466338640460038486502558645891390272204227219356714580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79781883108653997146779466338640460038486502558645891390272204227219356714580 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"43.xbar_access_same_device.89052597831510240713013118490953729375397004190085958563995124623147853102902","seed":89052597831510240713013118490953729375397004190085958563995124623147853102902,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4095688502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4095688502' seed=89052597831510240713013118490953729375397004190085958563995124623147853102902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89052597831510240713013118490953729375397004190085958563995124623147853102902 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"43.xbar_access_same_device_slow_rsp.20351795939889411791966259012586293951000660245247177021738859607151580122755","seed":20351795939889411791966259012586293951000660245247177021738859607151580122755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2662960771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2662960771' seed=20351795939889411791966259012586293951000660245247177021738859607151580122755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20351795939889411791966259012586293951000660245247177021738859607151580122755 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"43.xbar_same_source.28500347345001892885517989845293633870981845522676018260350938133895686888905","seed":28500347345001892885517989845293633870981845522676018260350938133895686888905,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=727948745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.727948745' seed=28500347345001892885517989845293633870981845522676018260350938133895686888905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=28500347345001892885517989845293633870981845522676018260350938133895686888905 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"43.xbar_error_random.9649774208362799725200852973321611174266873227733460550420282970033446694088","seed":9649774208362799725200852973321611174266873227733460550420282970033446694088,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1165733064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1165733064' seed=9649774208362799725200852973321611174266873227733460550420282970033446694088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9649774208362799725200852973321611174266873227733460550420282970033446694088 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"43.xbar_unmapped_addr.103578274095976873205741377228666856947477338321755360568853182907923006989201","seed":103578274095976873205741377228666856947477338321755360568853182907923006989201,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77833105 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.77833105' seed=103578274095976873205741377228666856947477338321755360568853182907923006989201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103578274095976873205741377228666856947477338321755360568853182907923006989201 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"43.xbar_error_and_unmapped_addr.16296529653604435843698518303602863164359324698636189950039710679451507856076","seed":16296529653604435843698518303602863164359324698636189950039710679451507856076,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202505932 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2202505932' seed=16296529653604435843698518303602863164359324698636189950039710679451507856076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16296529653604435843698518303602863164359324698636189950039710679451507856076 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"43.xbar_stress_all.33131496645759332950667848108118748345404526497699641606862671344359235690218","seed":33131496645759332950667848108118748345404526497699641606862671344359235690218,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232538346 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3232538346' seed=33131496645759332950667848108118748345404526497699641606862671344359235690218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33131496645759332950667848108118748345404526497699641606862671344359235690218 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"43.xbar_stress_all_with_rand_reset.49436241078578445800296952797222089569004339072073701165826851966916375812422","seed":49436241078578445800296952797222089569004339072073701165826851966916375812422,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=499063110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.499063110' seed=49436241078578445800296952797222089569004339072073701165826851966916375812422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49436241078578445800296952797222089569004339072073701165826851966916375812422 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"43.xbar_stress_all_with_error.21426910429971533077171607784309611196165122630189300472415063081022276660995","seed":21426910429971533077171607784309611196165122630189300472415063081022276660995,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1257926403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1257926403' seed=21426910429971533077171607784309611196165122630189300472415063081022276660995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21426910429971533077171607784309611196165122630189300472415063081022276660995 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"43.xbar_stress_all_with_reset_error.94688355652376592101002452886785793793435769083055789138779444836995548169957","seed":94688355652376592101002452886785793793435769083055789138779444836995548169957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723896037 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.723896037' seed=94688355652376592101002452886785793793435769083055789138779444836995548169957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=94688355652376592101002452886785793793435769083055789138779444836995548169957 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"44.chip_sw_all_escalation_resets.82419387911222356907432946568973037639769000395259188764549203800651738048730","seed":82419387911222356907432946568973037639769000395259188764549203800651738048730,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4274710746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.4274710746' seed=82419387911222356907432946568973037639769000395259188764549203800651738048730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82419387911222356907432946568973037639769000395259188764549203800651738048730 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.43924703571159781005967923160525018385520265120621227833047345638734403390690","seed":43924703571159781005967923160525018385520265120621227833047345638734403390690,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"44.xbar_smoke.60892103468168467752971804334901174701778291721958104819754480073670550239455","seed":60892103468168467752971804334901174701778291721958104819754480073670550239455,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3448912095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3448912095' seed=60892103468168467752971804334901174701778291721958104819754480073670550239455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60892103468168467752971804334901174701778291721958104819754480073670550239455 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"44.xbar_smoke_zero_delays.7619672284166847744419840796409848488950613465430134855672578726251869339335","seed":7619672284166847744419840796409848488950613465430134855672578726251869339335,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3720183495 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3720183495' seed=7619672284166847744419840796409848488950613465430134855672578726251869339335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7619672284166847744419840796409848488950613465430134855672578726251869339335 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"44.xbar_smoke_large_delays.106145218733723926010947695520108232174514079345362284916134361978460023870148","seed":106145218733723926010947695520108232174514079345362284916134361978460023870148,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4108899012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.4108899012' seed=106145218733723926010947695520108232174514079345362284916134361978460023870148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106145218733723926010947695520108232174514079345362284916134361978460023870148 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"44.xbar_smoke_slow_rsp.107159955220715571145262304677813613561603493531338824317581604350896609716927","seed":107159955220715571145262304677813613561603493531338824317581604350896609716927,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=439380671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.439380671' seed=107159955220715571145262304677813613561603493531338824317581604350896609716927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=107159955220715571145262304677813613561603493531338824317581604350896609716927 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"44.xbar_random.79542313028125490902116041253752857058173389792740626044761660154713401028529","seed":79542313028125490902116041253752857058173389792740626044761660154713401028529,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=47542193 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.47542193' seed=79542313028125490902116041253752857058173389792740626044761660154713401028529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=79542313028125490902116041253752857058173389792740626044761660154713401028529 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"44.xbar_random_zero_delays.99185685595663223364707017741357917576036714738010013231099637939024517566637","seed":99185685595663223364707017741357917576036714738010013231099637939024517566637,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=197562541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.197562541' seed=99185685595663223364707017741357917576036714738010013231099637939024517566637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99185685595663223364707017741357917576036714738010013231099637939024517566637 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"44.xbar_random_large_delays.74009174832431337777877614193110084248410265286597957553774739132249350280405","seed":74009174832431337777877614193110084248410265286597957553774739132249350280405,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246855381 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3246855381' seed=74009174832431337777877614193110084248410265286597957553774739132249350280405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74009174832431337777877614193110084248410265286597957553774739132249350280405 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"44.xbar_random_slow_rsp.53413756546500745218159085585760414559530198871203232518489579937936325074297","seed":53413756546500745218159085585760414559530198871203232518489579937936325074297,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560037753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3560037753' seed=53413756546500745218159085585760414559530198871203232518489579937936325074297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53413756546500745218159085585760414559530198871203232518489579937936325074297 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"44.xbar_access_same_device.54828289962481101172936804809453136624345785331239792599474249431151590959418","seed":54828289962481101172936804809453136624345785331239792599474249431151590959418,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3657886010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3657886010' seed=54828289962481101172936804809453136624345785331239792599474249431151590959418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54828289962481101172936804809453136624345785331239792599474249431151590959418 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"44.xbar_access_same_device_slow_rsp.109048132579104232666346754703202514072083543959761160584246871304966004314069","seed":109048132579104232666346754703202514072083543959761160584246871304966004314069,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3436220373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3436220373' seed=109048132579104232666346754703202514072083543959761160584246871304966004314069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109048132579104232666346754703202514072083543959761160584246871304966004314069 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"44.xbar_same_source.91162799587457744044599868250965774448927491950087264401009443956998546185816","seed":91162799587457744044599868250965774448927491950087264401009443956998546185816,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037257304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3037257304' seed=91162799587457744044599868250965774448927491950087264401009443956998546185816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91162799587457744044599868250965774448927491950087264401009443956998546185816 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"44.xbar_error_random.85326610802124292562677311522785267623420667381591024576767600784443459529254","seed":85326610802124292562677311522785267623420667381591024576767600784443459529254,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=127429158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.127429158' seed=85326610802124292562677311522785267623420667381591024576767600784443459529254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85326610802124292562677311522785267623420667381591024576767600784443459529254 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"44.xbar_unmapped_addr.110818341183228594775888865071208074375232108205767730821053771687312384555371","seed":110818341183228594775888865071208074375232108205767730821053771687312384555371,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039787371 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3039787371' seed=110818341183228594775888865071208074375232108205767730821053771687312384555371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110818341183228594775888865071208074375232108205767730821053771687312384555371 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"44.xbar_error_and_unmapped_addr.2908608613735016202948926686281901236606005170747950663007035173879484269528","seed":2908608613735016202948926686281901236606005170747950663007035173879484269528,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=304366552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.304366552' seed=2908608613735016202948926686281901236606005170747950663007035173879484269528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2908608613735016202948926686281901236606005170747950663007035173879484269528 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"44.xbar_stress_all.19363031983884861851645233343674064629107693929449941652732530660575609063376","seed":19363031983884861851645233343674064629107693929449941652732530660575609063376,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159408080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4159408080' seed=19363031983884861851645233343674064629107693929449941652732530660575609063376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=19363031983884861851645233343674064629107693929449941652732530660575609063376 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"44.xbar_stress_all_with_rand_reset.25663557554589123039866960225447254385516697220953419806276433306699730658548","seed":25663557554589123039866960225447254385516697220953419806276433306699730658548,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1523459316 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1523459316' seed=25663557554589123039866960225447254385516697220953419806276433306699730658548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25663557554589123039866960225447254385516697220953419806276433306699730658548 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"44.xbar_stress_all_with_error.99595272849725084704671885625370933814790778563517355762873165917321008617641","seed":99595272849725084704671885625370933814790778563517355762873165917321008617641,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2886834345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2886834345' seed=99595272849725084704671885625370933814790778563517355762873165917321008617641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99595272849725084704671885625370933814790778563517355762873165917321008617641 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"44.xbar_stress_all_with_reset_error.22441885707404670404132684126693412805367190342527697111351483064754514761504","seed":22441885707404670404132684126693412805367190342527697111351483064754514761504,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=853088032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.853088032' seed=22441885707404670404132684126693412805367190342527697111351483064754514761504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22441885707404670404132684126693412805367190342527697111351483064754514761504 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"45.chip_sw_all_escalation_resets.43025665050692383425869698792570401040720756917919446908432356229252425159957","seed":43025665050692383425869698792570401040720756917919446908432356229252425159957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3483866389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3483866389' seed=43025665050692383425869698792570401040720756917919446908432356229252425159957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43025665050692383425869698792570401040720756917919446908432356229252425159957 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.7251602548618225631802488961800083445827710291956748798084285686226959650774","seed":7251602548618225631802488961800083445827710291956748798084285686226959650774,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"45.xbar_smoke.21983159837966636531164229553596389785275018080187673806877062619849457530165","seed":21983159837966636531164229553596389785275018080187673806877062619849457530165,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4045534517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4045534517' seed=21983159837966636531164229553596389785275018080187673806877062619849457530165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21983159837966636531164229553596389785275018080187673806877062619849457530165 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"45.xbar_smoke_zero_delays.101597230104821845396525413655379398788978015380208161514406184795029807691096","seed":101597230104821845396525413655379398788978015380208161514406184795029807691096,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4073321816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.4073321816' seed=101597230104821845396525413655379398788978015380208161514406184795029807691096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=101597230104821845396525413655379398788978015380208161514406184795029807691096 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"45.xbar_smoke_large_delays.25859628523177582945805071144510055690546154704828532792825662810098334278117","seed":25859628523177582945805071144510055690546154704828532792825662810098334278117,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4110787045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4110787045' seed=25859628523177582945805071144510055690546154704828532792825662810098334278117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25859628523177582945805071144510055690546154704828532792825662810098334278117 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"45.xbar_smoke_slow_rsp.56072818817592188560019971856760799471370131727691741976559625038240741840446","seed":56072818817592188560019971856760799471370131727691741976559625038240741840446,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=684709438 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.684709438' seed=56072818817592188560019971856760799471370131727691741976559625038240741840446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56072818817592188560019971856760799471370131727691741976559625038240741840446 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"45.xbar_random.77736566484371680309281130533923008468197054179173846034209129898205556006798","seed":77736566484371680309281130533923008468197054179173846034209129898205556006798,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2667863950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2667863950' seed=77736566484371680309281130533923008468197054179173846034209129898205556006798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77736566484371680309281130533923008468197054179173846034209129898205556006798 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"45.xbar_random_zero_delays.73996686635994342582372040018262486668951132898372547339298507705641102123211","seed":73996686635994342582372040018262486668951132898372547339298507705641102123211,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2141364427 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2141364427' seed=73996686635994342582372040018262486668951132898372547339298507705641102123211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73996686635994342582372040018262486668951132898372547339298507705641102123211 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"45.xbar_random_large_delays.81417206503824096406950967987647421463377024181812994017489807499150160153616","seed":81417206503824096406950967987647421463377024181812994017489807499150160153616,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2858273808 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2858273808' seed=81417206503824096406950967987647421463377024181812994017489807499150160153616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81417206503824096406950967987647421463377024181812994017489807499150160153616 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"45.xbar_random_slow_rsp.36998801456136038322629680067463062251057530568728475154255597847316428533261","seed":36998801456136038322629680067463062251057530568728475154255597847316428533261,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2709564941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2709564941' seed=36998801456136038322629680067463062251057530568728475154255597847316428533261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36998801456136038322629680067463062251057530568728475154255597847316428533261 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"45.xbar_access_same_device.48951288173377836549310513386054626654681068031491426314211914257944004750957","seed":48951288173377836549310513386054626654681068031491426314211914257944004750957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=992439917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.992439917' seed=48951288173377836549310513386054626654681068031491426314211914257944004750957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=48951288173377836549310513386054626654681068031491426314211914257944004750957 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"45.xbar_access_same_device_slow_rsp.17454223976818972948648952339166760266959511795323181528390871912300592291441","seed":17454223976818972948648952339166760266959511795323181528390871912300592291441,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2708528753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2708528753' seed=17454223976818972948648952339166760266959511795323181528390871912300592291441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17454223976818972948648952339166760266959511795323181528390871912300592291441 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"45.xbar_same_source.64860185486809537764993492455001017091862718779551109361547168221592136784014","seed":64860185486809537764993492455001017091862718779551109361547168221592136784014,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525908622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3525908622' seed=64860185486809537764993492455001017091862718779551109361547168221592136784014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=64860185486809537764993492455001017091862718779551109361547168221592136784014 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"45.xbar_error_random.36532796250937393465068943109750521733999167759427440721690944782929923592610","seed":36532796250937393465068943109750521733999167759427440721690944782929923592610,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276826018 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1276826018' seed=36532796250937393465068943109750521733999167759427440721690944782929923592610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=36532796250937393465068943109750521733999167759427440721690944782929923592610 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"45.xbar_unmapped_addr.42210685005500857170349944041336557765670826471187868032687623340332828100629","seed":42210685005500857170349944041336557765670826471187868032687623340332828100629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=230721557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.230721557' seed=42210685005500857170349944041336557765670826471187868032687623340332828100629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42210685005500857170349944041336557765670826471187868032687623340332828100629 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"45.xbar_error_and_unmapped_addr.59290791329220655712841292577125826566724796389193718535595879774803906190073","seed":59290791329220655712841292577125826566724796389193718535595879774803906190073,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3774274297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3774274297' seed=59290791329220655712841292577125826566724796389193718535595879774803906190073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59290791329220655712841292577125826566724796389193718535595879774803906190073 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"45.xbar_stress_all.65902642069786531992402759114139055939943394351360751414513549351627343508090","seed":65902642069786531992402759114139055939943394351360751414513549351627343508090,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250303610 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3250303610' seed=65902642069786531992402759114139055939943394351360751414513549351627343508090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65902642069786531992402759114139055939943394351360751414513549351627343508090 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"45.xbar_stress_all_with_rand_reset.11999437793550086065857518156645244108249819218749388533185714850747441015389","seed":11999437793550086065857518156645244108249819218749388533185714850747441015389,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1795746397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.1795746397' seed=11999437793550086065857518156645244108249819218749388533185714850747441015389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=11999437793550086065857518156645244108249819218749388533185714850747441015389 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"45.xbar_stress_all_with_error.35891906659635020860377313712287749308071493115362551191717885842075602695051","seed":35891906659635020860377313712287749308071493115362551191717885842075602695051,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3872961419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3872961419' seed=35891906659635020860377313712287749308071493115362551191717885842075602695051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35891906659635020860377313712287749308071493115362551191717885842075602695051 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"45.xbar_stress_all_with_reset_error.45283729868528271032448524535801166627860844742520986244190156590392008344363","seed":45283729868528271032448524535801166627860844742520986244190156590392008344363,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161317675 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.161317675' seed=45283729868528271032448524535801166627860844742520986244190156590392008344363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45283729868528271032448524535801166627860844742520986244190156590392008344363 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"46.chip_sw_all_escalation_resets.65142599826340680834913761165490903471685594226397943559679082418503519853353","seed":65142599826340680834913761165490903471685594226397943559679082418503519853353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2849266473 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.2849266473' seed=65142599826340680834913761165490903471685594226397943559679082418503519853353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65142599826340680834913761165490903471685594226397943559679082418503519853353 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.13862186028049212530346200445902387894672251177296602038154896451835156317819","seed":13862186028049212530346200445902387894672251177296602038154896451835156317819,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"46.xbar_smoke.9893429746731989567891558363514429675279645505630366725517060186598572016672","seed":9893429746731989567891558363514429675279645505630366725517060186598572016672,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1647559712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1647559712' seed=9893429746731989567891558363514429675279645505630366725517060186598572016672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9893429746731989567891558363514429675279645505630366725517060186598572016672 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"46.xbar_smoke_zero_delays.1157296462587205021052807336947237409147864857178939944750945686916441512357","seed":1157296462587205021052807336947237409147864857178939944750945686916441512357,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3811776933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3811776933' seed=1157296462587205021052807336947237409147864857178939944750945686916441512357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1157296462587205021052807336947237409147864857178939944750945686916441512357 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"46.xbar_smoke_large_delays.7807624788033717458582525100182322798950816661398483522303189567044467307421","seed":7807624788033717458582525100182322798950816661398483522303189567044467307421,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3207869341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3207869341' seed=7807624788033717458582525100182322798950816661398483522303189567044467307421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7807624788033717458582525100182322798950816661398483522303189567044467307421 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"46.xbar_smoke_slow_rsp.99361358768274633922652684977968296019478936597456537031542846402949248970698","seed":99361358768274633922652684977968296019478936597456537031542846402949248970698,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=183234506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.183234506' seed=99361358768274633922652684977968296019478936597456537031542846402949248970698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99361358768274633922652684977968296019478936597456537031542846402949248970698 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"46.xbar_random.99835183783237289821055210046977540647292790267085595940658822740552796771446","seed":99835183783237289821055210046977540647292790267085595940658822740552796771446,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625644662 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.625644662' seed=99835183783237289821055210046977540647292790267085595940658822740552796771446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99835183783237289821055210046977540647292790267085595940658822740552796771446 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"46.xbar_random_zero_delays.98685408582769447414772943957939489667794612055645567878159587408664013628444","seed":98685408582769447414772943957939489667794612055645567878159587408664013628444,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009471516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3009471516' seed=98685408582769447414772943957939489667794612055645567878159587408664013628444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98685408582769447414772943957939489667794612055645567878159587408664013628444 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"46.xbar_random_large_delays.17074120163422444158959327549842186461167614741785157165898547525445183867627","seed":17074120163422444158959327549842186461167614741785157165898547525445183867627,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767798507 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3767798507' seed=17074120163422444158959327549842186461167614741785157165898547525445183867627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17074120163422444158959327549842186461167614741785157165898547525445183867627 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"46.xbar_random_slow_rsp.32618099241115227416026012465358568231207368852052080962354577345826443303115","seed":32618099241115227416026012465358568231207368852052080962354577345826443303115,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3745323211 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3745323211' seed=32618099241115227416026012465358568231207368852052080962354577345826443303115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32618099241115227416026012465358568231207368852052080962354577345826443303115 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"46.xbar_access_same_device.43911730532639667016793332350605307631335462078957199670761170710111313108792","seed":43911730532639667016793332350605307631335462078957199670761170710111313108792,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1181130552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1181130552' seed=43911730532639667016793332350605307631335462078957199670761170710111313108792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=43911730532639667016793332350605307631335462078957199670761170710111313108792 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"46.xbar_access_same_device_slow_rsp.114336641165145839338247808736233074904886686540574474901599303829781825959380","seed":114336641165145839338247808736233074904886686540574474901599303829781825959380,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=671593940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.671593940' seed=114336641165145839338247808736233074904886686540574474901599303829781825959380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=114336641165145839338247808736233074904886686540574474901599303829781825959380 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"46.xbar_same_source.56847774169865012831084867887374540396902158771641351742693193562124674498964","seed":56847774169865012831084867887374540396902158771641351742693193562124674498964,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3752165780 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3752165780' seed=56847774169865012831084867887374540396902158771641351742693193562124674498964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=56847774169865012831084867887374540396902158771641351742693193562124674498964 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"46.xbar_error_random.35536489824867783254648659452939671687510903401837397577838141014455770811503","seed":35536489824867783254648659452939671687510903401837397577838141014455770811503,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2908884079 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2908884079' seed=35536489824867783254648659452939671687510903401837397577838141014455770811503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35536489824867783254648659452939671687510903401837397577838141014455770811503 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"46.xbar_unmapped_addr.42785841255430683020530318109040948632694785534233329221186002244179895824305","seed":42785841255430683020530318109040948632694785534233329221186002244179895824305,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=961064881 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.961064881' seed=42785841255430683020530318109040948632694785534233329221186002244179895824305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42785841255430683020530318109040948632694785534233329221186002244179895824305 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"46.xbar_error_and_unmapped_addr.97934039078232071289575765680457919988678050449251975981679442976288895321898","seed":97934039078232071289575765680457919988678050449251975981679442976288895321898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1944241962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1944241962' seed=97934039078232071289575765680457919988678050449251975981679442976288895321898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97934039078232071289575765680457919988678050449251975981679442976288895321898 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"46.xbar_stress_all.31586839903322912202661136233116832186379319521954011298644286033584320223157","seed":31586839903322912202661136233116832186379319521954011298644286033584320223157,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2215450549 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2215450549' seed=31586839903322912202661136233116832186379319521954011298644286033584320223157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=31586839903322912202661136233116832186379319521954011298644286033584320223157 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"46.xbar_stress_all_with_rand_reset.100457056713828879797146292177487364765574452953042674914800094803163659709619","seed":100457056713828879797146292177487364765574452953042674914800094803163659709619,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3208981683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3208981683' seed=100457056713828879797146292177487364765574452953042674914800094803163659709619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=100457056713828879797146292177487364765574452953042674914800094803163659709619 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"46.xbar_stress_all_with_error.29546898922308901427694899562118550617086459769287043722164355099206675696108","seed":29546898922308901427694899562118550617086459769287043722164355099206675696108,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480428012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1480428012' seed=29546898922308901427694899562118550617086459769287043722164355099206675696108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=29546898922308901427694899562118550617086459769287043722164355099206675696108 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"46.xbar_stress_all_with_reset_error.69694942525957161885534130292116871554610119752756330320527214535795586592684","seed":69694942525957161885534130292116871554610119752756330320527214535795586592684,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3899092908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3899092908' seed=69694942525957161885534130292116871554610119752756330320527214535795586592684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=69694942525957161885534130292116871554610119752756330320527214535795586592684 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"47.chip_sw_all_escalation_resets.88056736259778486295664072989135859608567552181474038073217544918368209465807","seed":88056736259778486295664072989135859608567552181474038073217544918368209465807,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2115629519 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2115629519' seed=88056736259778486295664072989135859608567552181474038073217544918368209465807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=88056736259778486295664072989135859608567552181474038073217544918368209465807 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.76943325813373115436634703984671266247275496683130907400722970314393489953077","seed":76943325813373115436634703984671266247275496683130907400722970314393489953077,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"47.xbar_smoke.49795282454131626187109849751311004228351102758390744955537435920851892855463","seed":49795282454131626187109849751311004228351102758390744955537435920851892855463,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4276511399 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4276511399' seed=49795282454131626187109849751311004228351102758390744955537435920851892855463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=49795282454131626187109849751311004228351102758390744955537435920851892855463 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"47.xbar_smoke_zero_delays.66759000937513705922508146306085056435794614601557840574309388349883249356387","seed":66759000937513705922508146306085056435794614601557840574309388349883249356387,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3457707619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3457707619' seed=66759000937513705922508146306085056435794614601557840574309388349883249356387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=66759000937513705922508146306085056435794614601557840574309388349883249356387 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"47.xbar_smoke_large_delays.2074548220014121652217264835808363051390438660435696647074946402713425941891","seed":2074548220014121652217264835808363051390438660435696647074946402713425941891,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850376579 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3850376579' seed=2074548220014121652217264835808363051390438660435696647074946402713425941891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=2074548220014121652217264835808363051390438660435696647074946402713425941891 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"47.xbar_smoke_slow_rsp.86967645637128732778745034322182692885815576232821719873440296887288939395974","seed":86967645637128732778745034322182692885815576232821719873440296887288939395974,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2920266630 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2920266630' seed=86967645637128732778745034322182692885815576232821719873440296887288939395974 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86967645637128732778745034322182692885815576232821719873440296887288939395974 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"47.xbar_random.44445672206682158925014761076187063325371659772921043246287366781685965253279","seed":44445672206682158925014761076187063325371659772921043246287366781685965253279,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1341123231 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1341123231' seed=44445672206682158925014761076187063325371659772921043246287366781685965253279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=44445672206682158925014761076187063325371659772921043246287366781685965253279 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"47.xbar_random_zero_delays.92422945792579185863503394859077143978077004021927232353581875770686358822994","seed":92422945792579185863503394859077143978077004021927232353581875770686358822994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3115458642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3115458642' seed=92422945792579185863503394859077143978077004021927232353581875770686358822994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92422945792579185863503394859077143978077004021927232353581875770686358822994 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"47.xbar_random_large_delays.77621104203578892193290307398784830954293987588191788344951996763980313804113","seed":77621104203578892193290307398784830954293987588191788344951996763980313804113,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271441745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3271441745' seed=77621104203578892193290307398784830954293987588191788344951996763980313804113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77621104203578892193290307398784830954293987588191788344951996763980313804113 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"47.xbar_random_slow_rsp.46820032531234847135875392227995901022127380971626424426359130324389280946264","seed":46820032531234847135875392227995901022127380971626424426359130324389280946264,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1545934936 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1545934936' seed=46820032531234847135875392227995901022127380971626424426359130324389280946264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46820032531234847135875392227995901022127380971626424426359130324389280946264 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"47.xbar_access_same_device.51612528412991388793067591010929311627922397026649071732728507152804130135811","seed":51612528412991388793067591010929311627922397026649071732728507152804130135811,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051691779 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3051691779' seed=51612528412991388793067591010929311627922397026649071732728507152804130135811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=51612528412991388793067591010929311627922397026649071732728507152804130135811 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"47.xbar_access_same_device_slow_rsp.45674849091416759955713122179581369606130260905132799513658028073967047084217","seed":45674849091416759955713122179581369606130260905132799513658028073967047084217,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2381252793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.2381252793' seed=45674849091416759955713122179581369606130260905132799513658028073967047084217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45674849091416759955713122179581369606130260905132799513658028073967047084217 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"47.xbar_same_source.30750830063482075577715901235497929804552982540413544990027727126769912041790","seed":30750830063482075577715901235497929804552982540413544990027727126769912041790,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3650408766 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3650408766' seed=30750830063482075577715901235497929804552982540413544990027727126769912041790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30750830063482075577715901235497929804552982540413544990027727126769912041790 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"47.xbar_error_random.102270599472486309652560669172692450615326701808072436160722584073238806316691","seed":102270599472486309652560669172692450615326701808072436160722584073238806316691,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3521431187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3521431187' seed=102270599472486309652560669172692450615326701808072436160722584073238806316691 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102270599472486309652560669172692450615326701808072436160722584073238806316691 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"47.xbar_unmapped_addr.113280883774060713480179382710994118774551480319079315576160345879274574636516","seed":113280883774060713480179382710994118774551480319079315576160345879274574636516,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=431023588 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.431023588' seed=113280883774060713480179382710994118774551480319079315576160345879274574636516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=113280883774060713480179382710994118774551480319079315576160345879274574636516 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"47.xbar_error_and_unmapped_addr.1422456415111744573048206783792993380658826967918708714750150831117063335730","seed":1422456415111744573048206783792993380658826967918708714750150831117063335730,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1457172274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1457172274' seed=1422456415111744573048206783792993380658826967918708714750150831117063335730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1422456415111744573048206783792993380658826967918708714750150831117063335730 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"47.xbar_stress_all.7254064435793342888828568146386219523672880836525368975265416547979994317727","seed":7254064435793342888828568146386219523672880836525368975265416547979994317727,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2908472223 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2908472223' seed=7254064435793342888828568146386219523672880836525368975265416547979994317727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=7254064435793342888828568146386219523672880836525368975265416547979994317727 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"47.xbar_stress_all_with_rand_reset.20021769131658820406052223433115687098509904596979055143261677816178664553807","seed":20021769131658820406052223433115687098509904596979055143261677816178664553807,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221844815 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.4221844815' seed=20021769131658820406052223433115687098509904596979055143261677816178664553807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=20021769131658820406052223433115687098509904596979055143261677816178664553807 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"47.xbar_stress_all_with_error.103477209480442805993364710424315532378436146239963878771712305844813938531475","seed":103477209480442805993364710424315532378436146239963878771712305844813938531475,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2469633171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2469633171' seed=103477209480442805993364710424315532378436146239963878771712305844813938531475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=103477209480442805993364710424315532378436146239963878771712305844813938531475 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"47.xbar_stress_all_with_reset_error.105689627161911188692211679860244776249248312546712011191112694688528489776538","seed":105689627161911188692211679860244776249248312546712011191112694688528489776538,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=978060698 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.978060698' seed=105689627161911188692211679860244776249248312546712011191112694688528489776538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=105689627161911188692211679860244776249248312546712011191112694688528489776538 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"48.chip_sw_all_escalation_resets.17606745965745578671066922634522868733843744072030654091056413423290342280990","seed":17606745965745578671066922634522868733843744072030654091056413423290342280990,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=158961438 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.158961438' seed=17606745965745578671066922634522868733843744072030654091056413423290342280990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=17606745965745578671066922634522868733843744072030654091056413423290342280990 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.21104676685492218074700386273051546293427786403311807182334916682550139126075","seed":21104676685492218074700386273051546293427786403311807182334916682550139126075,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"48.xbar_smoke.89209945259823438787814452130972989593214199345772415919633979773338100676058","seed":89209945259823438787814452130972989593214199345772415919633979773338100676058,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884430810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3884430810' seed=89209945259823438787814452130972989593214199345772415919633979773338100676058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89209945259823438787814452130972989593214199345772415919633979773338100676058 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"48.xbar_smoke_zero_delays.42430845073235828396002777878337836636187446674572937221464106907087566645660","seed":42430845073235828396002777878337836636187446674572937221464106907087566645660,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3233917340 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3233917340' seed=42430845073235828396002777878337836636187446674572937221464106907087566645660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=42430845073235828396002777878337836636187446674572937221464106907087566645660 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"48.xbar_smoke_large_delays.6982778846096526615236998491999647036822667450778944219074828471365292706035","seed":6982778846096526615236998491999647036822667450778944219074828471365292706035,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1352845555 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1352845555' seed=6982778846096526615236998491999647036822667450778944219074828471365292706035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=6982778846096526615236998491999647036822667450778944219074828471365292706035 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"48.xbar_smoke_slow_rsp.16222392651897514652772479029465431916556131019287338729433342185868723364999","seed":16222392651897514652772479029465431916556131019287338729433342185868723364999,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2418943111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2418943111' seed=16222392651897514652772479029465431916556131019287338729433342185868723364999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=16222392651897514652772479029465431916556131019287338729433342185868723364999 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"48.xbar_random.4835751000393045379466430521264361885721420141100824455710090217796054019101","seed":4835751000393045379466430521264361885721420141100824455710090217796054019101,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347756573 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2347756573' seed=4835751000393045379466430521264361885721420141100824455710090217796054019101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=4835751000393045379466430521264361885721420141100824455710090217796054019101 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"48.xbar_random_zero_delays.82161089556586721476869145038588117386047800898101543610979786858479896955028","seed":82161089556586721476869145038588117386047800898101543610979786858479896955028,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054097044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2054097044' seed=82161089556586721476869145038588117386047800898101543610979786858479896955028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=82161089556586721476869145038588117386047800898101543610979786858479896955028 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"48.xbar_random_large_delays.27516140610201942128003101204758019455300003477246777125369647793586051544274","seed":27516140610201942128003101204758019455300003477246777125369647793586051544274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1822749906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1822749906' seed=27516140610201942128003101204758019455300003477246777125369647793586051544274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27516140610201942128003101204758019455300003477246777125369647793586051544274 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"48.xbar_random_slow_rsp.62038335064983957110049117594869318805559683621715741095557711003821961166451","seed":62038335064983957110049117594869318805559683621715741095557711003821961166451,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430910067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2430910067' seed=62038335064983957110049117594869318805559683621715741095557711003821961166451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62038335064983957110049117594869318805559683621715741095557711003821961166451 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"48.xbar_access_same_device.109246365735196633982026330032841066580649812343712698263289116419117223685839","seed":109246365735196633982026330032841066580649812343712698263289116419117223685839,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809310927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2809310927' seed=109246365735196633982026330032841066580649812343712698263289116419117223685839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109246365735196633982026330032841066580649812343712698263289116419117223685839 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"48.xbar_access_same_device_slow_rsp.1817596284799689337184305219493092622756428991190333090303363112319372408651","seed":1817596284799689337184305219493092622756428991190333090303363112319372408651,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395204939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3395204939' seed=1817596284799689337184305219493092622756428991190333090303363112319372408651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1817596284799689337184305219493092622756428991190333090303363112319372408651 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"48.xbar_same_source.18129440918673004975849175980927521906814719769988246040996188657341083775284","seed":18129440918673004975849175980927521906814719769988246040996188657341083775284,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2275504436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2275504436' seed=18129440918673004975849175980927521906814719769988246040996188657341083775284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18129440918673004975849175980927521906814719769988246040996188657341083775284 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"48.xbar_error_random.74888958889013985530814249353931241059881481888091859110737427626204217437436","seed":74888958889013985530814249353931241059881481888091859110737427626204217437436,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2712366332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2712366332' seed=74888958889013985530814249353931241059881481888091859110737427626204217437436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=74888958889013985530814249353931241059881481888091859110737427626204217437436 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"48.xbar_unmapped_addr.93798550477858456522156356272678455628089816936829313574958061792201065598648","seed":93798550477858456522156356272678455628089816936829313574958061792201065598648,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2791280312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2791280312' seed=93798550477858456522156356272678455628089816936829313574958061792201065598648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=93798550477858456522156356272678455628089816936829313574958061792201065598648 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"48.xbar_error_and_unmapped_addr.63972991899650058774421179772842055340435088217439874689357399928061676110323","seed":63972991899650058774421179772842055340435088217439874689357399928061676110323,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1627275763 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1627275763' seed=63972991899650058774421179772842055340435088217439874689357399928061676110323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=63972991899650058774421179772842055340435088217439874689357399928061676110323 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"48.xbar_stress_all.112369548719784233400046652606788029692680109265386825193574312186639585537543","seed":112369548719784233400046652606788029692680109265386825193574312186639585537543,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307995655 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1307995655' seed=112369548719784233400046652606788029692680109265386825193574312186639585537543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=112369548719784233400046652606788029692680109265386825193574312186639585537543 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"48.xbar_stress_all_with_rand_reset.25803514963924507801277719097564868987907273687876570188519003641863024969847","seed":25803514963924507801277719097564868987907273687876570188519003641863024969847,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1126729847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.1126729847' seed=25803514963924507801277719097564868987907273687876570188519003641863024969847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25803514963924507801277719097564868987907273687876570188519003641863024969847 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"48.xbar_stress_all_with_error.30229989408428962818714570549602289403938384568595941350538312158484863149450","seed":30229989408428962818714570549602289403938384568595941350538312158484863149450,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=533489034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.533489034' seed=30229989408428962818714570549602289403938384568595941350538312158484863149450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30229989408428962818714570549602289403938384568595941350538312158484863149450 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"48.xbar_stress_all_with_reset_error.62599356109213066066747024172059852699928100677673761804944495593308279915904","seed":62599356109213066066747024172059852699928100677673761804944495593308279915904,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=626378112 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.626378112' seed=62599356109213066066747024172059852699928100677673761804944495593308279915904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=62599356109213066066747024172059852699928100677673761804944495593308279915904 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"49.chip_sw_all_escalation_resets.40030313096791325312249635988888356863324100447913570772674008391952473815675","seed":40030313096791325312249635988888356863324100447913570772674008391952473815675,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1676966523 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1676966523' seed=40030313096791325312249635988888356863324100447913570772674008391952473815675 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40030313096791325312249635988888356863324100447913570772674008391952473815675 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.48736962083845248772356879181772917468362435707384567898373146189239792462196","seed":48736962083845248772356879181772917468362435707384567898373146189239792462196,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"xbar_smoke","qual_name":"49.xbar_smoke.46856618356793952380386435237736251541020574382438347947743009589951592048702","seed":46856618356793952380386435237736251541020574382438347947743009589951592048702,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2720704574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2720704574' seed=46856618356793952380386435237736251541020574382438347947743009589951592048702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=46856618356793952380386435237736251541020574382438347947743009589951592048702 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"49.xbar_smoke_zero_delays.50325969410232224761941134545986866055068343763765601123388943729822863224260","seed":50325969410232224761941134545986866055068343763765601123388943729822863224260,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3273944516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3273944516' seed=50325969410232224761941134545986866055068343763765601123388943729822863224260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=50325969410232224761941134545986866055068343763765601123388943729822863224260 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"49.xbar_smoke_large_delays.27872029476545714064001511268524381318155717736472127553650380799594658549972","seed":27872029476545714064001511268524381318155717736472127553650380799594658549972,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1153716436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1153716436' seed=27872029476545714064001511268524381318155717736472127553650380799594658549972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=27872029476545714064001511268524381318155717736472127553650380799594658549972 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"49.xbar_smoke_slow_rsp.61857826295545752342221124685894288790237623648412303566992708963459820508282","seed":61857826295545752342221124685894288790237623648412303566992708963459820508282,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1972720762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1972720762' seed=61857826295545752342221124685894288790237623648412303566992708963459820508282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61857826295545752342221124685894288790237623648412303566992708963459820508282 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"49.xbar_random.21561058657594889351802549003368304718066468363406802366790971797454044976699","seed":21561058657594889351802549003368304718066468363406802366790971797454044976699,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740115003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2740115003' seed=21561058657594889351802549003368304718066468363406802366790971797454044976699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=21561058657594889351802549003368304718066468363406802366790971797454044976699 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"49.xbar_random_zero_delays.33141133474941385443977892137860249776567663006024414419220583690118310469558","seed":33141133474941385443977892137860249776567663006024414419220583690118310469558,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_zero_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_zero_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365740470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3365740470' seed=33141133474941385443977892137860249776567663006024414419220583690118310469558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33141133474941385443977892137860249776567663006024414419220583690118310469558 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_zero_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"49.xbar_random_large_delays.85461574380691883893497670342733364831068798215161138344334298888879717889716","seed":85461574380691883893497670342733364831068798215161138344334298888879717889716,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_large_delays/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_large_delays/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1012807348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1012807348' seed=85461574380691883893497670342733364831068798215161138344334298888879717889716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=85461574380691883893497670342733364831068798215161138344334298888879717889716 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_large_delays/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"49.xbar_random_slow_rsp.18097746570718202663132954287635306696032377484840375400836340221499360504901","seed":18097746570718202663132954287635306696032377484840375400836340221499360504901,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1105554501 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1105554501' seed=18097746570718202663132954287635306696032377484840375400836340221499360504901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=18097746570718202663132954287635306696032377484840375400836340221499360504901 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_random_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"49.xbar_access_same_device.14453802834644704645429746525368622887770653077709092735658638979247013150279","seed":14453802834644704645429746525368622887770653077709092735658638979247013150279,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836629575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1836629575' seed=14453802834644704645429746525368622887770653077709092735658638979247013150279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=14453802834644704645429746525368622887770653077709092735658638979247013150279 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"49.xbar_access_same_device_slow_rsp.65380744049077476954570060204910305262107785240848358351418141455830488695182","seed":65380744049077476954570060204910305262107785240848358351418141455830488695182,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1146601870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1146601870' seed=65380744049077476954570060204910305262107785240848358351418141455830488695182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=65380744049077476954570060204910305262107785240848358351418141455830488695182 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"49.xbar_same_source.83346814889262782613969879572525055456851857085565290049708066703119532247001","seed":83346814889262782613969879572525055456851857085565290049708066703119532247001,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_same_source/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_same_source/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_same_source/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2018592729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2018592729' seed=83346814889262782613969879572525055456851857085565290049708066703119532247001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=83346814889262782613969879572525055456851857085565290049708066703119532247001 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_same_source/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"49.xbar_error_random.3135204797492638555874216619359593244036240123103082913820176109414933709160","seed":3135204797492638555874216619359593244036240123103082913820176109414933709160,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_random/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_random/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_random/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034535272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1034535272' seed=3135204797492638555874216619359593244036240123103082913820176109414933709160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=3135204797492638555874216619359593244036240123103082913820176109414933709160 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_random/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"49.xbar_unmapped_addr.10202731606650570807505313871517089640564055743507408431723760278717996963626","seed":10202731606650570807505313871517089640564055743507408431723760278717996963626,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739640106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2739640106' seed=10202731606650570807505313871517089640564055743507408431723760278717996963626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10202731606650570807505313871517089640564055743507408431723760278717996963626 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"49.xbar_error_and_unmapped_addr.41742443397533694679841248370858805277605466380115726333385075517793774199548","seed":41742443397533694679841248370858805277605466380115726333385075517793774199548,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846221052 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2846221052' seed=41742443397533694679841248370858805277605466380115726333385075517793774199548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=41742443397533694679841248370858805277605466380115726333385075517793774199548 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"49.xbar_stress_all.33265895057367127881524759451300830544346543704555800135511022665185026453175","seed":33265895057367127881524759451300830544346543704555800135511022665185026453175,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1027681975 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1027681975' seed=33265895057367127881524759451300830544346543704555800135511022665185026453175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33265895057367127881524759451300830544346543704555800135511022665185026453175 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"49.xbar_stress_all_with_rand_reset.12129911708854555291931386930864969668891152107724432885566626342653243207442","seed":12129911708854555291931386930864969668891152107724432885566626342653243207442,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1618259730 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1618259730' seed=12129911708854555291931386930864969668891152107724432885566626342653243207442 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=12129911708854555291931386930864969668891152107724432885566626342653243207442 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"49.xbar_stress_all_with_error.34221194771115461394140375297892338263649902884674312925297841143517556850080","seed":34221194771115461394140375297892338263649902884674312925297841143517556850080,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010646432 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1010646432' seed=34221194771115461394140375297892338263649902884674312925297841143517556850080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34221194771115461394140375297892338263649902884674312925297841143517556850080 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"49.xbar_stress_all_with_reset_error.34128059005275244979541748102038058849126856312251592575475985650974291428100","seed":34128059005275244979541748102038058849126856312251592575475985650974291428100,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest run_opts='+xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=722764548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.722764548' seed=34128059005275244979541748102038058849126856312251592575475985650974291428100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=34128059005275244979541748102038058849126856312251592575475985650974291428100 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"50.chip_sw_all_escalation_resets.60977448138307201793689010197607197837516741907082197912884354278561219545056","seed":60977448138307201793689010197607197837516741907082197912884354278561219545056,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237073376 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2237073376' seed=60977448138307201793689010197607197837516741907082197912884354278561219545056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60977448138307201793689010197607197837516741907082197912884354278561219545056 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.75602500614493407692522866309590508756428350744622600745789931855864567422830","seed":75602500614493407692522866309590508756428350744622600745789931855864567422830,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"51.chip_sw_all_escalation_resets.81143966022627520072087380720066933032775335988103664300337055582498034581123","seed":81143966022627520072087380720066933032775335988103664300337055582498034581123,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181229187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.4181229187' seed=81143966022627520072087380720066933032775335988103664300337055582498034581123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=81143966022627520072087380720066933032775335988103664300337055582498034581123 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.94678511634286151800697032328042726741183813371052341626088857426373107173544","seed":94678511634286151800697032328042726741183813371052341626088857426373107173544,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"52.chip_sw_all_escalation_resets.71472239311842196379182985638083802200192510596382903356260022226435251855926","seed":71472239311842196379182985638083802200192510596382903356260022226435251855926,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3906953782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3906953782' seed=71472239311842196379182985638083802200192510596382903356260022226435251855926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71472239311842196379182985638083802200192510596382903356260022226435251855926 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.26792191890599149693156870456740717896950081002970519382704484085104040891079","seed":26792191890599149693156870456740717896950081002970519382704484085104040891079,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"53.chip_sw_all_escalation_resets.98929217980936855596446643217630515030637599654840479637762644494667959624966","seed":98929217980936855596446643217630515030637599654840479637762644494667959624966,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2451956998 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2451956998' seed=98929217980936855596446643217630515030637599654840479637762644494667959624966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=98929217980936855596446643217630515030637599654840479637762644494667959624966 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.63674941396155170441916035916720929384189321688763279098780966346516864677023","seed":63674941396155170441916035916720929384189321688763279098780966346516864677023,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"54.chip_sw_all_escalation_resets.215312903973003851840171885270126966596279895784707928503914589503486474333","seed":215312903973003851840171885270126966596279895784707928503914589503486474333,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2467870813 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2467870813' seed=215312903973003851840171885270126966596279895784707928503914589503486474333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=215312903973003851840171885270126966596279895784707928503914589503486474333 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.9804304083697973098130958997820509503973543307442451493670891851308954542306","seed":9804304083697973098130958997820509503973543307442451493670891851308954542306,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=367418) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"55.chip_sw_all_escalation_resets.54923231371119772282880753735576253418403410448921564537302512793388935759773","seed":54923231371119772282880753735576253418403410448921564537302512793388935759773,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2689025949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2689025949' seed=54923231371119772282880753735576253418403410448921564537302512793388935759773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54923231371119772282880753735576253418403410448921564537302512793388935759773 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.114949747721929253949922100630564979860811875261162990472021470209636886402919","seed":114949747721929253949922100630564979860811875261162990472021470209636886402919,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"56.chip_sw_all_escalation_resets.35779834792849262122493963788027847107075530030698786787159967916526813787569","seed":35779834792849262122493963788027847107075530030698786787159967916526813787569,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2951951793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2951951793' seed=35779834792849262122493963788027847107075530030698786787159967916526813787569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=35779834792849262122493963788027847107075530030698786787159967916526813787569 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.24197345894826463588511169608933927155207956763108564734229469222265927527660","seed":24197345894826463588511169608933927155207956763108564734229469222265927527660,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"57.chip_sw_all_escalation_resets.59248801705234135323008573085684799950752880488458201005601328594422151724994","seed":59248801705234135323008573085684799950752880488458201005601328594422151724994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2607497154 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2607497154' seed=59248801705234135323008573085684799950752880488458201005601328594422151724994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=59248801705234135323008573085684799950752880488458201005601328594422151724994 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.96153931948444936466046698068862980242563149691649286772410220448217478972982","seed":96153931948444936466046698068862980242563149691649286772410220448217478972982,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=368301) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"58.chip_sw_all_escalation_resets.102369323047252090029316487460185965975153685052117406353325570471820295580508","seed":102369323047252090029316487460185965975153685052117406353325570471820295580508,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4121602908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.4121602908' seed=102369323047252090029316487460185965975153685052117406353325570471820295580508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=102369323047252090029316487460185965975153685052117406353325570471820295580508 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.57628118139923616110269201345414977760068218027186307714723721856426206039806","seed":57628118139923616110269201345414977760068218027186307714723721856426206039806,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"59.chip_sw_all_escalation_resets.77120870101454557658395772119276021547803561375151376020485821779247496038418","seed":77120870101454557658395772119276021547803561375151376020485821779247496038418,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082684434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3082684434' seed=77120870101454557658395772119276021547803561375151376020485821779247496038418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77120870101454557658395772119276021547803561375151376020485821779247496038418 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.43903321363806351559844520593616766896987570296726988454349385784790827872178","seed":43903321363806351559844520593616766896987570296726988454349385784790827872178,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"60.chip_sw_all_escalation_resets.91374943480053774889871667197228527704078089680529752107221220502189963051378","seed":91374943480053774889871667197228527704078089680529752107221220502189963051378,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3072688498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3072688498' seed=91374943480053774889871667197228527704078089680529752107221220502189963051378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=91374943480053774889871667197228527704078089680529752107221220502189963051378 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.89278981450123072751002979988879554390672584468307041256543109587255162196552","seed":89278981450123072751002979988879554390672584468307041256543109587255162196552,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"61.chip_sw_all_escalation_resets.30394103363511803064560557505412071362627039939376894161389394720609421657861","seed":30394103363511803064560557505412071362627039939376894161389394720609421657861,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846787333 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2846787333' seed=30394103363511803064560557505412071362627039939376894161389394720609421657861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=30394103363511803064560557505412071362627039939376894161389394720609421657861 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.110826086473239738708419282334839027180384512974876838917435292048735266085304","seed":110826086473239738708419282334839027180384512974876838917435292048735266085304,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"62.chip_sw_all_escalation_resets.72016795642321222465344976371514760254708166558625416674289522201045714260732","seed":72016795642321222465344976371514760254708166558625416674289522201045714260732,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=944165628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.944165628' seed=72016795642321222465344976371514760254708166558625416674289522201045714260732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=72016795642321222465344976371514760254708166558625416674289522201045714260732 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.80714363883559049356595209175467045803658673429419714561728507502627359162943","seed":80714363883559049356595209175467045803658673429419714561728507502627359162943,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"63.chip_sw_all_escalation_resets.109328522808928471340030462691765501014417968812675586599296680559511215757783","seed":109328522808928471340030462691765501014417968812675586599296680559511215757783,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230095831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3230095831' seed=109328522808928471340030462691765501014417968812675586599296680559511215757783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=109328522808928471340030462691765501014417968812675586599296680559511215757783 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.81869924853376536194133119844926544597450600069598861878120101596183759890890","seed":81869924853376536194133119844926544597450600069598861878120101596183759890890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"64.chip_sw_all_escalation_resets.25262966078070462433845543128611625088954953280301539454409245359047062679611","seed":25262966078070462433845543128611625088954953280301539454409245359047062679611,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3692916795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3692916795' seed=25262966078070462433845543128611625088954953280301539454409245359047062679611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=25262966078070462433845543128611625088954953280301539454409245359047062679611 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.34095103260257835867750564945289362875423492653359747206856682634790714402529","seed":34095103260257835867750564945289362875423492653359747206856682634790714402529,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"65.chip_sw_all_escalation_resets.23760841929387418649503573218420146405083371747697691725038770207214356942556","seed":23760841929387418649503573218420146405083371747697691725038770207214356942556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324530396 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3324530396' seed=23760841929387418649503573218420146405083371747697691725038770207214356942556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=23760841929387418649503573218420146405083371747697691725038770207214356942556 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.67234782038167531754784291397922974294542794182471542160452708546986620102650","seed":67234782038167531754784291397922974294542794182471542160452708546986620102650,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"66.chip_sw_all_escalation_resets.52235766173339341500815458477015687696649268943596868518361843332165994309596","seed":52235766173339341500815458477015687696649268943596868518361843332165994309596,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1300522972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1300522972' seed=52235766173339341500815458477015687696649268943596868518361843332165994309596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=52235766173339341500815458477015687696649268943596868518361843332165994309596 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.100623589627882408032752428156610634518459212591935943546110308026461737483592","seed":100623589627882408032752428156610634518459212591935943546110308026461737483592,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"67.chip_sw_all_escalation_resets.53688786727075042346120845025024473579129764397835679401149900131990501952445","seed":53688786727075042346120845025024473579129764397835679401149900131990501952445,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3718876093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3718876093' seed=53688786727075042346120845025024473579129764397835679401149900131990501952445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=53688786727075042346120845025024473579129764397835679401149900131990501952445 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.111794161572384517750256511155973721318248863062288423271975009467768540509893","seed":111794161572384517750256511155973721318248863062288423271975009467768540509893,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=370878) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"68.chip_sw_all_escalation_resets.45801132434996308910052206219524620138308894129062059260372007252279561625312","seed":45801132434996308910052206219524620138308894129062059260372007252279561625312,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3454344928 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3454344928' seed=45801132434996308910052206219524620138308894129062059260372007252279561625312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=45801132434996308910052206219524620138308894129062059260372007252279561625312 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.59985944459457268376302714079287775730769153639755543874923800122877206059107","seed":59985944459457268376302714079287775730769153639755543874923800122877206059107,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"69.chip_sw_all_escalation_resets.10689230040915338043463743475175724377520877819560527439195377716496608226823","seed":10689230040915338043463743475175724377520877819560527439195377716496608226823,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4205800967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.4205800967' seed=10689230040915338043463743475175724377520877819560527439195377716496608226823 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=10689230040915338043463743475175724377520877819560527439195377716496608226823 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.17150689287382183457754147811325103401071036289564359381565917311652472606639","seed":17150689287382183457754147811325103401071036289564359381565917311652472606639,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"70.chip_sw_all_escalation_resets.89558128301003518723927958979609319099229155345417069951119420134873338195873","seed":89558128301003518723927958979609319099229155345417069951119420134873338195873,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1542434721 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1542434721' seed=89558128301003518723927958979609319099229155345417069951119420134873338195873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=89558128301003518723927958979609319099229155345417069951119420134873338195873 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.87300027133602623798668488788422798220973426929555029754227914460078990996572","seed":87300027133602623798668488788422798220973426929555029754227914460078990996572,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"71.chip_sw_all_escalation_resets.110640882133588079036220971340974689703622801311496709198349924166842602845614","seed":110640882133588079036220971340974689703622801311496709198349924166842602845614,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1453159854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1453159854' seed=110640882133588079036220971340974689703622801311496709198349924166842602845614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=110640882133588079036220971340974689703622801311496709198349924166842602845614 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942172531651379785057012448454073451485323486833088453587424513774260732312","seed":1942172531651379785057012448454073451485323486833088453587424513774260732312,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"72.chip_sw_all_escalation_resets.40406298432096413037376220377989615378721873972059782499451727350197329131555","seed":40406298432096413037376220377989615378721873972059782499451727350197329131555,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3089692707 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3089692707' seed=40406298432096413037376220377989615378721873972059782499451727350197329131555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=40406298432096413037376220377989615378721873972059782499451727350197329131555 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.108191290119018526195583047008908105832072527746501770861671134806785632158368","seed":108191290119018526195583047008908105832072527746501770861671134806785632158368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"73.chip_sw_all_escalation_resets.33700492711909088278357959652530831018763736533443062126497877804018638536576","seed":33700492711909088278357959652530831018763736533443062126497877804018638536576,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3946856320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3946856320' seed=33700492711909088278357959652530831018763736533443062126497877804018638536576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=33700492711909088278357959652530831018763736533443062126497877804018638536576 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.103184868680541201659217025656302090233649722840014299579504995611579673524187","seed":103184868680541201659217025656302090233649722840014299579504995611579673524187,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"74.chip_sw_all_escalation_resets.77144710383625888455354087911212919014242889968600761449862535998496833017484","seed":77144710383625888455354087911212919014242889968600761449862535998496833017484,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1983387276 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1983387276' seed=77144710383625888455354087911212919014242889968600761449862535998496833017484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=77144710383625888455354087911212919014242889968600761449862535998496833017484 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.112523697246735181954719266927636323921064871056441452625311537015197237044215","seed":112523697246735181954719266927636323921064871056441452625311537015197237044215,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=374017) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"75.chip_sw_all_escalation_resets.84508928953633261861415089632472559977023299853213107547240254675614456401722","seed":84508928953633261861415089632472559977023299853213107547240254675614456401722,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832963898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1832963898' seed=84508928953633261861415089632472559977023299853213107547240254675614456401722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=84508928953633261861415089632472559977023299853213107547240254675614456401722 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.12230585841602833300252345479602392910831506845966168190250988977163508588169","seed":12230585841602833300252345479602392910831506845966168190250988977163508588169,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"76.chip_sw_all_escalation_resets.55842125316196443717745653095277551468091145057196880311891998976083509133190","seed":55842125316196443717745653095277551468091145057196880311891998976083509133190,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3793239942 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.3793239942' seed=55842125316196443717745653095277551468091145057196880311891998976083509133190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=55842125316196443717745653095277551468091145057196880311891998976083509133190 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.36447839859678838832309379648685419877607927626474040348944293609994253676968","seed":36447839859678838832309379648685419877607927626474040348944293609994253676968,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=373762) is running. Waiting for it to complete on the server (server_pid=208841)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"77.chip_sw_all_escalation_resets.9747542005827752430460231683806125088251100102654308981770812240378631878661","seed":9747542005827752430460231683806125088251100102654308981770812240378631878661,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726098949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2726098949' seed=9747542005827752430460231683806125088251100102654308981770812240378631878661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9747542005827752430460231683806125088251100102654308981770812240378631878661 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.46996364183654517052441556890736244797268086915591413868635873813154508809921","seed":46996364183654517052441556890736244797268086915591413868635873813154508809921,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"78.chip_sw_all_escalation_resets.70643149026865576483191742511117571882754612202389038322946051668251982322848","seed":70643149026865576483191742511117571882754612202389038322946051668251982322848,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3764018336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3764018336' seed=70643149026865576483191742511117571882754612202389038322946051668251982322848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70643149026865576483191742511117571882754612202389038322946051668251982322848 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.94854512244420593788144264258600715508417215519492180928590124845980105883690","seed":94854512244420593788144264258600715508417215519492180928590124845980105883690,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"79.chip_sw_all_escalation_resets.97190972516044366935007445428209676496683407636650672738940998344206109604003","seed":97190972516044366935007445428209676496683407636650672738940998344206109604003,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892041379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.892041379' seed=97190972516044366935007445428209676496683407636650672738940998344206109604003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=97190972516044366935007445428209676496683407636650672738940998344206109604003 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.66188524535980173722745986545218348732474129702148843580608553829441789659422","seed":66188524535980173722745986545218348732474129702148843580608553829441789659422,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"80.chip_sw_all_escalation_resets.1484458716381519894958105460171947781323036294585243732298982383721606506517","seed":1484458716381519894958105460171947781323036294585243732298982383721606506517,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509831189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.509831189' seed=1484458716381519894958105460171947781323036294585243732298982383721606506517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=1484458716381519894958105460171947781323036294585243732298982383721606506517 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1589946647250976528600292113496958970438276738364366353573303562254391471845","seed":1589946647250976528600292113496958970438276738364366353573303562254391471845,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"81.chip_sw_all_escalation_resets.15250592766445298670894610368793021079830178254329240069699703080834345436109","seed":15250592766445298670894610368793021079830178254329240069699703080834345436109,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3669459917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3669459917' seed=15250592766445298670894610368793021079830178254329240069699703080834345436109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=15250592766445298670894610368793021079830178254329240069699703080834345436109 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.12673190768029803127928075406434332581178892309337289942013014599427357039146","seed":12673190768029803127928075406434332581178892309337289942013014599427357039146,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"82.chip_sw_all_escalation_resets.26196793567898431026333317074528443909553257209144077718762209971779339015676","seed":26196793567898431026333317074528443909553257209144077718762209971779339015676,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506006524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1506006524' seed=26196793567898431026333317074528443909553257209144077718762209971779339015676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=26196793567898431026333317074528443909553257209144077718762209971779339015676 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.105829407339733450485723313728238328320110504224353964004992785793763763686572","seed":105829407339733450485723313728238328320110504224353964004992785793763763686572,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"83.chip_sw_all_escalation_resets.61118787120189084463297123169104566787739707050475080052926505241025455373829","seed":61118787120189084463297123169104566787739707050475080052926505241025455373829,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611368453 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.611368453' seed=61118787120189084463297123169104566787739707050475080052926505241025455373829 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61118787120189084463297123169104566787739707050475080052926505241025455373829 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.9127615537854923226725176143649178967008084414414474341104813741242792988807","seed":9127615537854923226725176143649178967008084414414474341104813741242792988807,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"84.chip_sw_all_escalation_resets.8077296948851739450357076464187534174050873148541345131611735790329105603975","seed":8077296948851739450357076464187534174050873148541345131611735790329105603975,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618154375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2618154375' seed=8077296948851739450357076464187534174050873148541345131611735790329105603975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=8077296948851739450357076464187534174050873148541345131611735790329105603975 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.154705556460764700630438531845827270171617087993804038581254219379863876218","seed":154705556460764700630438531845827270171617087993804038581254219379863876218,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"85.chip_sw_all_escalation_resets.9468757605096210025957368077137933269611860140603729610416834237740843449503","seed":9468757605096210025957368077137933269611860140603729610416834237740843449503,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2515713183 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2515713183' seed=9468757605096210025957368077137933269611860140603729610416834237740843449503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=9468757605096210025957368077137933269611860140603729610416834237740843449503 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.51478620968814936930091784733490729891538568938183810854522523163720475482029","seed":51478620968814936930091784733490729891538568938183810854522523163720475482029,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"86.chip_sw_all_escalation_resets.54981578985670089489955964041801697254195534825719374975401605051591879573535","seed":54981578985670089489955964041801697254195534825719374975401605051591879573535,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3116908575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3116908575' seed=54981578985670089489955964041801697254195534825719374975401605051591879573535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=54981578985670089489955964041801697254195534825719374975401605051591879573535 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.40642423908086105163157629853447788761669500450862524284990526191962626386183","seed":40642423908086105163157629853447788761669500450862524284990526191962626386183,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"87.chip_sw_all_escalation_resets.99437063885563174505972992405564501339032467465557472198094763111052856999931","seed":99437063885563174505972992405564501339032467465557472198094763111052856999931,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=607076347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.607076347' seed=99437063885563174505972992405564501339032467465557472198094763111052856999931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=99437063885563174505972992405564501339032467465557472198094763111052856999931 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.15020043394798723211331254759002141156450498659899354629846591951420896164968","seed":15020043394798723211331254759002141156450498659899354629846591951420896164968,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"88.chip_sw_all_escalation_resets.90399947652304646341118257152608978634348388137681597570983680319895650163036","seed":90399947652304646341118257152608978634348388137681597570983680319895650163036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2149046620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2149046620' seed=90399947652304646341118257152608978634348388137681597570983680319895650163036 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=90399947652304646341118257152608978634348388137681597570983680319895650163036 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.75978357037298929170190151590681487084720405127276137821023090338043056805907","seed":75978357037298929170190151590681487084720405127276137821023090338043056805907,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"89.chip_sw_all_escalation_resets.61099030468755354935034553962029632991023477521708123046687492390581279349878","seed":61099030468755354935034553962029632991023477521708123046687492390581279349878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1761827958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1761827958' seed=61099030468755354935034553962029632991023477521708123046687492390581279349878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61099030468755354935034553962029632991023477521708123046687492390581279349878 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.81859117346320453815008791123521503132045937390285646680246118164009188478522","seed":81859117346320453815008791123521503132045937390285646680246118164009188478522,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"90.chip_sw_all_escalation_resets.73812316089315488149462288727467552610199150693415948371787494930214638943359","seed":73812316089315488149462288727467552610199150693415948371787494930214638943359,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=913669247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.913669247' seed=73812316089315488149462288727467552610199150693415948371787494930214638943359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=73812316089315488149462288727467552610199150693415948371787494930214638943359 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"91.chip_sw_all_escalation_resets.92544825806631711780063021047082515586601991916782949319663180378809357352698","seed":92544825806631711780063021047082515586601991916782949319663180378809357352698,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3139223290 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3139223290' seed=92544825806631711780063021047082515586601991916782949319663180378809357352698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=92544825806631711780063021047082515586601991916782949319663180378809357352698 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"92.chip_sw_all_escalation_resets.61429192036013516497343763541281440016609772028732344382349636943634847963815","seed":61429192036013516497343763541281440016609772028732344382349636943634847963815,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2535660199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2535660199' seed=61429192036013516497343763541281440016609772028732344382349636943634847963815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=61429192036013516497343763541281440016609772028732344382349636943634847963815 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"93.chip_sw_all_escalation_resets.86372248402175618224828708161933064949058739533198214515205025430913069452645","seed":86372248402175618224828708161933064949058739533198214515205025430913069452645,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=147164517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.147164517' seed=86372248402175618224828708161933064949058739533198214515205025430913069452645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=86372248402175618224828708161933064949058739533198214515205025430913069452645 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"94.chip_sw_all_escalation_resets.106268571545376736747846413856928456794003526786826915575069963355394540861682","seed":106268571545376736747846413856928456794003526786826915575069963355394540861682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046771954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1046771954' seed=106268571545376736747846413856928456794003526786826915575069963355394540861682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=106268571545376736747846413856928456794003526786826915575069963355394540861682 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"95.chip_sw_all_escalation_resets.32842004598005090256612817624344621177687141507588799825126143868083116385157","seed":32842004598005090256612817624344621177687141507588799825126143868083116385157,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1484989317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1484989317' seed=32842004598005090256612817624344621177687141507588799825126143868083116385157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=32842004598005090256612817624344621177687141507588799825126143868083116385157 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"96.chip_sw_all_escalation_resets.71972035550419398862488330274219190417020586717428250804870386951726185463831","seed":71972035550419398862488330274219190417020586717428250804870386951726185463831,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738845207 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.3738845207' seed=71972035550419398862488330274219190417020586717428250804870386951726185463831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=71972035550419398862488330274219190417020586717428250804870386951726185463831 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"97.chip_sw_all_escalation_resets.70718029857279299053675405786773778714527178530709599916860465577718567778607","seed":70718029857279299053675405786773778714527178530709599916860465577718567778607,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2315368751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2315368751' seed=70718029857279299053675405786773778714527178530709599916860465577718567778607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=70718029857279299053675405786773778714527178530709599916860465577718567778607 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"98.chip_sw_all_escalation_resets.22092503835883929702445228152387217376092219080832110807092283842175503686874","seed":22092503835883929702445228152387217376092219080832110807092283842175503686874,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2340150490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2340150490' seed=22092503835883929702445228152387217376092219080832110807092283842175503686874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=22092503835883929702445228152387217376092219080832110807092283842175503686874 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"99.chip_sw_all_escalation_resets.60076733559495772140977938287472782326557263931479147895566753295972246921714","seed":60076733559495772140977938287472782326557263931479147895566753295972246921714,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest/run.log","log_context":["      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson && /nightly/current_run/opentitan/util/design/gen-otp-img.py \\\n","      --img-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \\\n","      --add-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \\\n","      --out /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \\\n","      --quiet --mmap-def /nightly/current_run/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson --top-secret-cfg /nightly/current_run/opentitan/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3355091442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3355091442' seed=60076733559495772140977938287472782326557263931479147895566753295972246921714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"'//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0'\"'\"' --sw-build-opts='\"'\"'--//hw/top=darjeeling --//hw/top=darjeeling'\"'\"' --sw-build-device=sim_dv --seed=60076733559495772140977938287472782326557263931479147895566753295972246921714 --run-dir=/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest' sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Error-[FCULIBNF] Ucapi library not found":[{"name":"chip_sw_otbn_ecdsa_op_irq","qual_name":"0.chip_sw_otbn_ecdsa_op_irq.82817323779495065205738468569757374692831558932240703416628422857126002516293","seed":82817323779495065205738468569757374692831558932240703416628422857126002516293,"line":412,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq/latest/run.log","log_context":["  Unable to locate ucapi library at \n","  /nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq","qual_name":"1.chip_sw_otbn_ecdsa_op_irq.81247485764731602612066173949806971372310908418066122379297024012995062287563","seed":81247485764731602612066173949806971372310908418066122379297024012995062287563,"line":412,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq/latest/run.log","log_context":["  Unable to locate ucapi library at \n","  /nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq","qual_name":"2.chip_sw_otbn_ecdsa_op_irq.61151706096742362578285867924422150804377232140738479005455824773103709121759","seed":61151706096742362578285867924422150804377232140738479005455824773103709121759,"line":412,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq/latest/run.log","log_context":["  Unable to locate ucapi library at \n","  /nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency","qual_name":"2.chip_sw_csrng_edn_concurrency.93973093928900187151796174264842573878979297670020578873982038627737017524226","seed":93973093928900187151796174264842573878979297670020578873982038627737017524226,"line":435,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency/latest/run.log","log_context":["  Unable to locate ucapi library at \n","  /nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.\n","\n","\n"]}],"UVM_FATAL @ * us: (dv_utils_pkg.sv:253) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\"":[{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en.69791956883010885870365309948058969601381214183195089657434452789024110628202","seed":69791956883010885870365309948058969601381214183195089657434452789024110628202,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.96534478651297695911856633971642059680667540428599890957761606868505122617158","seed":96534478651297695911856633971642059680667540428599890957761606868505122617158,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"0.chip_sw_csrng_edn_concurrency_reduced_freq.50252029581348650482443858240969768638990178643587059375555212918884648888636","seed":50252029581348650482443858240969768638990178643587059375555212918884648888636,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"1.chip_sw_otbn_ecdsa_op_irq_jitter_en.113836185337446966290051129107191534587436822193366155536121580913637104977206","seed":113836185337446966290051129107191534587436822193366155536121580913637104977206,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.89424573504809050158706619108554773134671943719526727737695944981228565510849","seed":89424573504809050158706619108554773134671943719526727737695944981228565510849,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"1.chip_sw_csrng_edn_concurrency_reduced_freq.16436835695463264002987357079650355418723026624709486902606935296903389853184","seed":16436835695463264002987357079650355418723026624709486902606935296903389853184,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"2.chip_sw_otbn_ecdsa_op_irq_jitter_en.39909425932676656554584786433682230815789654056605116895605686297363000394633","seed":39909425932676656554584786433682230815789654056605116895605686297363000394633,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.23457738271525267858422367189048115776569788104449245896406883101691150569902","seed":23457738271525267858422367189048115776569788104449245896406883101691150569902,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"2.chip_sw_csrng_edn_concurrency_reduced_freq.80362012472172097034742182032302252578700754644177369258752068665786211647104","seed":80362012472172097034742182032302252578700754644177369258752068665786211647104,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned a non-zero exit code: *":[{"name":"chip","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=urg cov_merge_opts='-lca -full64 -noreport +urg+lic+wait -merge_across_libs -show tests -flex_merge union -dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -dir /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/xbar_build_mode.vdb -dbname /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cov_merge/merged.vdb'\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126\n"]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"chip","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":2,"total":1730,"percent":0.11560693641618497}