{"block":{"name":"dma","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/dma/data/dma_testplan.html","stages":{"V1":{"testpoints":{"dma_memory_smoke":{"tests":{"dma_memory_smoke":{"max_time":1.3537583826109767,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0},"dma_handshake_smoke":{"tests":{"dma_handshake_smoke":{"max_time":0.8824724769219756,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0},"dma_generic_smoke":{"tests":{"dma_generic_smoke":{"max_time":0.9174423012882471,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"csr_hw_reset":{"tests":{"dma_csr_hw_reset":{"max_time":0.851739065721631,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_rw":{"tests":{"dma_csr_rw":{"max_time":0.884650225751102,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"csr_bit_bash":{"tests":{"dma_csr_bit_bash":{"max_time":0.8132823137566447,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"dma_csr_aliasing":{"max_time":1.3393500382080674,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_mem_rw_with_rand_reset":{"tests":{"dma_csr_mem_rw_with_rand_reset":{"max_time":0.8733201380819082,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"dma_csr_rw":{"max_time":0.884650225751102,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"dma_csr_aliasing":{"max_time":1.3393500382080674,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":6,"percent":0.0}},"passed":0,"total":113,"percent":0.0},"V2":{"testpoints":{"dma_memory_region_lock":{"tests":{"dma_memory_region_lock":{"max_time":0.8628396401181817,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"dma_memory_tl_error":{"tests":{"dma_memory_stress":{"max_time":0.8479785714298487,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"dma_handshake_tl_error":{"tests":{"dma_handshake_stress":{"max_time":0.8793628001585603,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"dma_handshake_stress":{"tests":{"dma_handshake_stress":{"max_time":0.8793628001585603,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"dma_memory_stress":{"tests":{"dma_memory_stress":{"max_time":0.8479785714298487,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"dma_generic_stress":{"tests":{"dma_generic_stress":{"max_time":0.872246035374701,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"dma_handshake_mem_buffer_overflow":{"tests":{"dma_handshake_stress":{"max_time":0.8793628001585603,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"dma_abort":{"tests":{"dma_abort":{"max_time":0.88005939591676,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"dma_stress_all":{"tests":{"dma_stress_all":{"max_time":238.0,"sim_time":36042.664490999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"alert_test":{"tests":{"dma_alert_test":{"max_time":0.8924161978065968,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"intr_test":{"tests":{"dma_intr_test":{"max_time":0.8990166839212179,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"tl_d_oob_addr_access":{"tests":{"dma_tl_errors":{"max_time":1.3951177718117833,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0},"tl_d_illegal_access":{"tests":{"dma_tl_errors":{"max_time":1.3951177718117833,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0},"tl_d_outstanding_access":{"tests":{"dma_csr_hw_reset":{"max_time":0.851739065721631,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"dma_csr_rw":{"max_time":0.884650225751102,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"dma_csr_aliasing":{"max_time":1.3393500382080674,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"dma_same_csr_outstanding":{"max_time":0.8767134556546807,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":12,"percent":0.0},"tl_d_partial_access":{"tests":{"dma_csr_hw_reset":{"max_time":0.851739065721631,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"dma_csr_rw":{"max_time":0.884650225751102,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"dma_csr_aliasing":{"max_time":1.3393500382080674,"sim_time":0.0,"passed":0,"total":1,"percent"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pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"dma_generic_smoke","qual_name":"0.dma_generic_smoke.108722622339921831452894906663753348827452542459789564755021667504504459561276","seed":108722622339921831452894906663753348827452542459789564755021667504504459561276,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=861735228 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq 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/nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_short_transfer.3824851128 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_short_transfer.3824851128 -covoverwrite' seed=63121443442675760887608252230055673939261126342858532082190974077961328302264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63121443442675760887608252230055673939261126342858532082190974077961328302264 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_longer_transfer","qual_name":"0.dma_longer_transfer.11002169316889458216661688231721862107393530615180524043701492252647894720260","seed":11002169316889458216661688231721862107393530615180524043701492252647894720260,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_longer_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_longer_transfer/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=121020164 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_longer_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_longer_transfer.121020164 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_longer_transfer.121020164 -covoverwrite' seed=11002169316889458216661688231721862107393530615180524043701492252647894720260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11002169316889458216661688231721862107393530615180524043701492252647894720260 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_longer_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_longer_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_mem_enabled","qual_name":"0.dma_mem_enabled.6329001863517069244659060106950035341502561903732426382948033518863180199177","seed":6329001863517069244659060106950035341502561903732426382948033518863180199177,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_mem_enabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_mem_enabled/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2553378057 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_mem_enabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_mem_enabled.2553378057 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_mem_enabled.2553378057 -covoverwrite' seed=6329001863517069244659060106950035341502561903732426382948033518863180199177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6329001863517069244659060106950035341502561903732426382948033518863180199177 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_mem_enabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_mem_enabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"0.dma_config_lock.80061132672463030318284896486272070129443170713800920130363102900847216390031","seed":80061132672463030318284896486272070129443170713800920130363102900847216390031,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3178721167 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_config_lock.3178721167 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_config_lock.3178721167 -covoverwrite' seed=80061132672463030318284896486272070129443170713800920130363102900847216390031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80061132672463030318284896486272070129443170713800920130363102900847216390031 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_stress","qual_name":"0.dma_generic_stress.57939897383739112826059679927192101892771650841954183728121976942254714976553","seed":57939897383739112826059679927192101892771650841954183728121976942254714976553,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_generic_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_generic_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=379517225 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_generic_stress.379517225 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_generic_stress.379517225 -covoverwrite' seed=57939897383739112826059679927192101892771650841954183728121976942254714976553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57939897383739112826059679927192101892771650841954183728121976942254714976553 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_generic_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_stress","qual_name":"0.dma_memory_stress.61543859709432832582131182368833677987069241812837808027386582902110508438903","seed":61543859709432832582131182368833677987069241812837808027386582902110508438903,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_memory_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_memory_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=592860535 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_memory_stress.592860535 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_memory_stress.592860535 -covoverwrite' seed=61543859709432832582131182368833677987069241812837808027386582902110508438903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61543859709432832582131182368833677987069241812837808027386582902110508438903 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_memory_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_stress","qual_name":"0.dma_handshake_stress.4685750786157828681094934585942491105920850088500812483694583403041148113918","seed":4685750786157828681094934585942491105920850088500812483694583403041148113918,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_handshake_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_handshake_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=830215166 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_handshake_stress.830215166 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_handshake_stress.830215166 -covoverwrite' seed=4685750786157828681094934585942491105920850088500812483694583403041148113918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4685750786157828681094934585942491105920850088500812483694583403041148113918 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_handshake_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"0.dma_tl_errors.25662779896623177764636486117466126828821890610687729801166454715853672975807","seed":25662779896623177764636486117466126828821890610687729801166454715853672975807,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2455932351 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_tl_errors.2455932351 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_tl_errors.2455932351 -covoverwrite' seed=25662779896623177764636486117466126828821890610687729801166454715853672975807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25662779896623177764636486117466126828821890610687729801166454715853672975807 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"0.dma_tl_intg_err.38855145245476759160770303417994508111689533040737974836920209747292208524370","seed":38855145245476759160770303417994508111689533040737974836920209747292208524370,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=345009234 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_tl_intg_err.345009234 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_tl_intg_err.345009234 -covoverwrite' seed=38855145245476759160770303417994508111689533040737974836920209747292208524370 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38855145245476759160770303417994508111689533040737974836920209747292208524370 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_stress_all_with_rand_reset","qual_name":"0.dma_stress_all_with_rand_reset.64541705566745032912818927793005933698589824761544535944435351168750816315749","seed":64541705566745032912818927793005933698589824761544535944435351168750816315749,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=dma_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1552664933 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_stress_all_with_rand_reset.1552664933 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_stress_all_with_rand_reset.1552664933 -covoverwrite' seed=64541705566745032912818927793005933698589824761544535944435351168750816315749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64541705566745032912818927793005933698589824761544535944435351168750816315749 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_sec_cm","qual_name":"0.dma_sec_cm.106150593121553388504870775019210106064313312148426767156020111185630496148806","seed":106150593121553388504870775019210106064313312148426767156020111185630496148806,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=371838278 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_sec_cm.371838278 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_sec_cm.371838278 -covoverwrite' seed=106150593121553388504870775019210106064313312148426767156020111185630496148806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106150593121553388504870775019210106064313312148426767156020111185630496148806 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"0.dma_intr_test.65470705852830041356044828723734602921801889993532049976953359133090344304918","seed":65470705852830041356044828723734602921801889993532049976953359133090344304918,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2874376470 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_intr_test.2874376470 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_intr_test.2874376470 -covoverwrite' seed=65470705852830041356044828723734602921801889993532049976953359133090344304918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65470705852830041356044828723734602921801889993532049976953359133090344304918 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_hw_reset","qual_name":"0.dma_csr_hw_reset.54905597997232460815558755805410978844603883893681668256287302432813035507345","seed":54905597997232460815558755805410978844603883893681668256287302432813035507345,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1384337041 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_csr_hw_reset.1384337041 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_csr_hw_reset.1384337041 -covoverwrite' seed=54905597997232460815558755805410978844603883893681668256287302432813035507345 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54905597997232460815558755805410978844603883893681668256287302432813035507345 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_rw","qual_name":"0.dma_csr_rw.87498188500117615402121957324914184166833986658998167020646779756654556891831","seed":87498188500117615402121957324914184166833986658998167020646779756654556891831,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2280934071 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_csr_rw.2280934071 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_csr_rw.2280934071 -covoverwrite' seed=87498188500117615402121957324914184166833986658998167020646779756654556891831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87498188500117615402121957324914184166833986658998167020646779756654556891831 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_bit_bash","qual_name":"0.dma_csr_bit_bash.99873112587759040212850662474594701059300591940421349836420333203953017625567","seed":99873112587759040212850662474594701059300591940421349836420333203953017625567,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2163153887 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_csr_bit_bash.2163153887 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_csr_bit_bash.2163153887 -covoverwrite' seed=99873112587759040212850662474594701059300591940421349836420333203953017625567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99873112587759040212850662474594701059300591940421349836420333203953017625567 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_aliasing","qual_name":"0.dma_csr_aliasing.66027850014524142986171099005510877434897876142201240563876534328560787289348","seed":66027850014524142986171099005510877434897876142201240563876534328560787289348,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3072488708 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_csr_aliasing.3072488708 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_csr_aliasing.3072488708 -covoverwrite' seed=66027850014524142986171099005510877434897876142201240563876534328560787289348 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66027850014524142986171099005510877434897876142201240563876534328560787289348 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_same_csr_outstanding","qual_name":"0.dma_same_csr_outstanding.110662329637588657060070469993427732144018682606452593706621682404251841855838","seed":110662329637588657060070469993427732144018682606452593706621682404251841855838,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1142161758 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_same_csr_outstanding.1142161758 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_same_csr_outstanding.1142161758 -covoverwrite' seed=110662329637588657060070469993427732144018682606452593706621682404251841855838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110662329637588657060070469993427732144018682606452593706621682404251841855838 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_mem_rw_with_rand_reset","qual_name":"0.dma_csr_mem_rw_with_rand_reset.95445764053475666897068302653915130918140826864467316758243122474214511993713","seed":95445764053475666897068302653915130918140826864467316758243122474214511993713,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=936239985 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/0.dma_csr_mem_rw_with_rand_reset.936239985 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.dma_csr_mem_rw_with_rand_reset.936239985 -covoverwrite' seed=95445764053475666897068302653915130918140826864467316758243122474214511993713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95445764053475666897068302653915130918140826864467316758243122474214511993713 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"0.dma_alert_test.115395313263863758518860815287991733694870839531803095344183761734059265377246","seed":115395313263863758518860815287991733694870839531803095344183761734059265377246,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1448100830 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/0.dma_alert_test.1448100830 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 0.dma_alert_test.1448100830 -covoverwrite' seed=115395313263863758518860815287991733694870839531803095344183761734059265377246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115395313263863758518860815287991733694870839531803095344183761734059265377246 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"1.dma_generic_smoke.38550527890037463733574741184282749213193836516182287806981628762496373966873","seed":38550527890037463733574741184282749213193836516182287806981628762496373966873,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2305378329 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_generic_smoke.2305378329 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_generic_smoke.2305378329 -covoverwrite' seed=38550527890037463733574741184282749213193836516182287806981628762496373966873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38550527890037463733574741184282749213193836516182287806981628762496373966873 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"1.dma_memory_smoke.104008092433102594980865318706903464182584243846480861760011725821187251202076","seed":104008092433102594980865318706903464182584243846480861760011725821187251202076,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1306224668 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_memory_smoke.1306224668 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_memory_smoke.1306224668 -covoverwrite' seed=104008092433102594980865318706903464182584243846480861760011725821187251202076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104008092433102594980865318706903464182584243846480861760011725821187251202076 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"1.dma_handshake_smoke.59441236877588970545909088840759137250859411550189697218123479293447423287297","seed":59441236877588970545909088840759137250859411550189697218123479293447423287297,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4280442881 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_handshake_smoke.4280442881 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_handshake_smoke.4280442881 -covoverwrite' seed=59441236877588970545909088840759137250859411550189697218123479293447423287297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59441236877588970545909088840759137250859411550189697218123479293447423287297 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_region_lock","qual_name":"1.dma_memory_region_lock.4107671037774297800600825361515381493451956320915879752744725039537398714834","seed":4107671037774297800600825361515381493451956320915879752744725039537398714834,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_region_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_region_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2724434386 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_region_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_memory_region_lock.2724434386 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_memory_region_lock.2724434386 -covoverwrite' seed=4107671037774297800600825361515381493451956320915879752744725039537398714834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4107671037774297800600825361515381493451956320915879752744725039537398714834 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_region_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_region_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_abort","qual_name":"1.dma_abort.106647942017441797039460676492895418235039617514284638525823444534121505629589","seed":106647942017441797039460676492895418235039617514284638525823444534121505629589,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_abort/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_abort/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1904092565 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_abort_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_abort.1904092565 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_abort.1904092565 -covoverwrite' seed=106647942017441797039460676492895418235039617514284638525823444534121505629589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106647942017441797039460676492895418235039617514284638525823444534121505629589 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_abort/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_abort_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"1.dma_short_transfer.103252903334533167516524122518494015307465861022078856563915576624505035472698","seed":103252903334533167516524122518494015307465861022078856563915576624505035472698,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=330874682 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_short_transfer.330874682 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_short_transfer.330874682 -covoverwrite' seed=103252903334533167516524122518494015307465861022078856563915576624505035472698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103252903334533167516524122518494015307465861022078856563915576624505035472698 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_longer_transfer","qual_name":"1.dma_longer_transfer.102260017824603742442022163030945240021066913509175603718930161997781948593852","seed":102260017824603742442022163030945240021066913509175603718930161997781948593852,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_longer_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_longer_transfer/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1752856252 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_longer_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_longer_transfer.1752856252 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_longer_transfer.1752856252 -covoverwrite' seed=102260017824603742442022163030945240021066913509175603718930161997781948593852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102260017824603742442022163030945240021066913509175603718930161997781948593852 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_longer_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_longer_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_mem_enabled","qual_name":"1.dma_mem_enabled.8432605446738654293404398486742994473408906543880778510376565051135919011707","seed":8432605446738654293404398486742994473408906543880778510376565051135919011707,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_mem_enabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_mem_enabled/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2483173243 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_mem_enabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_mem_enabled.2483173243 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_mem_enabled.2483173243 -covoverwrite' seed=8432605446738654293404398486742994473408906543880778510376565051135919011707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8432605446738654293404398486742994473408906543880778510376565051135919011707 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_mem_enabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_mem_enabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"1.dma_config_lock.79758692897182378493875971584025013185502088517391822470053194007854045076098","seed":79758692897182378493875971584025013185502088517391822470053194007854045076098,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2003966594 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_config_lock.2003966594 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_config_lock.2003966594 -covoverwrite' seed=79758692897182378493875971584025013185502088517391822470053194007854045076098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79758692897182378493875971584025013185502088517391822470053194007854045076098 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_stress","qual_name":"1.dma_generic_stress.51515086530166975856159720793392985632488677909210175867408945607778706511514","seed":51515086530166975856159720793392985632488677909210175867408945607778706511514,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_generic_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_generic_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=551933594 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_generic_stress.551933594 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_generic_stress.551933594 -covoverwrite' seed=51515086530166975856159720793392985632488677909210175867408945607778706511514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51515086530166975856159720793392985632488677909210175867408945607778706511514 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_generic_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_stress","qual_name":"1.dma_memory_stress.113341366114682454007163216952960656821957220710783473014534313903816410610911","seed":113341366114682454007163216952960656821957220710783473014534313903816410610911,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2267233503 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_memory_stress.2267233503 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_memory_stress.2267233503 -covoverwrite' seed=113341366114682454007163216952960656821957220710783473014534313903816410610911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113341366114682454007163216952960656821957220710783473014534313903816410610911 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_memory_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_stress","qual_name":"1.dma_handshake_stress.112069521849704074581211082216873838786260498539793374359359057515649325426797","seed":112069521849704074581211082216873838786260498539793374359359057515649325426797,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_handshake_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_handshake_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=883779693 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_handshake_stress.883779693 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_handshake_stress.883779693 -covoverwrite' seed=112069521849704074581211082216873838786260498539793374359359057515649325426797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112069521849704074581211082216873838786260498539793374359359057515649325426797 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_handshake_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"1.dma_tl_errors.2730971744205895745220392144684515565888847241677249768455444990134353624433","seed":2730971744205895745220392144684515565888847241677249768455444990134353624433,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=711949681 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/1.dma_tl_errors.711949681 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.dma_tl_errors.711949681 -covoverwrite' seed=2730971744205895745220392144684515565888847241677249768455444990134353624433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2730971744205895745220392144684515565888847241677249768455444990134353624433 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"1.dma_tl_intg_err.14079111375192663121335688233392767259736845415533545476656106218897779025301","seed":14079111375192663121335688233392767259736845415533545476656106218897779025301,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3243074965 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/1.dma_tl_intg_err.3243074965 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.dma_tl_intg_err.3243074965 -covoverwrite' seed=14079111375192663121335688233392767259736845415533545476656106218897779025301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14079111375192663121335688233392767259736845415533545476656106218897779025301 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_sec_cm","qual_name":"1.dma_sec_cm.105053506782688190761857191793017719029348023488492625108233714540960101755201","seed":105053506782688190761857191793017719029348023488492625108233714540960101755201,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3738757441 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_sec_cm.3738757441 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_sec_cm.3738757441 -covoverwrite' seed=105053506782688190761857191793017719029348023488492625108233714540960101755201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105053506782688190761857191793017719029348023488492625108233714540960101755201 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"1.dma_intr_test.83232696765822269492350297755350055707257109105954046015621816591863849953950","seed":83232696765822269492350297755350055707257109105954046015621816591863849953950,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=439626398 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/1.dma_intr_test.439626398 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.dma_intr_test.439626398 -covoverwrite' seed=83232696765822269492350297755350055707257109105954046015621816591863849953950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83232696765822269492350297755350055707257109105954046015621816591863849953950 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_rw","qual_name":"1.dma_csr_rw.58698736075160488743767253999904577248603008725911442874549081435095684441121","seed":58698736075160488743767253999904577248603008725911442874549081435095684441121,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2553898017 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/1.dma_csr_rw.2553898017 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.dma_csr_rw.2553898017 -covoverwrite' seed=58698736075160488743767253999904577248603008725911442874549081435095684441121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58698736075160488743767253999904577248603008725911442874549081435095684441121 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_same_csr_outstanding","qual_name":"1.dma_same_csr_outstanding.110512325076714569782758236379793392921492252493972489284173351837947371768159","seed":110512325076714569782758236379793392921492252493972489284173351837947371768159,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2158807391 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/1.dma_same_csr_outstanding.2158807391 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.dma_same_csr_outstanding.2158807391 -covoverwrite' seed=110512325076714569782758236379793392921492252493972489284173351837947371768159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110512325076714569782758236379793392921492252493972489284173351837947371768159 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_mem_rw_with_rand_reset","qual_name":"1.dma_csr_mem_rw_with_rand_reset.94147449769720491002893357878243550190059055416256771934637033305069147675457","seed":94147449769720491002893357878243550190059055416256771934637033305069147675457,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1381522241 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/1.dma_csr_mem_rw_with_rand_reset.1381522241 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.dma_csr_mem_rw_with_rand_reset.1381522241 -covoverwrite' seed=94147449769720491002893357878243550190059055416256771934637033305069147675457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94147449769720491002893357878243550190059055416256771934637033305069147675457 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"1.dma_alert_test.24757824120187919807900776632775341882491261426670308003772185046511517995047","seed":24757824120187919807900776632775341882491261426670308003772185046511517995047,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=728010791 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/1.dma_alert_test.728010791 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 1.dma_alert_test.728010791 -covoverwrite' seed=24757824120187919807900776632775341882491261426670308003772185046511517995047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24757824120187919807900776632775341882491261426670308003772185046511517995047 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/1.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"2.dma_generic_smoke.59656868982143621826249214896951522350180006753356094008746960018472575517920","seed":59656868982143621826249214896951522350180006753356094008746960018472575517920,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2685748448 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_generic_smoke.2685748448 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_generic_smoke.2685748448 -covoverwrite' seed=59656868982143621826249214896951522350180006753356094008746960018472575517920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59656868982143621826249214896951522350180006753356094008746960018472575517920 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"2.dma_memory_smoke.36323347657456893792887737408033735728072559484165364143724993552898550004837","seed":36323347657456893792887737408033735728072559484165364143724993552898550004837,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=366083173 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_memory_smoke.366083173 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_memory_smoke.366083173 -covoverwrite' seed=36323347657456893792887737408033735728072559484165364143724993552898550004837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36323347657456893792887737408033735728072559484165364143724993552898550004837 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"2.dma_handshake_smoke.104538382119354901100617061112739015671870434899257497924939113592639652407499","seed":104538382119354901100617061112739015671870434899257497924939113592639652407499,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=635480267 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_handshake_smoke.635480267 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_handshake_smoke.635480267 -covoverwrite' seed=104538382119354901100617061112739015671870434899257497924939113592639652407499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104538382119354901100617061112739015671870434899257497924939113592639652407499 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_region_lock","qual_name":"2.dma_memory_region_lock.1614974860829520278078907243849200436904841905168570860471505051814105742876","seed":1614974860829520278078907243849200436904841905168570860471505051814105742876,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_region_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_region_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3379330588 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_region_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_memory_region_lock.3379330588 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_memory_region_lock.3379330588 -covoverwrite' seed=1614974860829520278078907243849200436904841905168570860471505051814105742876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1614974860829520278078907243849200436904841905168570860471505051814105742876 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_region_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_region_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_abort","qual_name":"2.dma_abort.97156723330391381394759340696169296435301119653405300109318402996476571268617","seed":97156723330391381394759340696169296435301119653405300109318402996476571268617,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_abort/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_abort/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3021714953 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_abort_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_abort.3021714953 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_abort.3021714953 -covoverwrite' seed=97156723330391381394759340696169296435301119653405300109318402996476571268617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97156723330391381394759340696169296435301119653405300109318402996476571268617 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_abort/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_abort_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"2.dma_short_transfer.62764036554057087829991874481463377953428880473810611727194452308621845921129","seed":62764036554057087829991874481463377953428880473810611727194452308621845921129,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=857800041 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_short_transfer.857800041 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_short_transfer.857800041 -covoverwrite' seed=62764036554057087829991874481463377953428880473810611727194452308621845921129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62764036554057087829991874481463377953428880473810611727194452308621845921129 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_longer_transfer","qual_name":"2.dma_longer_transfer.49180784574694139090990227125244962445382066448367783179416954086495966872410","seed":49180784574694139090990227125244962445382066448367783179416954086495966872410,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_longer_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_longer_transfer/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2826584922 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_longer_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_longer_transfer.2826584922 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_longer_transfer.2826584922 -covoverwrite' seed=49180784574694139090990227125244962445382066448367783179416954086495966872410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49180784574694139090990227125244962445382066448367783179416954086495966872410 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_longer_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_longer_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_mem_enabled","qual_name":"2.dma_mem_enabled.1879026837681208446814213132624499281323000168839726026928357173874631189548","seed":1879026837681208446814213132624499281323000168839726026928357173874631189548,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_mem_enabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_mem_enabled/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1966154796 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_mem_enabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_mem_enabled.1966154796 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_mem_enabled.1966154796 -covoverwrite' seed=1879026837681208446814213132624499281323000168839726026928357173874631189548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1879026837681208446814213132624499281323000168839726026928357173874631189548 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_mem_enabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_mem_enabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"2.dma_config_lock.102560592884247747824699812806670723872997192474902443753790956812699649425089","seed":102560592884247747824699812806670723872997192474902443753790956812699649425089,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2775039681 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_config_lock.2775039681 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_config_lock.2775039681 -covoverwrite' seed=102560592884247747824699812806670723872997192474902443753790956812699649425089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102560592884247747824699812806670723872997192474902443753790956812699649425089 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_stress","qual_name":"2.dma_generic_stress.28228123278138170253901715794386985903461935962385503928584685394220084741168","seed":28228123278138170253901715794386985903461935962385503928584685394220084741168,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_generic_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_generic_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=174179376 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_generic_stress.174179376 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_generic_stress.174179376 -covoverwrite' seed=28228123278138170253901715794386985903461935962385503928584685394220084741168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28228123278138170253901715794386985903461935962385503928584685394220084741168 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_generic_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_stress","qual_name":"2.dma_memory_stress.56788715727563194171886946406857732357715362226482620930003673679234057097786","seed":56788715727563194171886946406857732357715362226482620930003673679234057097786,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2717110842 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_memory_stress.2717110842 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_memory_stress.2717110842 -covoverwrite' seed=56788715727563194171886946406857732357715362226482620930003673679234057097786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56788715727563194171886946406857732357715362226482620930003673679234057097786 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_memory_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_stress","qual_name":"2.dma_handshake_stress.86381211670346548069659268436902468431193461745211537381181825011219236634316","seed":86381211670346548069659268436902468431193461745211537381181825011219236634316,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_handshake_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_handshake_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=287555276 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_handshake_stress.287555276 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_handshake_stress.287555276 -covoverwrite' seed=86381211670346548069659268436902468431193461745211537381181825011219236634316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86381211670346548069659268436902468431193461745211537381181825011219236634316 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_handshake_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"2.dma_tl_errors.81994341134448126885330675369161676390913615737131180139527301967257835022279","seed":81994341134448126885330675369161676390913615737131180139527301967257835022279,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2764711879 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/2.dma_tl_errors.2764711879 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.dma_tl_errors.2764711879 -covoverwrite' seed=81994341134448126885330675369161676390913615737131180139527301967257835022279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81994341134448126885330675369161676390913615737131180139527301967257835022279 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"2.dma_tl_intg_err.35358053712275458535361490079381750306436427854077315382037791919252742271851","seed":35358053712275458535361490079381750306436427854077315382037791919252742271851,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=498266987 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/2.dma_tl_intg_err.498266987 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.dma_tl_intg_err.498266987 -covoverwrite' seed=35358053712275458535361490079381750306436427854077315382037791919252742271851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35358053712275458535361490079381750306436427854077315382037791919252742271851 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_sec_cm","qual_name":"2.dma_sec_cm.28077174662916762725596208798907879377452829063643792208447643220326491413877","seed":28077174662916762725596208798907879377452829063643792208447643220326491413877,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1517346165 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_sec_cm.1517346165 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_sec_cm.1517346165 -covoverwrite' seed=28077174662916762725596208798907879377452829063643792208447643220326491413877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28077174662916762725596208798907879377452829063643792208447643220326491413877 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"2.dma_intr_test.16906425911358972019234629810448676337788588567301815586402494991834631017871","seed":16906425911358972019234629810448676337788588567301815586402494991834631017871,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=36607375 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/2.dma_intr_test.36607375 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.dma_intr_test.36607375 -covoverwrite' seed=16906425911358972019234629810448676337788588567301815586402494991834631017871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16906425911358972019234629810448676337788588567301815586402494991834631017871 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_rw","qual_name":"2.dma_csr_rw.46844547864807545219578650932460235127011819372003570303738149943978807999536","seed":46844547864807545219578650932460235127011819372003570303738149943978807999536,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1488403504 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/2.dma_csr_rw.1488403504 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.dma_csr_rw.1488403504 -covoverwrite' seed=46844547864807545219578650932460235127011819372003570303738149943978807999536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46844547864807545219578650932460235127011819372003570303738149943978807999536 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_same_csr_outstanding","qual_name":"2.dma_same_csr_outstanding.74921186521760598336278398674602296360402871595729251304918617238107347582006","seed":74921186521760598336278398674602296360402871595729251304918617238107347582006,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3017899062 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/2.dma_same_csr_outstanding.3017899062 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.dma_same_csr_outstanding.3017899062 -covoverwrite' seed=74921186521760598336278398674602296360402871595729251304918617238107347582006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74921186521760598336278398674602296360402871595729251304918617238107347582006 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_mem_rw_with_rand_reset","qual_name":"2.dma_csr_mem_rw_with_rand_reset.105612936115125960006715541610137511995844336007129336797764621176846327113900","seed":105612936115125960006715541610137511995844336007129336797764621176846327113900,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2459330732 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/2.dma_csr_mem_rw_with_rand_reset.2459330732 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.dma_csr_mem_rw_with_rand_reset.2459330732 -covoverwrite' seed=105612936115125960006715541610137511995844336007129336797764621176846327113900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105612936115125960006715541610137511995844336007129336797764621176846327113900 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"2.dma_alert_test.10669836660311725358083546241111461873207183209416086531945442959661190011887","seed":10669836660311725358083546241111461873207183209416086531945442959661190011887,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=185785327 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/2.dma_alert_test.185785327 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 2.dma_alert_test.185785327 -covoverwrite' seed=10669836660311725358083546241111461873207183209416086531945442959661190011887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10669836660311725358083546241111461873207183209416086531945442959661190011887 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"3.dma_generic_smoke.8441828520393806381170820349850889963557299862238524441814031589031328971341","seed":8441828520393806381170820349850889963557299862238524441814031589031328971341,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4240538189 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_generic_smoke.4240538189 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_generic_smoke.4240538189 -covoverwrite' seed=8441828520393806381170820349850889963557299862238524441814031589031328971341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8441828520393806381170820349850889963557299862238524441814031589031328971341 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"3.dma_memory_smoke.93791129428241382168255141010982855742804842842324967668984757246727442004586","seed":93791129428241382168255141010982855742804842842324967668984757246727442004586,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2372008554 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_memory_smoke.2372008554 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_memory_smoke.2372008554 -covoverwrite' seed=93791129428241382168255141010982855742804842842324967668984757246727442004586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93791129428241382168255141010982855742804842842324967668984757246727442004586 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"3.dma_handshake_smoke.35602303905641886417103080816455609330534224819456074348016426041592342931953","seed":35602303905641886417103080816455609330534224819456074348016426041592342931953,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3437521393 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_handshake_smoke.3437521393 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_handshake_smoke.3437521393 -covoverwrite' seed=35602303905641886417103080816455609330534224819456074348016426041592342931953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35602303905641886417103080816455609330534224819456074348016426041592342931953 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_region_lock","qual_name":"3.dma_memory_region_lock.57643288768581526435962274922528036630098543225521546053413820366718313745563","seed":57643288768581526435962274922528036630098543225521546053413820366718313745563,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_memory_region_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_memory_region_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4229483675 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_region_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_memory_region_lock.4229483675 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_memory_region_lock.4229483675 -covoverwrite' seed=57643288768581526435962274922528036630098543225521546053413820366718313745563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57643288768581526435962274922528036630098543225521546053413820366718313745563 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_memory_region_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_region_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_abort","qual_name":"3.dma_abort.108521896598780007648722035261944860463618219748614779297169355351967073187489","seed":108521896598780007648722035261944860463618219748614779297169355351967073187489,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_abort/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_abort/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1531328161 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_abort_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_abort.1531328161 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_abort.1531328161 -covoverwrite' seed=108521896598780007648722035261944860463618219748614779297169355351967073187489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108521896598780007648722035261944860463618219748614779297169355351967073187489 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_abort/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_abort_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"3.dma_short_transfer.113858691189917909390270853221308853192413709542347516200856088389307169523000","seed":113858691189917909390270853221308853192413709542347516200856088389307169523000,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1730692408 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_short_transfer.1730692408 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_short_transfer.1730692408 -covoverwrite' seed=113858691189917909390270853221308853192413709542347516200856088389307169523000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113858691189917909390270853221308853192413709542347516200856088389307169523000 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_longer_transfer","qual_name":"3.dma_longer_transfer.18218075011718319802544479404722768113220386943669202470991586684225665620140","seed":18218075011718319802544479404722768113220386943669202470991586684225665620140,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_longer_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_longer_transfer/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2851854508 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_longer_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_longer_transfer.2851854508 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_longer_transfer.2851854508 -covoverwrite' seed=18218075011718319802544479404722768113220386943669202470991586684225665620140 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18218075011718319802544479404722768113220386943669202470991586684225665620140 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_longer_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_longer_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_mem_enabled","qual_name":"3.dma_mem_enabled.42649774748428419342025924999398616986389347879846573449535626925125810521045","seed":42649774748428419342025924999398616986389347879846573449535626925125810521045,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_mem_enabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_mem_enabled/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2790261717 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_mem_enabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_mem_enabled.2790261717 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_mem_enabled.2790261717 -covoverwrite' seed=42649774748428419342025924999398616986389347879846573449535626925125810521045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42649774748428419342025924999398616986389347879846573449535626925125810521045 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_mem_enabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_mem_enabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"3.dma_config_lock.9166591102185590446922397107066410441010584905936838481007468601023557632311","seed":9166591102185590446922397107066410441010584905936838481007468601023557632311,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1390772535 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_config_lock.1390772535 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_config_lock.1390772535 -covoverwrite' seed=9166591102185590446922397107066410441010584905936838481007468601023557632311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9166591102185590446922397107066410441010584905936838481007468601023557632311 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_stress","qual_name":"3.dma_generic_stress.45791126463050890669668870283971400705519614540643403480299164159318921111296","seed":45791126463050890669668870283971400705519614540643403480299164159318921111296,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_generic_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_generic_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4222150400 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_generic_stress.4222150400 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_generic_stress.4222150400 -covoverwrite' seed=45791126463050890669668870283971400705519614540643403480299164159318921111296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45791126463050890669668870283971400705519614540643403480299164159318921111296 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_generic_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"3.dma_tl_errors.62463935489065230108290944379716649016425707480036307743667936872936962984301","seed":62463935489065230108290944379716649016425707480036307743667936872936962984301,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3863415149 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/3.dma_tl_errors.3863415149 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.dma_tl_errors.3863415149 -covoverwrite' seed=62463935489065230108290944379716649016425707480036307743667936872936962984301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62463935489065230108290944379716649016425707480036307743667936872936962984301 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"3.dma_tl_intg_err.104146048480318946910162379433319894520444701578494964034643411131595124827692","seed":104146048480318946910162379433319894520444701578494964034643411131595124827692,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1623647788 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/3.dma_tl_intg_err.1623647788 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.dma_tl_intg_err.1623647788 -covoverwrite' seed=104146048480318946910162379433319894520444701578494964034643411131595124827692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104146048480318946910162379433319894520444701578494964034643411131595124827692 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_sec_cm","qual_name":"3.dma_sec_cm.47811119016289266289378325091922049434344059222510220238797615994647419403057","seed":47811119016289266289378325091922049434344059222510220238797615994647419403057,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1712175921 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_sec_cm.1712175921 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_sec_cm.1712175921 -covoverwrite' seed=47811119016289266289378325091922049434344059222510220238797615994647419403057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47811119016289266289378325091922049434344059222510220238797615994647419403057 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"3.dma_intr_test.105177405710420630564460355067400283660888553516608705670273268366968160703279","seed":105177405710420630564460355067400283660888553516608705670273268366968160703279,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2014237487 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/3.dma_intr_test.2014237487 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.dma_intr_test.2014237487 -covoverwrite' seed=105177405710420630564460355067400283660888553516608705670273268366968160703279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105177405710420630564460355067400283660888553516608705670273268366968160703279 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_rw","qual_name":"3.dma_csr_rw.18203338055867294293471192953237542029662645925558270083415553042161447386534","seed":18203338055867294293471192953237542029662645925558270083415553042161447386534,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2984164774 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/3.dma_csr_rw.2984164774 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.dma_csr_rw.2984164774 -covoverwrite' seed=18203338055867294293471192953237542029662645925558270083415553042161447386534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18203338055867294293471192953237542029662645925558270083415553042161447386534 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_same_csr_outstanding","qual_name":"3.dma_same_csr_outstanding.646490046869756181159582744688300541453523040832146345863618826438926998573","seed":646490046869756181159582744688300541453523040832146345863618826438926998573,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=932781101 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/3.dma_same_csr_outstanding.932781101 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.dma_same_csr_outstanding.932781101 -covoverwrite' seed=646490046869756181159582744688300541453523040832146345863618826438926998573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=646490046869756181159582744688300541453523040832146345863618826438926998573 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_mem_rw_with_rand_reset","qual_name":"3.dma_csr_mem_rw_with_rand_reset.66338702825305712095658075669964103962896741314704860032045532189917328804332","seed":66338702825305712095658075669964103962896741314704860032045532189917328804332,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2617346540 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/3.dma_csr_mem_rw_with_rand_reset.2617346540 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.dma_csr_mem_rw_with_rand_reset.2617346540 -covoverwrite' seed=66338702825305712095658075669964103962896741314704860032045532189917328804332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66338702825305712095658075669964103962896741314704860032045532189917328804332 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"3.dma_alert_test.82986803649737954360622773655486290448638523883647811842795868898956362264279","seed":82986803649737954360622773655486290448638523883647811842795868898956362264279,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2021273303 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/3.dma_alert_test.2021273303 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 3.dma_alert_test.2021273303 -covoverwrite' seed=82986803649737954360622773655486290448638523883647811842795868898956362264279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82986803649737954360622773655486290448638523883647811842795868898956362264279 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/3.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"4.dma_generic_smoke.83045474128039364436460578163909875984726724493639925502258767446012849591168","seed":83045474128039364436460578163909875984726724493639925502258767446012849591168,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2042139520 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_generic_smoke.2042139520 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_generic_smoke.2042139520 -covoverwrite' seed=83045474128039364436460578163909875984726724493639925502258767446012849591168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83045474128039364436460578163909875984726724493639925502258767446012849591168 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"4.dma_memory_smoke.52553211721707154523684050094435741123205566813700447094064214527410093586507","seed":52553211721707154523684050094435741123205566813700447094064214527410093586507,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1341552715 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_memory_smoke.1341552715 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_memory_smoke.1341552715 -covoverwrite' seed=52553211721707154523684050094435741123205566813700447094064214527410093586507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52553211721707154523684050094435741123205566813700447094064214527410093586507 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"4.dma_handshake_smoke.94853585770613145782016258327985233223512550836087248807949247849023558776479","seed":94853585770613145782016258327985233223512550836087248807949247849023558776479,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3476682399 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_handshake_smoke.3476682399 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_handshake_smoke.3476682399 -covoverwrite' seed=94853585770613145782016258327985233223512550836087248807949247849023558776479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94853585770613145782016258327985233223512550836087248807949247849023558776479 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_region_lock","qual_name":"4.dma_memory_region_lock.112871433047120567264687110090739839967985040587101763365079960632912246579727","seed":112871433047120567264687110090739839967985040587101763365079960632912246579727,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_memory_region_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_memory_region_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2063442447 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_region_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_memory_region_lock.2063442447 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_memory_region_lock.2063442447 -covoverwrite' seed=112871433047120567264687110090739839967985040587101763365079960632912246579727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112871433047120567264687110090739839967985040587101763365079960632912246579727 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_memory_region_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_region_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_abort","qual_name":"4.dma_abort.69704620515533722660943130305369520855535550724683264616564443635609530721094","seed":69704620515533722660943130305369520855535550724683264616564443635609530721094,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_abort/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_abort/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4246397766 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_abort_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_abort.4246397766 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_abort.4246397766 -covoverwrite' seed=69704620515533722660943130305369520855535550724683264616564443635609530721094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69704620515533722660943130305369520855535550724683264616564443635609530721094 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_abort/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_abort_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"4.dma_short_transfer.93584643726764301292040974218895477133264660161632756393682681230429676685531","seed":93584643726764301292040974218895477133264660161632756393682681230429676685531,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2467875035 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_short_transfer.2467875035 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_short_transfer.2467875035 -covoverwrite' seed=93584643726764301292040974218895477133264660161632756393682681230429676685531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93584643726764301292040974218895477133264660161632756393682681230429676685531 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_longer_transfer","qual_name":"4.dma_longer_transfer.36899237943173081228020673194298453403693816877564484439171225078643502703055","seed":36899237943173081228020673194298453403693816877564484439171225078643502703055,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_longer_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_longer_transfer/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3366805967 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_longer_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_longer_transfer.3366805967 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_longer_transfer.3366805967 -covoverwrite' seed=36899237943173081228020673194298453403693816877564484439171225078643502703055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36899237943173081228020673194298453403693816877564484439171225078643502703055 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_longer_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_longer_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_mem_enabled","qual_name":"4.dma_mem_enabled.21538061429029473636734547949563653433744148714302879081429832569012199495453","seed":21538061429029473636734547949563653433744148714302879081429832569012199495453,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_mem_enabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_mem_enabled/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4049213213 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_mem_enabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_mem_enabled.4049213213 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_mem_enabled.4049213213 -covoverwrite' seed=21538061429029473636734547949563653433744148714302879081429832569012199495453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21538061429029473636734547949563653433744148714302879081429832569012199495453 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_mem_enabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_mem_enabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"4.dma_config_lock.8983398943159705886442830286314054011035946122740690655606248622427820541900","seed":8983398943159705886442830286314054011035946122740690655606248622427820541900,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3515369420 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_config_lock.3515369420 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_config_lock.3515369420 -covoverwrite' seed=8983398943159705886442830286314054011035946122740690655606248622427820541900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8983398943159705886442830286314054011035946122740690655606248622427820541900 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_stress","qual_name":"4.dma_generic_stress.68035253350587218575904055908700872075819485829423460066672666954655719310583","seed":68035253350587218575904055908700872075819485829423460066672666954655719310583,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_generic_stress/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_generic_stress/latest run_opts='+test_timeout_ns=300_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1999717623 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_generic_stress.1999717623 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_generic_stress.1999717623 -covoverwrite' seed=68035253350587218575904055908700872075819485829423460066672666954655719310583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68035253350587218575904055908700872075819485829423460066672666954655719310583 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_generic_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_stress_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"4.dma_tl_errors.77234659277950418638349123422622356290063992369052184915697497484092213955325","seed":77234659277950418638349123422622356290063992369052184915697497484092213955325,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4076210941 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/4.dma_tl_errors.4076210941 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.dma_tl_errors.4076210941 -covoverwrite' seed=77234659277950418638349123422622356290063992369052184915697497484092213955325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77234659277950418638349123422622356290063992369052184915697497484092213955325 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"4.dma_tl_intg_err.2274527469768517430115654932299230342766816370203684941442945710377812523956","seed":2274527469768517430115654932299230342766816370203684941442945710377812523956,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4071783348 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/4.dma_tl_intg_err.4071783348 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.dma_tl_intg_err.4071783348 -covoverwrite' seed=2274527469768517430115654932299230342766816370203684941442945710377812523956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2274527469768517430115654932299230342766816370203684941442945710377812523956 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_sec_cm","qual_name":"4.dma_sec_cm.14011775620192733850611171861145625531609092967034806313000028362962372872045","seed":14011775620192733850611171861145625531609092967034806313000028362962372872045,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1889748845 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_sec_cm.1889748845 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_sec_cm.1889748845 -covoverwrite' seed=14011775620192733850611171861145625531609092967034806313000028362962372872045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14011775620192733850611171861145625531609092967034806313000028362962372872045 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"4.dma_intr_test.44966808570925471497559287569432918007690449542673026374264746015769216948588","seed":44966808570925471497559287569432918007690449542673026374264746015769216948588,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1474566508 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/4.dma_intr_test.1474566508 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.dma_intr_test.1474566508 -covoverwrite' seed=44966808570925471497559287569432918007690449542673026374264746015769216948588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44966808570925471497559287569432918007690449542673026374264746015769216948588 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_rw","qual_name":"4.dma_csr_rw.66788747460841569410282347150500662703475150467168717573519937928079020575988","seed":66788747460841569410282347150500662703475150467168717573519937928079020575988,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3955150068 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/4.dma_csr_rw.3955150068 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.dma_csr_rw.3955150068 -covoverwrite' seed=66788747460841569410282347150500662703475150467168717573519937928079020575988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66788747460841569410282347150500662703475150467168717573519937928079020575988 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_same_csr_outstanding","qual_name":"4.dma_same_csr_outstanding.102540097436866254015964375430647459687439821533623861092132532846661096217892","seed":102540097436866254015964375430647459687439821533623861092132532846661096217892,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3094650148 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/4.dma_same_csr_outstanding.3094650148 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.dma_same_csr_outstanding.3094650148 -covoverwrite' seed=102540097436866254015964375430647459687439821533623861092132532846661096217892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102540097436866254015964375430647459687439821533623861092132532846661096217892 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_csr_mem_rw_with_rand_reset","qual_name":"4.dma_csr_mem_rw_with_rand_reset.29694539391413028048430272577841672437045848092376574264467592054155805320630","seed":29694539391413028048430272577841672437045848092376574264467592054155805320630,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3674072502 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/4.dma_csr_mem_rw_with_rand_reset.3674072502 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.dma_csr_mem_rw_with_rand_reset.3674072502 -covoverwrite' seed=29694539391413028048430272577841672437045848092376574264467592054155805320630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29694539391413028048430272577841672437045848092376574264467592054155805320630 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"4.dma_alert_test.68097752456473330440649964504879326454227801069053091819472603057940220081227","seed":68097752456473330440649964504879326454227801069053091819472603057940220081227,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3205231691 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/4.dma_alert_test.3205231691 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 4.dma_alert_test.3205231691 -covoverwrite' seed=68097752456473330440649964504879326454227801069053091819472603057940220081227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68097752456473330440649964504879326454227801069053091819472603057940220081227 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/4.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"5.dma_generic_smoke.45882654540703464719495287675553725322100149598028151686900316484155537446536","seed":45882654540703464719495287675553725322100149598028151686900316484155537446536,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2267633288 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/5.dma_generic_smoke.2267633288 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 5.dma_generic_smoke.2267633288 -covoverwrite' seed=45882654540703464719495287675553725322100149598028151686900316484155537446536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45882654540703464719495287675553725322100149598028151686900316484155537446536 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"5.dma_memory_smoke.106797992322882317917886092452542639499408101274045894783711998012270329701223","seed":106797992322882317917886092452542639499408101274045894783711998012270329701223,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2660737895 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/5.dma_memory_smoke.2660737895 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 5.dma_memory_smoke.2660737895 -covoverwrite' seed=106797992322882317917886092452542639499408101274045894783711998012270329701223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106797992322882317917886092452542639499408101274045894783711998012270329701223 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"5.dma_handshake_smoke.76556107886531429330307030780048902270890506015537012848905283980183951343023","seed":76556107886531429330307030780048902270890506015537012848905283980183951343023,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=707755439 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/5.dma_handshake_smoke.707755439 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 5.dma_handshake_smoke.707755439 -covoverwrite' seed=76556107886531429330307030780048902270890506015537012848905283980183951343023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76556107886531429330307030780048902270890506015537012848905283980183951343023 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"5.dma_short_transfer.2258095463677974293057390908584062741831805092992853424848893499005829053243","seed":2258095463677974293057390908584062741831805092992853424848893499005829053243,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1255865147 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/5.dma_short_transfer.1255865147 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 5.dma_short_transfer.1255865147 -covoverwrite' seed=2258095463677974293057390908584062741831805092992853424848893499005829053243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2258095463677974293057390908584062741831805092992853424848893499005829053243 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"5.dma_config_lock.15144808178230070026556530876424156964769169185150858647041392421476503295372","seed":15144808178230070026556530876424156964769169185150858647041392421476503295372,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=882546060 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/5.dma_config_lock.882546060 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 5.dma_config_lock.882546060 -covoverwrite' seed=15144808178230070026556530876424156964769169185150858647041392421476503295372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15144808178230070026556530876424156964769169185150858647041392421476503295372 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"5.dma_tl_errors.114123853842391327893263899717813574879495447722314883110432636032402274790250","seed":114123853842391327893263899717813574879495447722314883110432636032402274790250,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=532294506 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/5.dma_tl_errors.532294506 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.dma_tl_errors.532294506 -covoverwrite' seed=114123853842391327893263899717813574879495447722314883110432636032402274790250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114123853842391327893263899717813574879495447722314883110432636032402274790250 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"5.dma_tl_intg_err.49038310009352355701456359028457896526544502330314527653106176001928731845109","seed":49038310009352355701456359028457896526544502330314527653106176001928731845109,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=106979829 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/5.dma_tl_intg_err.106979829 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.dma_tl_intg_err.106979829 -covoverwrite' seed=49038310009352355701456359028457896526544502330314527653106176001928731845109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49038310009352355701456359028457896526544502330314527653106176001928731845109 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"5.dma_intr_test.52750492103155642075782175665922607204610292708152747700765644353449353366361","seed":52750492103155642075782175665922607204610292708152747700765644353449353366361,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3637857113 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/5.dma_intr_test.3637857113 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.dma_intr_test.3637857113 -covoverwrite' seed=52750492103155642075782175665922607204610292708152747700765644353449353366361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52750492103155642075782175665922607204610292708152747700765644353449353366361 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"5.dma_alert_test.4604377482968435156635261085625655158086413667688504468553422236681947994155","seed":4604377482968435156635261085625655158086413667688504468553422236681947994155,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=975853611 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/5.dma_alert_test.975853611 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 5.dma_alert_test.975853611 -covoverwrite' seed=4604377482968435156635261085625655158086413667688504468553422236681947994155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4604377482968435156635261085625655158086413667688504468553422236681947994155 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/5.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"6.dma_generic_smoke.15261116858363840589400600076675250091384253168452359152219474433610800916450","seed":15261116858363840589400600076675250091384253168452359152219474433610800916450,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3252119522 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/6.dma_generic_smoke.3252119522 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 6.dma_generic_smoke.3252119522 -covoverwrite' seed=15261116858363840589400600076675250091384253168452359152219474433610800916450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15261116858363840589400600076675250091384253168452359152219474433610800916450 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"6.dma_memory_smoke.57491555937552333783967509364783260077377301491432469377975307744109715734670","seed":57491555937552333783967509364783260077377301491432469377975307744109715734670,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3117367438 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/6.dma_memory_smoke.3117367438 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 6.dma_memory_smoke.3117367438 -covoverwrite' seed=57491555937552333783967509364783260077377301491432469377975307744109715734670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57491555937552333783967509364783260077377301491432469377975307744109715734670 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"6.dma_handshake_smoke.76478079519492372850444343969652071285384032399759096709630761746484724313598","seed":76478079519492372850444343969652071285384032399759096709630761746484724313598,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3491573246 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/6.dma_handshake_smoke.3491573246 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 6.dma_handshake_smoke.3491573246 -covoverwrite' seed=76478079519492372850444343969652071285384032399759096709630761746484724313598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76478079519492372850444343969652071285384032399759096709630761746484724313598 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"6.dma_short_transfer.57224991476118338705970062889935322143021425289941001038563232864833748830610","seed":57224991476118338705970062889935322143021425289941001038563232864833748830610,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4126378386 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/6.dma_short_transfer.4126378386 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 6.dma_short_transfer.4126378386 -covoverwrite' seed=57224991476118338705970062889935322143021425289941001038563232864833748830610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57224991476118338705970062889935322143021425289941001038563232864833748830610 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"6.dma_config_lock.99296196411692073289215493736991056693433801937899776788176382472035715447194","seed":99296196411692073289215493736991056693433801937899776788176382472035715447194,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2593585562 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/6.dma_config_lock.2593585562 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 6.dma_config_lock.2593585562 -covoverwrite' seed=99296196411692073289215493736991056693433801937899776788176382472035715447194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99296196411692073289215493736991056693433801937899776788176382472035715447194 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"6.dma_tl_errors.113375790962634871909028595318701289818462671552913459199149651136720318282526","seed":113375790962634871909028595318701289818462671552913459199149651136720318282526,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1096596254 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/6.dma_tl_errors.1096596254 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.dma_tl_errors.1096596254 -covoverwrite' seed=113375790962634871909028595318701289818462671552913459199149651136720318282526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113375790962634871909028595318701289818462671552913459199149651136720318282526 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"6.dma_tl_intg_err.59597201771410737760796403384659893676359366375661891318255901910286549195324","seed":59597201771410737760796403384659893676359366375661891318255901910286549195324,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4083489340 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/6.dma_tl_intg_err.4083489340 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.dma_tl_intg_err.4083489340 -covoverwrite' seed=59597201771410737760796403384659893676359366375661891318255901910286549195324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59597201771410737760796403384659893676359366375661891318255901910286549195324 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"6.dma_intr_test.69422017230884294003977465535150590718261152518606499415943306230063347923432","seed":69422017230884294003977465535150590718261152518606499415943306230063347923432,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3273783784 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/6.dma_intr_test.3273783784 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.dma_intr_test.3273783784 -covoverwrite' seed=69422017230884294003977465535150590718261152518606499415943306230063347923432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69422017230884294003977465535150590718261152518606499415943306230063347923432 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"6.dma_alert_test.53298624148170526246263240395702704929806088889047799877844576054040669988674","seed":53298624148170526246263240395702704929806088889047799877844576054040669988674,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4032833346 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/6.dma_alert_test.4032833346 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 6.dma_alert_test.4032833346 -covoverwrite' seed=53298624148170526246263240395702704929806088889047799877844576054040669988674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53298624148170526246263240395702704929806088889047799877844576054040669988674 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"7.dma_generic_smoke.33067657019686389140495560613919635217957175177731678496879379094593414585970","seed":33067657019686389140495560613919635217957175177731678496879379094593414585970,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1696292466 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/7.dma_generic_smoke.1696292466 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 7.dma_generic_smoke.1696292466 -covoverwrite' seed=33067657019686389140495560613919635217957175177731678496879379094593414585970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33067657019686389140495560613919635217957175177731678496879379094593414585970 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"7.dma_memory_smoke.36735644097250898878482157261409408678506070085671718112686016401500789075155","seed":36735644097250898878482157261409408678506070085671718112686016401500789075155,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3595103443 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/7.dma_memory_smoke.3595103443 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 7.dma_memory_smoke.3595103443 -covoverwrite' seed=36735644097250898878482157261409408678506070085671718112686016401500789075155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36735644097250898878482157261409408678506070085671718112686016401500789075155 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"7.dma_handshake_smoke.57293260249453784179151264931658061057207264195825458455344999891009283251944","seed":57293260249453784179151264931658061057207264195825458455344999891009283251944,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1429167848 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/7.dma_handshake_smoke.1429167848 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 7.dma_handshake_smoke.1429167848 -covoverwrite' seed=57293260249453784179151264931658061057207264195825458455344999891009283251944 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57293260249453784179151264931658061057207264195825458455344999891009283251944 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"7.dma_short_transfer.89841480611703477670360818154908426964531904204388824092714751491484724931023","seed":89841480611703477670360818154908426964531904204388824092714751491484724931023,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3442125263 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/7.dma_short_transfer.3442125263 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 7.dma_short_transfer.3442125263 -covoverwrite' seed=89841480611703477670360818154908426964531904204388824092714751491484724931023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89841480611703477670360818154908426964531904204388824092714751491484724931023 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"7.dma_config_lock.106700506606917170298676044144414353147195688929833900893818475151237697286789","seed":106700506606917170298676044144414353147195688929833900893818475151237697286789,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=523285125 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/7.dma_config_lock.523285125 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 7.dma_config_lock.523285125 -covoverwrite' seed=106700506606917170298676044144414353147195688929833900893818475151237697286789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106700506606917170298676044144414353147195688929833900893818475151237697286789 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"7.dma_tl_errors.14037157132302529383989810936571881089350630584968643808516477608538974726720","seed":14037157132302529383989810936571881089350630584968643808516477608538974726720,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1020799552 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/7.dma_tl_errors.1020799552 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.dma_tl_errors.1020799552 -covoverwrite' seed=14037157132302529383989810936571881089350630584968643808516477608538974726720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14037157132302529383989810936571881089350630584968643808516477608538974726720 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"7.dma_tl_intg_err.18127430641792451726011822136962347744593148657687834888690872592469948089640","seed":18127430641792451726011822136962347744593148657687834888690872592469948089640,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=762823976 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/7.dma_tl_intg_err.762823976 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.dma_tl_intg_err.762823976 -covoverwrite' seed=18127430641792451726011822136962347744593148657687834888690872592469948089640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18127430641792451726011822136962347744593148657687834888690872592469948089640 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"7.dma_intr_test.2192708796947332356804237007314494703545472002656059440605677446825979046128","seed":2192708796947332356804237007314494703545472002656059440605677446825979046128,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3724962032 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/7.dma_intr_test.3724962032 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.dma_intr_test.3724962032 -covoverwrite' seed=2192708796947332356804237007314494703545472002656059440605677446825979046128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2192708796947332356804237007314494703545472002656059440605677446825979046128 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"7.dma_alert_test.68084398596948655017052688188988391221078690747320891884826160077023663756118","seed":68084398596948655017052688188988391221078690747320891884826160077023663756118,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1750471510 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/7.dma_alert_test.1750471510 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 7.dma_alert_test.1750471510 -covoverwrite' seed=68084398596948655017052688188988391221078690747320891884826160077023663756118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68084398596948655017052688188988391221078690747320891884826160077023663756118 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/7.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"8.dma_generic_smoke.41415880766952653689900820267174346722674268618992306389464137765997539495054","seed":41415880766952653689900820267174346722674268618992306389464137765997539495054,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2178419854 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/8.dma_generic_smoke.2178419854 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 8.dma_generic_smoke.2178419854 -covoverwrite' seed=41415880766952653689900820267174346722674268618992306389464137765997539495054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41415880766952653689900820267174346722674268618992306389464137765997539495054 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"8.dma_memory_smoke.4806813620958902520359578042070465524203775359504556671744459702317074974082","seed":4806813620958902520359578042070465524203775359504556671744459702317074974082,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2343404930 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/8.dma_memory_smoke.2343404930 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 8.dma_memory_smoke.2343404930 -covoverwrite' seed=4806813620958902520359578042070465524203775359504556671744459702317074974082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4806813620958902520359578042070465524203775359504556671744459702317074974082 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"8.dma_handshake_smoke.51678750153751074147069103115821375941270240501836827516931532132211816834341","seed":51678750153751074147069103115821375941270240501836827516931532132211816834341,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3641615653 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/8.dma_handshake_smoke.3641615653 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 8.dma_handshake_smoke.3641615653 -covoverwrite' seed=51678750153751074147069103115821375941270240501836827516931532132211816834341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51678750153751074147069103115821375941270240501836827516931532132211816834341 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"8.dma_short_transfer.101286171978424612190043854032469785292941947853153075214982981069399851055648","seed":101286171978424612190043854032469785292941947853153075214982981069399851055648,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=477674016 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/8.dma_short_transfer.477674016 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 8.dma_short_transfer.477674016 -covoverwrite' seed=101286171978424612190043854032469785292941947853153075214982981069399851055648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101286171978424612190043854032469785292941947853153075214982981069399851055648 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"8.dma_config_lock.41353187330005143283768326303296686332257805930240330510573322251187319655072","seed":41353187330005143283768326303296686332257805930240330510573322251187319655072,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=339135136 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/8.dma_config_lock.339135136 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 8.dma_config_lock.339135136 -covoverwrite' seed=41353187330005143283768326303296686332257805930240330510573322251187319655072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41353187330005143283768326303296686332257805930240330510573322251187319655072 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"8.dma_tl_errors.11783704613010121716603626202119786537421566935784024208870784713908741813609","seed":11783704613010121716603626202119786537421566935784024208870784713908741813609,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2360685929 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/8.dma_tl_errors.2360685929 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.dma_tl_errors.2360685929 -covoverwrite' seed=11783704613010121716603626202119786537421566935784024208870784713908741813609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11783704613010121716603626202119786537421566935784024208870784713908741813609 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"8.dma_tl_intg_err.51237725319403927866936020831970256009835345054314846581121948967649260719989","seed":51237725319403927866936020831970256009835345054314846581121948967649260719989,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=317312885 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/8.dma_tl_intg_err.317312885 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.dma_tl_intg_err.317312885 -covoverwrite' seed=51237725319403927866936020831970256009835345054314846581121948967649260719989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51237725319403927866936020831970256009835345054314846581121948967649260719989 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"8.dma_intr_test.32127577855162442729250019132643391045252593401956924061974106287414638370044","seed":32127577855162442729250019132643391045252593401956924061974106287414638370044,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3493158140 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/8.dma_intr_test.3493158140 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.dma_intr_test.3493158140 -covoverwrite' seed=32127577855162442729250019132643391045252593401956924061974106287414638370044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32127577855162442729250019132643391045252593401956924061974106287414638370044 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"8.dma_alert_test.112422764348880468709676976509069388121606161604430810290064305974280037795486","seed":112422764348880468709676976509069388121606161604430810290064305974280037795486,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3025077918 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/8.dma_alert_test.3025077918 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 8.dma_alert_test.3025077918 -covoverwrite' seed=112422764348880468709676976509069388121606161604430810290064305974280037795486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112422764348880468709676976509069388121606161604430810290064305974280037795486 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/8.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"9.dma_generic_smoke.105634543258303649860475305495973035439540260010868891495405112487111475129410","seed":105634543258303649860475305495973035439540260010868891495405112487111475129410,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1423764546 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/9.dma_generic_smoke.1423764546 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 9.dma_generic_smoke.1423764546 -covoverwrite' seed=105634543258303649860475305495973035439540260010868891495405112487111475129410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105634543258303649860475305495973035439540260010868891495405112487111475129410 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"9.dma_memory_smoke.66672062000009611671643394493263678167359140033348282121959025203574804913498","seed":66672062000009611671643394493263678167359140033348282121959025203574804913498,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3465354586 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/9.dma_memory_smoke.3465354586 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 9.dma_memory_smoke.3465354586 -covoverwrite' seed=66672062000009611671643394493263678167359140033348282121959025203574804913498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66672062000009611671643394493263678167359140033348282121959025203574804913498 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"9.dma_handshake_smoke.102582539477619158558414095502318948395970365472287189103714467564381623392999","seed":102582539477619158558414095502318948395970365472287189103714467564381623392999,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1351719655 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/9.dma_handshake_smoke.1351719655 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 9.dma_handshake_smoke.1351719655 -covoverwrite' seed=102582539477619158558414095502318948395970365472287189103714467564381623392999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102582539477619158558414095502318948395970365472287189103714467564381623392999 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"9.dma_short_transfer.52555995348513199955409304181709994644602347728791481156331381834528147334130","seed":52555995348513199955409304181709994644602347728791481156331381834528147334130,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1711236082 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/9.dma_short_transfer.1711236082 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 9.dma_short_transfer.1711236082 -covoverwrite' seed=52555995348513199955409304181709994644602347728791481156331381834528147334130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52555995348513199955409304181709994644602347728791481156331381834528147334130 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"9.dma_config_lock.30429467578027852593497748892204838752949917670437061239333766344820780084386","seed":30429467578027852593497748892204838752949917670437061239333766344820780084386,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1535290530 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/9.dma_config_lock.1535290530 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 9.dma_config_lock.1535290530 -covoverwrite' seed=30429467578027852593497748892204838752949917670437061239333766344820780084386 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30429467578027852593497748892204838752949917670437061239333766344820780084386 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"9.dma_tl_errors.75533419173366683935229479763313748249201217394586843344122653877686342230560","seed":75533419173366683935229479763313748249201217394586843344122653877686342230560,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1017356832 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/9.dma_tl_errors.1017356832 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.dma_tl_errors.1017356832 -covoverwrite' seed=75533419173366683935229479763313748249201217394586843344122653877686342230560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75533419173366683935229479763313748249201217394586843344122653877686342230560 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"9.dma_tl_intg_err.62782473421626831946401550620764052467672434299858057153446928511673478427560","seed":62782473421626831946401550620764052467672434299858057153446928511673478427560,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1783903144 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/9.dma_tl_intg_err.1783903144 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.dma_tl_intg_err.1783903144 -covoverwrite' seed=62782473421626831946401550620764052467672434299858057153446928511673478427560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62782473421626831946401550620764052467672434299858057153446928511673478427560 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_intr_test","qual_name":"9.dma_intr_test.76824939854654352143494142076304881326147674983438053328713139449848308839357","seed":76824939854654352143494142076304881326147674983438053328713139449848308839357,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1743926205 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/9.dma_intr_test.1743926205 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.dma_intr_test.1743926205 -covoverwrite' seed=76824939854654352143494142076304881326147674983438053328713139449848308839357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76824939854654352143494142076304881326147674983438053328713139449848308839357 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_alert_test","qual_name":"9.dma_alert_test.104530585533298602213978606450654211547633047347600927198461308421541740080093","seed":104530585533298602213978606450654211547633047347600927198461308421541740080093,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_alert_test/latest run_opts='+run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=844295133 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/9.dma_alert_test.844295133 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 9.dma_alert_test.844295133 -covoverwrite' seed=104530585533298602213978606450654211547633047347600927198461308421541740080093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104530585533298602213978606450654211547633047347600927198461308421541740080093 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/9.dma_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"10.dma_generic_smoke.59857172420369785680750652856107822785653734067037579304175974067099211507161","seed":59857172420369785680750652856107822785653734067037579304175974067099211507161,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3795953113 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/10.dma_generic_smoke.3795953113 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 10.dma_generic_smoke.3795953113 -covoverwrite' seed=59857172420369785680750652856107822785653734067037579304175974067099211507161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59857172420369785680750652856107822785653734067037579304175974067099211507161 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"10.dma_memory_smoke.51412100526302799106054146776344123105225580085868696947288623044987976193171","seed":51412100526302799106054146776344123105225580085868696947288623044987976193171,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=97031315 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/10.dma_memory_smoke.97031315 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 10.dma_memory_smoke.97031315 -covoverwrite' seed=51412100526302799106054146776344123105225580085868696947288623044987976193171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51412100526302799106054146776344123105225580085868696947288623044987976193171 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"10.dma_handshake_smoke.22213384216576129939551726707424148204381817506540341438023269648507254491758","seed":22213384216576129939551726707424148204381817506540341438023269648507254491758,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3319417454 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/10.dma_handshake_smoke.3319417454 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 10.dma_handshake_smoke.3319417454 -covoverwrite' seed=22213384216576129939551726707424148204381817506540341438023269648507254491758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22213384216576129939551726707424148204381817506540341438023269648507254491758 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"10.dma_short_transfer.27181483026262698890618056501667452371775561084331473457476533391024905509832","seed":27181483026262698890618056501667452371775561084331473457476533391024905509832,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3228556232 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/10.dma_short_transfer.3228556232 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 10.dma_short_transfer.3228556232 -covoverwrite' seed=27181483026262698890618056501667452371775561084331473457476533391024905509832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27181483026262698890618056501667452371775561084331473457476533391024905509832 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"10.dma_config_lock.5100972799597930381600486842489077406875107487591562509085313498898412720585","seed":5100972799597930381600486842489077406875107487591562509085313498898412720585,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1337053641 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/10.dma_config_lock.1337053641 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 10.dma_config_lock.1337053641 -covoverwrite' seed=5100972799597930381600486842489077406875107487591562509085313498898412720585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5100972799597930381600486842489077406875107487591562509085313498898412720585 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"10.dma_tl_errors.37224429599919244582397577015579739089721050218634744089778952586437627316808","seed":37224429599919244582397577015579739089721050218634744089778952586437627316808,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2083097160 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/10.dma_tl_errors.2083097160 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.dma_tl_errors.2083097160 -covoverwrite' seed=37224429599919244582397577015579739089721050218634744089778952586437627316808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37224429599919244582397577015579739089721050218634744089778952586437627316808 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"10.dma_tl_intg_err.107036095281126982968308356384184016060906163115553044148847583363424676585927","seed":107036095281126982968308356384184016060906163115553044148847583363424676585927,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3274285511 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/10.dma_tl_intg_err.3274285511 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.dma_tl_intg_err.3274285511 -covoverwrite' seed=107036095281126982968308356384184016060906163115553044148847583363424676585927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107036095281126982968308356384184016060906163115553044148847583363424676585927 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/10.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"11.dma_generic_smoke.57590466959094097438478432284493175326661099946267305700017615780551242695788","seed":57590466959094097438478432284493175326661099946267305700017615780551242695788,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1015956588 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/11.dma_generic_smoke.1015956588 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 11.dma_generic_smoke.1015956588 -covoverwrite' seed=57590466959094097438478432284493175326661099946267305700017615780551242695788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57590466959094097438478432284493175326661099946267305700017615780551242695788 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"11.dma_memory_smoke.74627276162470789858865312251523941497451201696758538161865325516460716991531","seed":74627276162470789858865312251523941497451201696758538161865325516460716991531,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4145554475 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/11.dma_memory_smoke.4145554475 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 11.dma_memory_smoke.4145554475 -covoverwrite' seed=74627276162470789858865312251523941497451201696758538161865325516460716991531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74627276162470789858865312251523941497451201696758538161865325516460716991531 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"11.dma_handshake_smoke.74534322880744859105004048906193019975172056186081315076024538147879760806870","seed":74534322880744859105004048906193019975172056186081315076024538147879760806870,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=94749654 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/11.dma_handshake_smoke.94749654 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 11.dma_handshake_smoke.94749654 -covoverwrite' seed=74534322880744859105004048906193019975172056186081315076024538147879760806870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74534322880744859105004048906193019975172056186081315076024538147879760806870 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"11.dma_short_transfer.61710886406742447605127278237577631608279126740787832042249683551693628526491","seed":61710886406742447605127278237577631608279126740787832042249683551693628526491,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2598129563 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/11.dma_short_transfer.2598129563 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 11.dma_short_transfer.2598129563 -covoverwrite' seed=61710886406742447605127278237577631608279126740787832042249683551693628526491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61710886406742447605127278237577631608279126740787832042249683551693628526491 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"11.dma_config_lock.45534897535945335327153105639859185497252648309962949842215688541826667181590","seed":45534897535945335327153105639859185497252648309962949842215688541826667181590,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1673197078 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/11.dma_config_lock.1673197078 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 11.dma_config_lock.1673197078 -covoverwrite' seed=45534897535945335327153105639859185497252648309962949842215688541826667181590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45534897535945335327153105639859185497252648309962949842215688541826667181590 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"11.dma_tl_errors.101149882897314486888883310307645727579173524279510900857227963333898913951717","seed":101149882897314486888883310307645727579173524279510900857227963333898913951717,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1680322533 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/11.dma_tl_errors.1680322533 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.dma_tl_errors.1680322533 -covoverwrite' seed=101149882897314486888883310307645727579173524279510900857227963333898913951717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101149882897314486888883310307645727579173524279510900857227963333898913951717 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"11.dma_tl_intg_err.21522062045883992561963730551063022285630863480252595090803922340892302513258","seed":21522062045883992561963730551063022285630863480252595090803922340892302513258,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2238583914 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/11.dma_tl_intg_err.2238583914 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.dma_tl_intg_err.2238583914 -covoverwrite' seed=21522062045883992561963730551063022285630863480252595090803922340892302513258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21522062045883992561963730551063022285630863480252595090803922340892302513258 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"12.dma_generic_smoke.102196465995498377728310473687124178943786984938790969951988405253670184407600","seed":102196465995498377728310473687124178943786984938790969951988405253670184407600,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3264467504 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/12.dma_generic_smoke.3264467504 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 12.dma_generic_smoke.3264467504 -covoverwrite' seed=102196465995498377728310473687124178943786984938790969951988405253670184407600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102196465995498377728310473687124178943786984938790969951988405253670184407600 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"12.dma_memory_smoke.64973908088761948574442106751177258187124236556518838775509970243765082743003","seed":64973908088761948574442106751177258187124236556518838775509970243765082743003,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2441044187 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/12.dma_memory_smoke.2441044187 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 12.dma_memory_smoke.2441044187 -covoverwrite' seed=64973908088761948574442106751177258187124236556518838775509970243765082743003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64973908088761948574442106751177258187124236556518838775509970243765082743003 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"12.dma_handshake_smoke.69762257936283771581112114804846733922968071904896696031679771359190527405770","seed":69762257936283771581112114804846733922968071904896696031679771359190527405770,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2033872586 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/12.dma_handshake_smoke.2033872586 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 12.dma_handshake_smoke.2033872586 -covoverwrite' seed=69762257936283771581112114804846733922968071904896696031679771359190527405770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69762257936283771581112114804846733922968071904896696031679771359190527405770 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"12.dma_short_transfer.108973346288035030063172314851206873455491638355121307599629524496644531473660","seed":108973346288035030063172314851206873455491638355121307599629524496644531473660,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=54709500 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/12.dma_short_transfer.54709500 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 12.dma_short_transfer.54709500 -covoverwrite' seed=108973346288035030063172314851206873455491638355121307599629524496644531473660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108973346288035030063172314851206873455491638355121307599629524496644531473660 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"12.dma_config_lock.90170921765508715192313398410558763080121703692300143217785222784807415020637","seed":90170921765508715192313398410558763080121703692300143217785222784807415020637,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3919019101 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/12.dma_config_lock.3919019101 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 12.dma_config_lock.3919019101 -covoverwrite' seed=90170921765508715192313398410558763080121703692300143217785222784807415020637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90170921765508715192313398410558763080121703692300143217785222784807415020637 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"12.dma_tl_errors.59559586983351770584281074944036351326116722590239173855389738973696013812111","seed":59559586983351770584281074944036351326116722590239173855389738973696013812111,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=295092623 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/12.dma_tl_errors.295092623 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.dma_tl_errors.295092623 -covoverwrite' seed=59559586983351770584281074944036351326116722590239173855389738973696013812111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59559586983351770584281074944036351326116722590239173855389738973696013812111 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"12.dma_tl_intg_err.89584952226195514731725867136333095412082013279400317374780458992655499756425","seed":89584952226195514731725867136333095412082013279400317374780458992655499756425,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1224967049 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/12.dma_tl_intg_err.1224967049 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.dma_tl_intg_err.1224967049 -covoverwrite' seed=89584952226195514731725867136333095412082013279400317374780458992655499756425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89584952226195514731725867136333095412082013279400317374780458992655499756425 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/12.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"13.dma_generic_smoke.40932669636721420547069743072617208540470057685919059352258111451514274007456","seed":40932669636721420547069743072617208540470057685919059352258111451514274007456,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3485682080 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/13.dma_generic_smoke.3485682080 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 13.dma_generic_smoke.3485682080 -covoverwrite' seed=40932669636721420547069743072617208540470057685919059352258111451514274007456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40932669636721420547069743072617208540470057685919059352258111451514274007456 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"13.dma_memory_smoke.60837562730959282072032233874036429586916348638868726202587868233283357878361","seed":60837562730959282072032233874036429586916348638868726202587868233283357878361,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1732487257 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/13.dma_memory_smoke.1732487257 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 13.dma_memory_smoke.1732487257 -covoverwrite' seed=60837562730959282072032233874036429586916348638868726202587868233283357878361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60837562730959282072032233874036429586916348638868726202587868233283357878361 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"13.dma_handshake_smoke.105250051515151455821208807051341711863043447456276607010771554173298991695348","seed":105250051515151455821208807051341711863043447456276607010771554173298991695348,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2580809204 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/13.dma_handshake_smoke.2580809204 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 13.dma_handshake_smoke.2580809204 -covoverwrite' seed=105250051515151455821208807051341711863043447456276607010771554173298991695348 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105250051515151455821208807051341711863043447456276607010771554173298991695348 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"13.dma_short_transfer.21944742054715987275675337344685342472413540330848489317273629549718616444785","seed":21944742054715987275675337344685342472413540330848489317273629549718616444785,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3914895217 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/13.dma_short_transfer.3914895217 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 13.dma_short_transfer.3914895217 -covoverwrite' seed=21944742054715987275675337344685342472413540330848489317273629549718616444785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21944742054715987275675337344685342472413540330848489317273629549718616444785 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"13.dma_config_lock.87751743005058849102638898198083151121351421790340894304308839348525275713662","seed":87751743005058849102638898198083151121351421790340894304308839348525275713662,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=69111934 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/13.dma_config_lock.69111934 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 13.dma_config_lock.69111934 -covoverwrite' seed=87751743005058849102638898198083151121351421790340894304308839348525275713662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87751743005058849102638898198083151121351421790340894304308839348525275713662 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"13.dma_tl_errors.48491403052858616572684862912803312194432353587894836024006323169237568411513","seed":48491403052858616572684862912803312194432353587894836024006323169237568411513,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=384915321 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/13.dma_tl_errors.384915321 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.dma_tl_errors.384915321 -covoverwrite' seed=48491403052858616572684862912803312194432353587894836024006323169237568411513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48491403052858616572684862912803312194432353587894836024006323169237568411513 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"13.dma_tl_intg_err.60604156780669864929569918150299270065124707354585058949990201928318610686028","seed":60604156780669864929569918150299270065124707354585058949990201928318610686028,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=582598732 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/13.dma_tl_intg_err.582598732 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.dma_tl_intg_err.582598732 -covoverwrite' seed=60604156780669864929569918150299270065124707354585058949990201928318610686028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60604156780669864929569918150299270065124707354585058949990201928318610686028 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/13.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"14.dma_generic_smoke.72115816378070354269111079050737125931047949759349273995325979867195984219377","seed":72115816378070354269111079050737125931047949759349273995325979867195984219377,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1921420529 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/14.dma_generic_smoke.1921420529 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 14.dma_generic_smoke.1921420529 -covoverwrite' seed=72115816378070354269111079050737125931047949759349273995325979867195984219377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72115816378070354269111079050737125931047949759349273995325979867195984219377 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"14.dma_memory_smoke.101168374399947255542192025339708744390056449686713598638885494672258484348575","seed":101168374399947255542192025339708744390056449686713598638885494672258484348575,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2493982367 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/14.dma_memory_smoke.2493982367 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 14.dma_memory_smoke.2493982367 -covoverwrite' seed=101168374399947255542192025339708744390056449686713598638885494672258484348575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101168374399947255542192025339708744390056449686713598638885494672258484348575 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"14.dma_handshake_smoke.73558219843767929551947501873642075444391570538304830663081297412840635233312","seed":73558219843767929551947501873642075444391570538304830663081297412840635233312,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2729964576 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/14.dma_handshake_smoke.2729964576 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 14.dma_handshake_smoke.2729964576 -covoverwrite' seed=73558219843767929551947501873642075444391570538304830663081297412840635233312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73558219843767929551947501873642075444391570538304830663081297412840635233312 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"14.dma_short_transfer.32460168612409915741833191481441806625175533678825199148645355928029567075827","seed":32460168612409915741833191481441806625175533678825199148645355928029567075827,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4201072115 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/14.dma_short_transfer.4201072115 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 14.dma_short_transfer.4201072115 -covoverwrite' seed=32460168612409915741833191481441806625175533678825199148645355928029567075827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32460168612409915741833191481441806625175533678825199148645355928029567075827 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_config_lock","qual_name":"14.dma_config_lock.96562378328769233143614814903141772981884155701301864125882012161400426929603","seed":96562378328769233143614814903141772981884155701301864125882012161400426929603,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_config_lock/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_config_lock/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2199068099 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_config_lock_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/14.dma_config_lock.2199068099 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 14.dma_config_lock.2199068099 -covoverwrite' seed=96562378328769233143614814903141772981884155701301864125882012161400426929603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96562378328769233143614814903141772981884155701301864125882012161400426929603 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_config_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_config_lock_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"14.dma_tl_errors.24988523473212130395468864788542381338304828355986566734573329415367602982009","seed":24988523473212130395468864788542381338304828355986566734573329415367602982009,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1360776313 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/14.dma_tl_errors.1360776313 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.dma_tl_errors.1360776313 -covoverwrite' seed=24988523473212130395468864788542381338304828355986566734573329415367602982009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24988523473212130395468864788542381338304828355986566734573329415367602982009 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"14.dma_tl_intg_err.42176175893105647316764191942004445932164924395144881096362784859502436641328","seed":42176175893105647316764191942004445932164924395144881096362784859502436641328,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2713414192 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/14.dma_tl_intg_err.2713414192 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.dma_tl_intg_err.2713414192 -covoverwrite' seed=42176175893105647316764191942004445932164924395144881096362784859502436641328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42176175893105647316764191942004445932164924395144881096362784859502436641328 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/14.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"15.dma_generic_smoke.108907266328777885730418467143965118293869849421133366793284304354924978929436","seed":108907266328777885730418467143965118293869849421133366793284304354924978929436,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1536327452 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/15.dma_generic_smoke.1536327452 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 15.dma_generic_smoke.1536327452 -covoverwrite' seed=108907266328777885730418467143965118293869849421133366793284304354924978929436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108907266328777885730418467143965118293869849421133366793284304354924978929436 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"15.dma_memory_smoke.112091497499154883391067814808884409496179621914997707240843035486409809004295","seed":112091497499154883391067814808884409496179621914997707240843035486409809004295,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=978388743 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/15.dma_memory_smoke.978388743 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 15.dma_memory_smoke.978388743 -covoverwrite' seed=112091497499154883391067814808884409496179621914997707240843035486409809004295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112091497499154883391067814808884409496179621914997707240843035486409809004295 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"15.dma_handshake_smoke.4575444866004928393459001854908352623323687820323885498700011091697188196517","seed":4575444866004928393459001854908352623323687820323885498700011091697188196517,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=344707237 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/15.dma_handshake_smoke.344707237 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 15.dma_handshake_smoke.344707237 -covoverwrite' seed=4575444866004928393459001854908352623323687820323885498700011091697188196517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4575444866004928393459001854908352623323687820323885498700011091697188196517 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"15.dma_short_transfer.4507593295128294328477396877506052923830453136314274297501727379907856704589","seed":4507593295128294328477396877506052923830453136314274297501727379907856704589,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3772916813 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/15.dma_short_transfer.3772916813 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 15.dma_short_transfer.3772916813 -covoverwrite' seed=4507593295128294328477396877506052923830453136314274297501727379907856704589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4507593295128294328477396877506052923830453136314274297501727379907856704589 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"15.dma_tl_errors.30537253749206060252377329424753572527571280896011920872736147174871529762083","seed":30537253749206060252377329424753572527571280896011920872736147174871529762083,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=837102883 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/15.dma_tl_errors.837102883 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.dma_tl_errors.837102883 -covoverwrite' seed=30537253749206060252377329424753572527571280896011920872736147174871529762083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30537253749206060252377329424753572527571280896011920872736147174871529762083 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"15.dma_tl_intg_err.16134041986262874859984451024768340044166398855703125250086023438499311004697","seed":16134041986262874859984451024768340044166398855703125250086023438499311004697,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4200082457 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/15.dma_tl_intg_err.4200082457 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.dma_tl_intg_err.4200082457 -covoverwrite' seed=16134041986262874859984451024768340044166398855703125250086023438499311004697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16134041986262874859984451024768340044166398855703125250086023438499311004697 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/15.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"16.dma_generic_smoke.78474506297307394835688410398189933098526666650947602167767327739973376635268","seed":78474506297307394835688410398189933098526666650947602167767327739973376635268,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=80441732 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/16.dma_generic_smoke.80441732 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 16.dma_generic_smoke.80441732 -covoverwrite' seed=78474506297307394835688410398189933098526666650947602167767327739973376635268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78474506297307394835688410398189933098526666650947602167767327739973376635268 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"16.dma_memory_smoke.69305360403365504937056824914427858414042213881669094865916161629519675541786","seed":69305360403365504937056824914427858414042213881669094865916161629519675541786,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3957999898 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/16.dma_memory_smoke.3957999898 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 16.dma_memory_smoke.3957999898 -covoverwrite' seed=69305360403365504937056824914427858414042213881669094865916161629519675541786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69305360403365504937056824914427858414042213881669094865916161629519675541786 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"16.dma_handshake_smoke.18053540733114241560664370033944827617219250120231786486073475669787699160914","seed":18053540733114241560664370033944827617219250120231786486073475669787699160914,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3749029714 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/16.dma_handshake_smoke.3749029714 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 16.dma_handshake_smoke.3749029714 -covoverwrite' seed=18053540733114241560664370033944827617219250120231786486073475669787699160914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18053540733114241560664370033944827617219250120231786486073475669787699160914 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"16.dma_short_transfer.43632808118411957315232891863741179847099149778556611069593252311246662282510","seed":43632808118411957315232891863741179847099149778556611069593252311246662282510,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1491610894 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/16.dma_short_transfer.1491610894 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 16.dma_short_transfer.1491610894 -covoverwrite' seed=43632808118411957315232891863741179847099149778556611069593252311246662282510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43632808118411957315232891863741179847099149778556611069593252311246662282510 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"16.dma_tl_errors.108833485885969439949967444444959832621554722273065046102515172052886706248820","seed":108833485885969439949967444444959832621554722273065046102515172052886706248820,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3802193012 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/16.dma_tl_errors.3802193012 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.dma_tl_errors.3802193012 -covoverwrite' seed=108833485885969439949967444444959832621554722273065046102515172052886706248820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108833485885969439949967444444959832621554722273065046102515172052886706248820 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"16.dma_tl_intg_err.30471403421494448130651521720798483986024999194892571993529943369620734974698","seed":30471403421494448130651521720798483986024999194892571993529943369620734974698,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1796315882 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/16.dma_tl_intg_err.1796315882 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.dma_tl_intg_err.1796315882 -covoverwrite' seed=30471403421494448130651521720798483986024999194892571993529943369620734974698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30471403421494448130651521720798483986024999194892571993529943369620734974698 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/16.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"17.dma_generic_smoke.65108075035368009257998996969341659072939178195031067861164368225389887673496","seed":65108075035368009257998996969341659072939178195031067861164368225389887673496,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2159596696 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/17.dma_generic_smoke.2159596696 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 17.dma_generic_smoke.2159596696 -covoverwrite' seed=65108075035368009257998996969341659072939178195031067861164368225389887673496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65108075035368009257998996969341659072939178195031067861164368225389887673496 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"17.dma_memory_smoke.46232786790097175236055543929251244661385741963797353013548707546376806476798","seed":46232786790097175236055543929251244661385741963797353013548707546376806476798,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4242156542 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/17.dma_memory_smoke.4242156542 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 17.dma_memory_smoke.4242156542 -covoverwrite' seed=46232786790097175236055543929251244661385741963797353013548707546376806476798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46232786790097175236055543929251244661385741963797353013548707546376806476798 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"17.dma_handshake_smoke.52240647397887920549301492448070916572210818156548843339381976826071010869439","seed":52240647397887920549301492448070916572210818156548843339381976826071010869439,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2460319935 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/17.dma_handshake_smoke.2460319935 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 17.dma_handshake_smoke.2460319935 -covoverwrite' seed=52240647397887920549301492448070916572210818156548843339381976826071010869439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52240647397887920549301492448070916572210818156548843339381976826071010869439 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"17.dma_short_transfer.98552255556687101699829548728535164050885884728892178190352777561098928529808","seed":98552255556687101699829548728535164050885884728892178190352777561098928529808,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3675005328 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/17.dma_short_transfer.3675005328 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 17.dma_short_transfer.3675005328 -covoverwrite' seed=98552255556687101699829548728535164050885884728892178190352777561098928529808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98552255556687101699829548728535164050885884728892178190352777561098928529808 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"17.dma_tl_errors.69401477771217323309590784870436788384242530595117666374954673178281102831005","seed":69401477771217323309590784870436788384242530595117666374954673178281102831005,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=638348701 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/17.dma_tl_errors.638348701 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.dma_tl_errors.638348701 -covoverwrite' seed=69401477771217323309590784870436788384242530595117666374954673178281102831005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69401477771217323309590784870436788384242530595117666374954673178281102831005 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"17.dma_tl_intg_err.48046342523546027591601357149352285193830879403817792854254011889983906085549","seed":48046342523546027591601357149352285193830879403817792854254011889983906085549,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2584967853 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/17.dma_tl_intg_err.2584967853 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.dma_tl_intg_err.2584967853 -covoverwrite' seed=48046342523546027591601357149352285193830879403817792854254011889983906085549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48046342523546027591601357149352285193830879403817792854254011889983906085549 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/17.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"18.dma_generic_smoke.84881777139559570147062242438943557444263120785967395943533138195166433505856","seed":84881777139559570147062242438943557444263120785967395943533138195166433505856,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=579203648 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/18.dma_generic_smoke.579203648 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 18.dma_generic_smoke.579203648 -covoverwrite' seed=84881777139559570147062242438943557444263120785967395943533138195166433505856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84881777139559570147062242438943557444263120785967395943533138195166433505856 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"18.dma_memory_smoke.95303097348429272769359843607756280438278320090686950724941700215481014032298","seed":95303097348429272769359843607756280438278320090686950724941700215481014032298,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2972063658 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/18.dma_memory_smoke.2972063658 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 18.dma_memory_smoke.2972063658 -covoverwrite' seed=95303097348429272769359843607756280438278320090686950724941700215481014032298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95303097348429272769359843607756280438278320090686950724941700215481014032298 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"18.dma_handshake_smoke.2573716192414688422313384693467550653778957096538597362957721590822955332451","seed":2573716192414688422313384693467550653778957096538597362957721590822955332451,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1468216163 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/18.dma_handshake_smoke.1468216163 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 18.dma_handshake_smoke.1468216163 -covoverwrite' seed=2573716192414688422313384693467550653778957096538597362957721590822955332451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2573716192414688422313384693467550653778957096538597362957721590822955332451 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"18.dma_short_transfer.78459074992076052095179557124888222051616095280306466922672369407419683295363","seed":78459074992076052095179557124888222051616095280306466922672369407419683295363,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3764244611 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/18.dma_short_transfer.3764244611 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 18.dma_short_transfer.3764244611 -covoverwrite' seed=78459074992076052095179557124888222051616095280306466922672369407419683295363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78459074992076052095179557124888222051616095280306466922672369407419683295363 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"18.dma_tl_errors.55782688091246725382906064379052888662948566801469457287197811492081006798981","seed":55782688091246725382906064379052888662948566801469457287197811492081006798981,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2697455749 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/18.dma_tl_errors.2697455749 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.dma_tl_errors.2697455749 -covoverwrite' seed=55782688091246725382906064379052888662948566801469457287197811492081006798981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55782688091246725382906064379052888662948566801469457287197811492081006798981 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"18.dma_tl_intg_err.56896914306971963323174901614917675530715888651002521263913135409842522282636","seed":56896914306971963323174901614917675530715888651002521263913135409842522282636,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3047545484 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/18.dma_tl_intg_err.3047545484 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.dma_tl_intg_err.3047545484 -covoverwrite' seed=56896914306971963323174901614917675530715888651002521263913135409842522282636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56896914306971963323174901614917675530715888651002521263913135409842522282636 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/18.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"19.dma_generic_smoke.98717987026659624782205743575474710866695770340518083937214840917332335336456","seed":98717987026659624782205743575474710866695770340518083937214840917332335336456,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=663297032 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/19.dma_generic_smoke.663297032 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 19.dma_generic_smoke.663297032 -covoverwrite' seed=98717987026659624782205743575474710866695770340518083937214840917332335336456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98717987026659624782205743575474710866695770340518083937214840917332335336456 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"19.dma_memory_smoke.87296370311535458535901792318738162274058375478305515426354716909368644621951","seed":87296370311535458535901792318738162274058375478305515426354716909368644621951,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2008962687 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/19.dma_memory_smoke.2008962687 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 19.dma_memory_smoke.2008962687 -covoverwrite' seed=87296370311535458535901792318738162274058375478305515426354716909368644621951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87296370311535458535901792318738162274058375478305515426354716909368644621951 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"19.dma_handshake_smoke.72383832025326623592667670425692519340614858415992092488713533132453994599998","seed":72383832025326623592667670425692519340614858415992092488713533132453994599998,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2635634238 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/19.dma_handshake_smoke.2635634238 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 19.dma_handshake_smoke.2635634238 -covoverwrite' seed=72383832025326623592667670425692519340614858415992092488713533132453994599998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72383832025326623592667670425692519340614858415992092488713533132453994599998 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"19.dma_short_transfer.1548256363015427730777586787096127934586167407800443943607674479396659546059","seed":1548256363015427730777586787096127934586167407800443943607674479396659546059,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1588742091 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/19.dma_short_transfer.1588742091 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 19.dma_short_transfer.1588742091 -covoverwrite' seed=1548256363015427730777586787096127934586167407800443943607674479396659546059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1548256363015427730777586787096127934586167407800443943607674479396659546059 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"19.dma_tl_errors.39315695635542171570563671843719594937171325745133681891601886642699183165754","seed":39315695635542171570563671843719594937171325745133681891601886642699183165754,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=958763322 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/19.dma_tl_errors.958763322 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.dma_tl_errors.958763322 -covoverwrite' seed=39315695635542171570563671843719594937171325745133681891601886642699183165754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39315695635542171570563671843719594937171325745133681891601886642699183165754 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"19.dma_tl_intg_err.84481795733208063395063606453378047149970126407675482132018287853267366893164","seed":84481795733208063395063606453378047149970126407675482132018287853267366893164,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2925450860 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/19.dma_tl_intg_err.2925450860 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.dma_tl_intg_err.2925450860 -covoverwrite' seed=84481795733208063395063606453378047149970126407675482132018287853267366893164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84481795733208063395063606453378047149970126407675482132018287853267366893164 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/19.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"20.dma_generic_smoke.37760418290634721076488434044912009071639731600579520100498539046049300270868","seed":37760418290634721076488434044912009071639731600579520100498539046049300270868,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4112961300 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/20.dma_generic_smoke.4112961300 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 20.dma_generic_smoke.4112961300 -covoverwrite' seed=37760418290634721076488434044912009071639731600579520100498539046049300270868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37760418290634721076488434044912009071639731600579520100498539046049300270868 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"20.dma_memory_smoke.65062574436454910026258121954884581612975137412659440975002439469365623574959","seed":65062574436454910026258121954884581612975137412659440975002439469365623574959,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1708183983 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/20.dma_memory_smoke.1708183983 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 20.dma_memory_smoke.1708183983 -covoverwrite' seed=65062574436454910026258121954884581612975137412659440975002439469365623574959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65062574436454910026258121954884581612975137412659440975002439469365623574959 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"20.dma_handshake_smoke.65038504981870576568830065648983503215109607801454610457505888352748678340506","seed":65038504981870576568830065648983503215109607801454610457505888352748678340506,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=907730842 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/20.dma_handshake_smoke.907730842 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 20.dma_handshake_smoke.907730842 -covoverwrite' seed=65038504981870576568830065648983503215109607801454610457505888352748678340506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65038504981870576568830065648983503215109607801454610457505888352748678340506 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"20.dma_short_transfer.75264852055214388077097071877264060635188350528025323148615362725031237478959","seed":75264852055214388077097071877264060635188350528025323148615362725031237478959,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=516516399 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/20.dma_short_transfer.516516399 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 20.dma_short_transfer.516516399 -covoverwrite' seed=75264852055214388077097071877264060635188350528025323148615362725031237478959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75264852055214388077097071877264060635188350528025323148615362725031237478959 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"20.dma_tl_errors.62896451613105198091116488716288368524736141280154622132778415109912077121431","seed":62896451613105198091116488716288368524736141280154622132778415109912077121431,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1115797399 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/20.dma_tl_errors.1115797399 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.dma_tl_errors.1115797399 -covoverwrite' seed=62896451613105198091116488716288368524736141280154622132778415109912077121431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62896451613105198091116488716288368524736141280154622132778415109912077121431 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"20.dma_tl_intg_err.102695193214579241933590965595167391095499457593214268455162150040523945223732","seed":102695193214579241933590965595167391095499457593214268455162150040523945223732,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=458434100 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/20.dma_tl_intg_err.458434100 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.dma_tl_intg_err.458434100 -covoverwrite' seed=102695193214579241933590965595167391095499457593214268455162150040523945223732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102695193214579241933590965595167391095499457593214268455162150040523945223732 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/20.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"21.dma_generic_smoke.53143771746672461954515729055320093968842811834921012278594579367270684732194","seed":53143771746672461954515729055320093968842811834921012278594579367270684732194,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1735306018 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/21.dma_generic_smoke.1735306018 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 21.dma_generic_smoke.1735306018 -covoverwrite' seed=53143771746672461954515729055320093968842811834921012278594579367270684732194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53143771746672461954515729055320093968842811834921012278594579367270684732194 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"21.dma_memory_smoke.52229999985736067842703444117023879735794419554263508166318212847109750004641","seed":52229999985736067842703444117023879735794419554263508166318212847109750004641,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=773200801 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/21.dma_memory_smoke.773200801 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 21.dma_memory_smoke.773200801 -covoverwrite' seed=52229999985736067842703444117023879735794419554263508166318212847109750004641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52229999985736067842703444117023879735794419554263508166318212847109750004641 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"21.dma_handshake_smoke.47231980475532226700495848685664391145631987466859622811676556114852269787408","seed":47231980475532226700495848685664391145631987466859622811676556114852269787408,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1858865424 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/21.dma_handshake_smoke.1858865424 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 21.dma_handshake_smoke.1858865424 -covoverwrite' seed=47231980475532226700495848685664391145631987466859622811676556114852269787408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47231980475532226700495848685664391145631987466859622811676556114852269787408 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"21.dma_short_transfer.111237744646896455799411332815975415096347965497500672672541258623837516774708","seed":111237744646896455799411332815975415096347965497500672672541258623837516774708,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2952183092 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/21.dma_short_transfer.2952183092 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 21.dma_short_transfer.2952183092 -covoverwrite' seed=111237744646896455799411332815975415096347965497500672672541258623837516774708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111237744646896455799411332815975415096347965497500672672541258623837516774708 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"21.dma_tl_errors.27036325840712994699728146639783028288914893972620949127079744060513181889476","seed":27036325840712994699728146639783028288914893972620949127079744060513181889476,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=30798788 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/21.dma_tl_errors.30798788 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.dma_tl_errors.30798788 -covoverwrite' seed=27036325840712994699728146639783028288914893972620949127079744060513181889476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27036325840712994699728146639783028288914893972620949127079744060513181889476 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"21.dma_tl_intg_err.10057295823869031031981400713554146807685111471500885645802251288184026985828","seed":10057295823869031031981400713554146807685111471500885645802251288184026985828,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1721136484 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/21.dma_tl_intg_err.1721136484 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.dma_tl_intg_err.1721136484 -covoverwrite' seed=10057295823869031031981400713554146807685111471500885645802251288184026985828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10057295823869031031981400713554146807685111471500885645802251288184026985828 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/21.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"22.dma_generic_smoke.11388450466315280934648383742924729650062332555377453997431625036836494028122","seed":11388450466315280934648383742924729650062332555377453997431625036836494028122,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=373206362 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/22.dma_generic_smoke.373206362 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 22.dma_generic_smoke.373206362 -covoverwrite' seed=11388450466315280934648383742924729650062332555377453997431625036836494028122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11388450466315280934648383742924729650062332555377453997431625036836494028122 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"22.dma_memory_smoke.107421556674370613909666376112834349220250377041970256298800816483348600341895","seed":107421556674370613909666376112834349220250377041970256298800816483348600341895,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=622347655 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/22.dma_memory_smoke.622347655 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 22.dma_memory_smoke.622347655 -covoverwrite' seed=107421556674370613909666376112834349220250377041970256298800816483348600341895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107421556674370613909666376112834349220250377041970256298800816483348600341895 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"22.dma_handshake_smoke.33064223738840041722425256356076802852855073001397131176039415311355182740093","seed":33064223738840041722425256356076802852855073001397131176039415311355182740093,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=504787581 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/22.dma_handshake_smoke.504787581 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 22.dma_handshake_smoke.504787581 -covoverwrite' seed=33064223738840041722425256356076802852855073001397131176039415311355182740093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33064223738840041722425256356076802852855073001397131176039415311355182740093 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"22.dma_short_transfer.76380822802516897007005386320002841757542985665008895390269114947432989995423","seed":76380822802516897007005386320002841757542985665008895390269114947432989995423,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=973746591 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/22.dma_short_transfer.973746591 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 22.dma_short_transfer.973746591 -covoverwrite' seed=76380822802516897007005386320002841757542985665008895390269114947432989995423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76380822802516897007005386320002841757542985665008895390269114947432989995423 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"22.dma_tl_errors.19931256221176934842201036094320406697520238498417732831172355659393666114652","seed":19931256221176934842201036094320406697520238498417732831172355659393666114652,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1896866908 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/22.dma_tl_errors.1896866908 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.dma_tl_errors.1896866908 -covoverwrite' seed=19931256221176934842201036094320406697520238498417732831172355659393666114652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19931256221176934842201036094320406697520238498417732831172355659393666114652 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"22.dma_tl_intg_err.80265160243227279279440843183785875185896974386571813207257694190656777214483","seed":80265160243227279279440843183785875185896974386571813207257694190656777214483,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3277707795 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/22.dma_tl_intg_err.3277707795 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.dma_tl_intg_err.3277707795 -covoverwrite' seed=80265160243227279279440843183785875185896974386571813207257694190656777214483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80265160243227279279440843183785875185896974386571813207257694190656777214483 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/22.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"23.dma_generic_smoke.115655654441231749038140731890275165880326672052724779759118790353644159628190","seed":115655654441231749038140731890275165880326672052724779759118790353644159628190,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4002018206 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/23.dma_generic_smoke.4002018206 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 23.dma_generic_smoke.4002018206 -covoverwrite' seed=115655654441231749038140731890275165880326672052724779759118790353644159628190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115655654441231749038140731890275165880326672052724779759118790353644159628190 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"23.dma_memory_smoke.105826534719260700503521639229981374565859962607429806334090536140021080692848","seed":105826534719260700503521639229981374565859962607429806334090536140021080692848,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3997866096 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/23.dma_memory_smoke.3997866096 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 23.dma_memory_smoke.3997866096 -covoverwrite' seed=105826534719260700503521639229981374565859962607429806334090536140021080692848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105826534719260700503521639229981374565859962607429806334090536140021080692848 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"23.dma_handshake_smoke.68071810377410554639116103880130657710813781490826321434509434313296413113717","seed":68071810377410554639116103880130657710813781490826321434509434313296413113717,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2281880949 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/23.dma_handshake_smoke.2281880949 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 23.dma_handshake_smoke.2281880949 -covoverwrite' seed=68071810377410554639116103880130657710813781490826321434509434313296413113717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68071810377410554639116103880130657710813781490826321434509434313296413113717 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"23.dma_short_transfer.94698049863183505823688160649495490244105694758212612231315953154542653197086","seed":94698049863183505823688160649495490244105694758212612231315953154542653197086,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=156289822 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/23.dma_short_transfer.156289822 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 23.dma_short_transfer.156289822 -covoverwrite' seed=94698049863183505823688160649495490244105694758212612231315953154542653197086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94698049863183505823688160649495490244105694758212612231315953154542653197086 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"23.dma_tl_errors.23266878657302572102805140942739474822751441434715778675182605911572416408331","seed":23266878657302572102805140942739474822751441434715778675182605911572416408331,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=707111691 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/23.dma_tl_errors.707111691 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.dma_tl_errors.707111691 -covoverwrite' seed=23266878657302572102805140942739474822751441434715778675182605911572416408331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23266878657302572102805140942739474822751441434715778675182605911572416408331 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"23.dma_tl_intg_err.109951468697067444216552305887921581577319301776585155876256583450984823637464","seed":109951468697067444216552305887921581577319301776585155876256583450984823637464,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=683918808 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/23.dma_tl_intg_err.683918808 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.dma_tl_intg_err.683918808 -covoverwrite' seed=109951468697067444216552305887921581577319301776585155876256583450984823637464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109951468697067444216552305887921581577319301776585155876256583450984823637464 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/23.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"24.dma_generic_smoke.99503974460159248022725981305315187782322303368714643940929158769742852365732","seed":99503974460159248022725981305315187782322303368714643940929158769742852365732,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3291454884 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/24.dma_generic_smoke.3291454884 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 24.dma_generic_smoke.3291454884 -covoverwrite' seed=99503974460159248022725981305315187782322303368714643940929158769742852365732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99503974460159248022725981305315187782322303368714643940929158769742852365732 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_memory_smoke","qual_name":"24.dma_memory_smoke.29407933392771094079387902413742003844294943074277144329001792308894552138685","seed":29407933392771094079387902413742003844294943074277144329001792308894552138685,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_memory_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_memory_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3207439293 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_memory_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/24.dma_memory_smoke.3207439293 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 24.dma_memory_smoke.3207439293 -covoverwrite' seed=29407933392771094079387902413742003844294943074277144329001792308894552138685 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29407933392771094079387902413742003844294943074277144329001792308894552138685 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_memory_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_memory_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_handshake_smoke","qual_name":"24.dma_handshake_smoke.15147061314590835247080739036981862361999509690783697436702609202351722186821","seed":15147061314590835247080739036981862361999509690783697436702609202351722186821,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_handshake_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_handshake_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1215547461 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_handshake_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/24.dma_handshake_smoke.1215547461 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 24.dma_handshake_smoke.1215547461 -covoverwrite' seed=15147061314590835247080739036981862361999509690783697436702609202351722186821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15147061314590835247080739036981862361999509690783697436702609202351722186821 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_handshake_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_handshake_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_short_transfer","qual_name":"24.dma_short_transfer.89260340445980586039215246870315826605206004683061451868773797102875406045331","seed":89260340445980586039215246870315826605206004683061451868773797102875406045331,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_short_transfer/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_short_transfer/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2088308883 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_short_transfer_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/24.dma_short_transfer.2088308883 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 24.dma_short_transfer.2088308883 -covoverwrite' seed=89260340445980586039215246870315826605206004683061451868773797102875406045331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89260340445980586039215246870315826605206004683061451868773797102875406045331 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_short_transfer/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_short_transfer_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_errors","qual_name":"24.dma_tl_errors.26719304375167191507215387064664128398595667034914348218142131131245940245511","seed":26719304375167191507215387064664128398595667034914348218142131131245940245511,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2129724423 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/24.dma_tl_errors.2129724423 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.dma_tl_errors.2129724423 -covoverwrite' seed=26719304375167191507215387064664128398595667034914348218142131131245940245511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26719304375167191507215387064664128398595667034914348218142131131245940245511 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_tl_intg_err","qual_name":"24.dma_tl_intg_err.113147969725403489525698841776335205194942031566539616471495005869104077808401","seed":113147969725403489525698841776335205194942031566539616471495005869104077808401,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3933283089 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/cover_reg_top/24.dma_tl_intg_err.3933283089 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.dma_tl_intg_err.3933283089 -covoverwrite' seed=113147969725403489525698841776335205194942031566539616471495005869104077808401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113147969725403489525698841776335205194942031566539616471495005869104077808401 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/24.dma_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"25.dma_generic_smoke.6474249855144350734698638776808442747521104036770985281588126069245427673973","seed":6474249855144350734698638776808442747521104036770985281588126069245427673973,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/25.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/25.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2938202997 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/25.dma_generic_smoke.2938202997 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 25.dma_generic_smoke.2938202997 -covoverwrite' seed=6474249855144350734698638776808442747521104036770985281588126069245427673973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6474249855144350734698638776808442747521104036770985281588126069245427673973 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/25.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"26.dma_generic_smoke.37569120528535427318020061368254564260023295610925249306932093288602224303602","seed":37569120528535427318020061368254564260023295610925249306932093288602224303602,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/26.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/26.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=830217714 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/26.dma_generic_smoke.830217714 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 26.dma_generic_smoke.830217714 -covoverwrite' seed=37569120528535427318020061368254564260023295610925249306932093288602224303602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37569120528535427318020061368254564260023295610925249306932093288602224303602 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/26.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"27.dma_generic_smoke.31476192028569483676683265418155170344175502328035029540388249256315724889294","seed":31476192028569483676683265418155170344175502328035029540388249256315724889294,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/27.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/27.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2933783758 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/27.dma_generic_smoke.2933783758 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 27.dma_generic_smoke.2933783758 -covoverwrite' seed=31476192028569483676683265418155170344175502328035029540388249256315724889294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31476192028569483676683265418155170344175502328035029540388249256315724889294 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/27.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"28.dma_generic_smoke.74372971915047249288405902441751438189250230851124223512269246395350897500631","seed":74372971915047249288405902441751438189250230851124223512269246395350897500631,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/28.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/28.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2812387799 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/28.dma_generic_smoke.2812387799 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 28.dma_generic_smoke.2812387799 -covoverwrite' seed=74372971915047249288405902441751438189250230851124223512269246395350897500631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74372971915047249288405902441751438189250230851124223512269246395350897500631 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/28.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"29.dma_generic_smoke.15661934764532551287453568837785819994297647986365668619576083126537275275931","seed":15661934764532551287453568837785819994297647986365668619576083126537275275931,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/29.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/29.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2140371611 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/29.dma_generic_smoke.2140371611 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 29.dma_generic_smoke.2140371611 -covoverwrite' seed=15661934764532551287453568837785819994297647986365668619576083126537275275931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15661934764532551287453568837785819994297647986365668619576083126537275275931 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/29.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"30.dma_generic_smoke.86852044911103092007792787740303744467720498258802947660200503650020172344073","seed":86852044911103092007792787740303744467720498258802947660200503650020172344073,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/30.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/30.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4246579977 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/30.dma_generic_smoke.4246579977 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 30.dma_generic_smoke.4246579977 -covoverwrite' seed=86852044911103092007792787740303744467720498258802947660200503650020172344073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86852044911103092007792787740303744467720498258802947660200503650020172344073 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/30.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"31.dma_generic_smoke.95843150852600026399070255261589870765958829862689794112925865636142495730297","seed":95843150852600026399070255261589870765958829862689794112925865636142495730297,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/31.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/31.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3062270585 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/31.dma_generic_smoke.3062270585 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 31.dma_generic_smoke.3062270585 -covoverwrite' seed=95843150852600026399070255261589870765958829862689794112925865636142495730297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95843150852600026399070255261589870765958829862689794112925865636142495730297 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/31.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"32.dma_generic_smoke.35852471689743693040966709483051129052524337599218133786295600178400434107000","seed":35852471689743693040966709483051129052524337599218133786295600178400434107000,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/32.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/32.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2822287992 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/32.dma_generic_smoke.2822287992 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 32.dma_generic_smoke.2822287992 -covoverwrite' seed=35852471689743693040966709483051129052524337599218133786295600178400434107000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35852471689743693040966709483051129052524337599218133786295600178400434107000 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/32.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"33.dma_generic_smoke.104354496015572527866157788390843127429550906207607631089302745475344689541908","seed":104354496015572527866157788390843127429550906207607631089302745475344689541908,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/33.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/33.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3785372436 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/33.dma_generic_smoke.3785372436 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 33.dma_generic_smoke.3785372436 -covoverwrite' seed=104354496015572527866157788390843127429550906207607631089302745475344689541908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104354496015572527866157788390843127429550906207607631089302745475344689541908 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/33.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"34.dma_generic_smoke.106201000921785072778512635651519174168604328668847099422615456798965207631098","seed":106201000921785072778512635651519174168604328668847099422615456798965207631098,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/34.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/34.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=250840314 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/34.dma_generic_smoke.250840314 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 34.dma_generic_smoke.250840314 -covoverwrite' seed=106201000921785072778512635651519174168604328668847099422615456798965207631098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106201000921785072778512635651519174168604328668847099422615456798965207631098 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/34.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"35.dma_generic_smoke.61987185462686154972184213155018733695154313541786477455913336596742802962363","seed":61987185462686154972184213155018733695154313541786477455913336596742802962363,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/35.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/35.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2119628731 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/35.dma_generic_smoke.2119628731 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 35.dma_generic_smoke.2119628731 -covoverwrite' seed=61987185462686154972184213155018733695154313541786477455913336596742802962363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61987185462686154972184213155018733695154313541786477455913336596742802962363 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/35.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"36.dma_generic_smoke.67238175836374262932294409056981710372749688536234272737496113602622594483706","seed":67238175836374262932294409056981710372749688536234272737496113602622594483706,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/36.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/36.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=430704122 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/36.dma_generic_smoke.430704122 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 36.dma_generic_smoke.430704122 -covoverwrite' seed=67238175836374262932294409056981710372749688536234272737496113602622594483706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67238175836374262932294409056981710372749688536234272737496113602622594483706 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/36.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"37.dma_generic_smoke.45990631053757538295259028910242593394568014910201349756200661790860367040099","seed":45990631053757538295259028910242593394568014910201349756200661790860367040099,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/37.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/37.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1466371683 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/37.dma_generic_smoke.1466371683 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 37.dma_generic_smoke.1466371683 -covoverwrite' seed=45990631053757538295259028910242593394568014910201349756200661790860367040099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45990631053757538295259028910242593394568014910201349756200661790860367040099 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/37.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"38.dma_generic_smoke.11570912545744518137679632485638259146711077641153361468357095366793397132857","seed":11570912545744518137679632485638259146711077641153361468357095366793397132857,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/38.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/38.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1069669945 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/38.dma_generic_smoke.1069669945 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 38.dma_generic_smoke.1069669945 -covoverwrite' seed=11570912545744518137679632485638259146711077641153361468357095366793397132857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11570912545744518137679632485638259146711077641153361468357095366793397132857 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/38.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"39.dma_generic_smoke.82433858757096304031732528798386734600267660708423977395360211126277376801488","seed":82433858757096304031732528798386734600267660708423977395360211126277376801488,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/39.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/39.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3159063248 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/39.dma_generic_smoke.3159063248 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 39.dma_generic_smoke.3159063248 -covoverwrite' seed=82433858757096304031732528798386734600267660708423977395360211126277376801488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82433858757096304031732528798386734600267660708423977395360211126277376801488 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/39.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"40.dma_generic_smoke.57874081232307374337971427638590933165595708598967657048201056988491597274533","seed":57874081232307374337971427638590933165595708598967657048201056988491597274533,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/40.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/40.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=1651826085 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/40.dma_generic_smoke.1651826085 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 40.dma_generic_smoke.1651826085 -covoverwrite' seed=57874081232307374337971427638590933165595708598967657048201056988491597274533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57874081232307374337971427638590933165595708598967657048201056988491597274533 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/40.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"41.dma_generic_smoke.23632319905332194193140359048073777999495180788241837326134096504758576289004","seed":23632319905332194193140359048073777999495180788241837326134096504758576289004,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/41.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/41.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=4180350188 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/41.dma_generic_smoke.4180350188 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 41.dma_generic_smoke.4180350188 -covoverwrite' seed=23632319905332194193140359048073777999495180788241837326134096504758576289004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23632319905332194193140359048073777999495180788241837326134096504758576289004 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/41.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"42.dma_generic_smoke.66378768181517306027168621873532445827685163158617004466724285490678321998421","seed":66378768181517306027168621873532445827685163158617004466724285490678321998421,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/42.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/42.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=908159573 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/42.dma_generic_smoke.908159573 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 42.dma_generic_smoke.908159573 -covoverwrite' seed=66378768181517306027168621873532445827685163158617004466724285490678321998421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66378768181517306027168621873532445827685163158617004466724285490678321998421 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/42.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"43.dma_generic_smoke.25815565806388394602264052906415706395272736863820166201963552740636365510699","seed":25815565806388394602264052906415706395272736863820166201963552740636365510699,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/43.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/43.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3796457515 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/43.dma_generic_smoke.3796457515 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 43.dma_generic_smoke.3796457515 -covoverwrite' seed=25815565806388394602264052906415706395272736863820166201963552740636365510699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25815565806388394602264052906415706395272736863820166201963552740636365510699 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/43.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"44.dma_generic_smoke.23102674443690929006728421907240794408261197811346486076613866401565574113201","seed":23102674443690929006728421907240794408261197811346486076613866401565574113201,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/44.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/44.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=215426993 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/44.dma_generic_smoke.215426993 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 44.dma_generic_smoke.215426993 -covoverwrite' seed=23102674443690929006728421907240794408261197811346486076613866401565574113201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23102674443690929006728421907240794408261197811346486076613866401565574113201 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/44.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"45.dma_generic_smoke.56057954733914867097361308610425272776173499591253918945361973433184195432411","seed":56057954733914867097361308610425272776173499591253918945361973433184195432411,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/45.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/45.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=187682779 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/45.dma_generic_smoke.187682779 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 45.dma_generic_smoke.187682779 -covoverwrite' seed=56057954733914867097361308610425272776173499591253918945361973433184195432411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56057954733914867097361308610425272776173499591253918945361973433184195432411 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/45.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"46.dma_generic_smoke.7686121428755976101004640761251618926952023635741041676602298494461612920623","seed":7686121428755976101004640761251618926952023635741041676602298494461612920623,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/46.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/46.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=813961007 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/46.dma_generic_smoke.813961007 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 46.dma_generic_smoke.813961007 -covoverwrite' seed=7686121428755976101004640761251618926952023635741041676602298494461612920623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7686121428755976101004640761251618926952023635741041676602298494461612920623 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/46.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"47.dma_generic_smoke.35929607604578609728625257397127013094627371012751683765301567636675679862150","seed":35929607604578609728625257397127013094627371012751683765301567636675679862150,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/47.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/47.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3340090758 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/47.dma_generic_smoke.3340090758 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 47.dma_generic_smoke.3340090758 -covoverwrite' seed=35929607604578609728625257397127013094627371012751683765301567636675679862150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35929607604578609728625257397127013094627371012751683765301567636675679862150 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/47.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"48.dma_generic_smoke.91108206975001275114778301413747649179460373512916279517324234503448494595881","seed":91108206975001275114778301413747649179460373512916279517324234503448494595881,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/48.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/48.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=3838828329 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/48.dma_generic_smoke.3838828329 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 48.dma_generic_smoke.3838828329 -covoverwrite' seed=91108206975001275114778301413747649179460373512916279517324234503448494595881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91108206975001275114778301413747649179460373512916279517324234503448494595881 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/48.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"dma_generic_smoke","qual_name":"49.dma_generic_smoke.9933650608018824013729952507217073876476348115212212033152200381885376192261","seed":9933650608018824013729952507217073876476348115212212033152200381885376192261,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/49.dma_generic_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/dma-sim-xcelium/49.dma_generic_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/dma-sim-xcelium/default/xcelium.d -r tb +SVSEED=2739232517 +UVM_TESTNAME=dma_base_test +UVM_TEST_SEQ=dma_generic_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage/default/49.dma_generic_smoke.2739232517 -covworkdir /nightly/current_run/scratch/master/dma-sim-xcelium/coverage -covscope default -covtest 49.dma_generic_smoke.2739232517 -covoverwrite' seed=9933650608018824013729952507217073876476348115212212033152200381885376192261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9933650608018824013729952507217073876476348115212212033152200381885376192261 --run-dir=/nightly/current_run/scratch/master/dma-sim-xcelium/49.dma_generic_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=dma_base_test uvm_test_seq=dma_generic_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job returned a non-zero exit code: *":[{"name":"dma","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/cov_merge/merged/cov_merge.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126\n"]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"dma","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/cov_report/cov_report.log","log_context":[]}]}},"passed":3,"total":268,"percent":1.1194029850746268}