{"block":{"name":"edn","variant":"edn1","commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn1/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.931901277974248,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":0.840631416067481,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":1.3200382040813565,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":0.836083841510117,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":0.8411216009408236,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":0.8671635584905744,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":1.3200382040813565,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"edn_csr_aliasing":{"max_time":0.8411216009408236,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":6,"percent":0.0}},"passed":0,"total":23,"percent":0.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":1.4307496920228004,"sim_time":0.0,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":1.4307496920228004,"sim_time":0.0,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"genbits":{"tests":{"edn_genbits":{"max_time":1.4307496920228004,"sim_time":0.0,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.410707808099687,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"alerts":{"tests":{"edn_alert":{"max_time":1.4196287682279944,"sim_time":0.0,"passed":0,"total":200,"percent":0.0}},"passed":0,"total":200,"percent":0.0},"errs":{"tests":{"edn_err":{"max_time":1.4185914965346456,"sim_time":0.0,"passed":0,"total":100,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"disable":{"tests":{"edn_disable":{"max_time":0.8954893769696355,"sim_time":0.0,"passed":0,"total":50,"percent":0.0},"edn_disable_auto_req_mode":{"max_time":1.4171390980482101,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":100,"percent":0.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":6.46,"sim_time":342.34801799999997,"passed":30,"total":30,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":0.853705701418221,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":1.365114982239902,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":1.371717194095254,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":1.371717194095254,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.840631416067481,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"edn_csr_rw":{"max_time":1.3200382040813565,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"edn_csr_aliasing":{"max_time":0.8411216009408236,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"edn_same_csr_outstanding":{"max_time":1.362260676920414,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":12,"percent":0.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.840631416067481,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"edn_csr_rw":{"max_time":1.3200382040813565,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"edn_csr_aliasing":{"max_time":0.8411216009408236,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"edn_same_csr_outstanding":{"max_time":1.362260676920414,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":12,"percent":0.0}},"passed":30,"total":607,"percent":4.942339373970346},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_sec_cm":{"max_time":1.4337655641138554,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"edn_tl_intg_err":{"max_time":1.4097365541383624,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":30,"percent":0.0},"sec_cm_config_regwen":{"tests":{"edn_regwen":{"max_time":1.4293949073180556,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.4196287682279944,"sim_time":0.0,"passed":0,"total":200,"percent":0.0}},"passed":0,"total":200,"percent":0.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":1.4337655641138554,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":1.4337655641138554,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":1.4337655641138554,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":1.4337655641138554,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.4196287682279944,"sim_time":0.0,"passed":0,"total":200,"percent":0.0},"edn_sec_cm":{"max_time":1.4337655641138554,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":205,"percent":0.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.4196287682279944,"sim_time":0.0,"passed":0,"total":200,"percent":0.0}},"passed":0,"total":200,"percent":0.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":1.4097365541383624,"sim_time":0.0,"passed":0,"total":25,"percent":0.0}},"passed":0,"total":25,"percent":0.0}},"passed":0,"total":235,"percent":0.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":1.3764637960121036,"sim_time":0.0,"passed":0,"total":30,"percent":0.0}},"passed":0,"total":30,"percent":0.0}},"passed":0,"total":30,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"edn_smoke","qual_name":"0.edn_smoke.59331919253176382546560035316302780343220940339369538291716657332315782226013","seed":59331919253176382546560035316302780343220940339369538291716657332315782226013,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3945111645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3945111645' seed=59331919253176382546560035316302780343220940339369538291716657332315782226013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59331919253176382546560035316302780343220940339369538291716657332315782226013 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_regwen","qual_name":"0.edn_regwen.91511083159584431267150362807420273309730779326851980224877446640468598477052","seed":91511083159584431267150362807420273309730779326851980224877446640468598477052,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_regwen/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=313807100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.313807100' seed=91511083159584431267150362807420273309730779326851980224877446640468598477052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91511083159584431267150362807420273309730779326851980224877446640468598477052 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"0.edn_genbits.87807514526537247015235496166429399835338138992298078514525317219842481601551","seed":87807514526537247015235496166429399835338138992298078514525317219842481601551,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2116434959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2116434959' seed=87807514526537247015235496166429399835338138992298078514525317219842481601551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87807514526537247015235496166429399835338138992298078514525317219842481601551 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"0.edn_stress_all_with_rand_reset.49276371857325515962102951297935041615155314996146646389747948286083125488032","seed":49276371857325515962102951297935041615155314996146646389747948286083125488032,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1779444128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1779444128' seed=49276371857325515962102951297935041615155314996146646389747948286083125488032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49276371857325515962102951297935041615155314996146646389747948286083125488032 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"0.edn_intr.56345970825130094810676681760820467948020229850192727394581832516636850390514","seed":56345970825130094810676681760820467948020229850192727394581832516636850390514,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823161330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2823161330' seed=56345970825130094810676681760820467948020229850192727394581832516636850390514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56345970825130094810676681760820467948020229850192727394581832516636850390514 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"0.edn_alert.8711669250725567647129261620365278589881825983404747314357577064005738151600","seed":8711669250725567647129261620365278589881825983404747314357577064005738151600,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207863472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.207863472' seed=8711669250725567647129261620365278589881825983404747314357577064005738151600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8711669250725567647129261620365278589881825983404747314357577064005738151600 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"0.edn_err.30429838994325850987733406165548376282471478553041751895599065947976680295253","seed":30429838994325850987733406165548376282471478553041751895599065947976680295253,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2399882069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2399882069' seed=30429838994325850987733406165548376282471478553041751895599065947976680295253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30429838994325850987733406165548376282471478553041751895599065947976680295253 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"0.edn_disable.9816617489343174984377847484815347827696868119905015967780593041653416479188","seed":9816617489343174984377847484815347827696868119905015967780593041653416479188,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=720783828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.720783828' seed=9816617489343174984377847484815347827696868119905015967780593041653416479188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9816617489343174984377847484815347827696868119905015967780593041653416479188 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"0.edn_disable_auto_req_mode.27264636889245951729000802053873046957361173342045671826052678797314092286482","seed":27264636889245951729000802053873046957361173342045671826052678797314092286482,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612745746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.612745746' seed=27264636889245951729000802053873046957361173342045671826052678797314092286482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27264636889245951729000802053873046957361173342045671826052678797314092286482 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_sec_cm","qual_name":"0.edn_sec_cm.42231375536550358827081429310665375347420371771154893706060635034184863371975","seed":42231375536550358827081429310665375347420371771154893706060635034184863371975,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=515035847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.515035847' seed=42231375536550358827081429310665375347420371771154893706060635034184863371975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42231375536550358827081429310665375347420371771154893706060635034184863371975 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"0.edn_tl_errors.68764572567177535081316980698875848745866255154464775482445326515937661473678","seed":68764572567177535081316980698875848745866255154464775482445326515937661473678,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1994707854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1994707854' seed=68764572567177535081316980698875848745866255154464775482445326515937661473678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68764572567177535081316980698875848745866255154464775482445326515937661473678 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"0.edn_tl_intg_err.19469175989505456992183545824954967118437523248744638188890397922156507999596","seed":19469175989505456992183545824954967118437523248744638188890397922156507999596,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3222449516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3222449516' seed=19469175989505456992183545824954967118437523248744638188890397922156507999596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19469175989505456992183545824954967118437523248744638188890397922156507999596 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"0.edn_alert_test.88547809530377688646501904148087603247997969843545412280871452196666258962270","seed":88547809530377688646501904148087603247997969843545412280871452196666258962270,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2771859294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2771859294' seed=88547809530377688646501904148087603247997969843545412280871452196666258962270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88547809530377688646501904148087603247997969843545412280871452196666258962270 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"0.edn_intr_test.58218270608658796100246152254320228858550941992114524644671789463111903943275","seed":58218270608658796100246152254320228858550941992114524644671789463111903943275,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569055851 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.569055851' seed=58218270608658796100246152254320228858550941992114524644671789463111903943275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58218270608658796100246152254320228858550941992114524644671789463111903943275 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_hw_reset","qual_name":"0.edn_csr_hw_reset.62744092220014976483955977994170761570709988402291957247498349054275729439555","seed":62744092220014976483955977994170761570709988402291957247498349054275729439555,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840383299 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.840383299' seed=62744092220014976483955977994170761570709988402291957247498349054275729439555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62744092220014976483955977994170761570709988402291957247498349054275729439555 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_rw","qual_name":"0.edn_csr_rw.40426394131178692504473949968227379086745246585293429314665844897872929670056","seed":40426394131178692504473949968227379086745246585293429314665844897872929670056,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=192463784 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.192463784' seed=40426394131178692504473949968227379086745246585293429314665844897872929670056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40426394131178692504473949968227379086745246585293429314665844897872929670056 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_bit_bash","qual_name":"0.edn_csr_bit_bash.68684337516038133824668560950285756696138861838528302136320637346554271583504","seed":68684337516038133824668560950285756696138861838528302136320637346554271583504,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861728528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3861728528' seed=68684337516038133824668560950285756696138861838528302136320637346554271583504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68684337516038133824668560950285756696138861838528302136320637346554271583504 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_aliasing","qual_name":"0.edn_csr_aliasing.80197617459461592443660551817020085135895518377614125903323276442654685918032","seed":80197617459461592443660551817020085135895518377614125903323276442654685918032,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292735824 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4292735824' seed=80197617459461592443660551817020085135895518377614125903323276442654685918032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80197617459461592443660551817020085135895518377614125903323276442654685918032 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_same_csr_outstanding","qual_name":"0.edn_same_csr_outstanding.4329569872885036818803564785554333784718387241193568700394588190362774563363","seed":4329569872885036818803564785554333784718387241193568700394588190362774563363,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128898595 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2128898595' seed=4329569872885036818803564785554333784718387241193568700394588190362774563363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4329569872885036818803564785554333784718387241193568700394588190362774563363 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_mem_rw_with_rand_reset","qual_name":"0.edn_csr_mem_rw_with_rand_reset.8919305171321473312541965467743748528470955017338985331894309801186557132118","seed":8919305171321473312541965467743748528470955017338985331894309801186557132118,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483622230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.483622230' seed=8919305171321473312541965467743748528470955017338985331894309801186557132118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8919305171321473312541965467743748528470955017338985331894309801186557132118 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"1.edn_smoke.19089237410110484663488138994354739090943397708595696966045135526198446624231","seed":19089237410110484663488138994354739090943397708595696966045135526198446624231,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1887407591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1887407591' seed=19089237410110484663488138994354739090943397708595696966045135526198446624231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19089237410110484663488138994354739090943397708595696966045135526198446624231 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_regwen","qual_name":"1.edn_regwen.94242191188549602895400002273554247366847691261836993744167079038096898980683","seed":94242191188549602895400002273554247366847691261836993744167079038096898980683,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_regwen/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2376006475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2376006475' seed=94242191188549602895400002273554247366847691261836993744167079038096898980683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94242191188549602895400002273554247366847691261836993744167079038096898980683 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"1.edn_genbits.51258728696412954083218650876269954393796005838267476230270358596982490136208","seed":51258728696412954083218650876269954393796005838267476230270358596982490136208,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2719088272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2719088272' seed=51258728696412954083218650876269954393796005838267476230270358596982490136208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51258728696412954083218650876269954393796005838267476230270358596982490136208 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"1.edn_stress_all_with_rand_reset.70144568515343699434576780456582246166589812065964536745877237630858778036750","seed":70144568515343699434576780456582246166589812065964536745877237630858778036750,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374786574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.374786574' seed=70144568515343699434576780456582246166589812065964536745877237630858778036750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70144568515343699434576780456582246166589812065964536745877237630858778036750 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"1.edn_intr.49915798030643336430745897184657937804726284774171730343539617561852670916069","seed":49915798030643336430745897184657937804726284774171730343539617561852670916069,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046730725 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4046730725' seed=49915798030643336430745897184657937804726284774171730343539617561852670916069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49915798030643336430745897184657937804726284774171730343539617561852670916069 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"1.edn_alert.74736327617691481274199537880124765336429831130578487905653997686206287471744","seed":74736327617691481274199537880124765336429831130578487905653997686206287471744,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667313280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.667313280' seed=74736327617691481274199537880124765336429831130578487905653997686206287471744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74736327617691481274199537880124765336429831130578487905653997686206287471744 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"1.edn_err.15028084539500541041303790986524562837896525379688794213031896121461482569925","seed":15028084539500541041303790986524562837896525379688794213031896121461482569925,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3313615045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3313615045' seed=15028084539500541041303790986524562837896525379688794213031896121461482569925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15028084539500541041303790986524562837896525379688794213031896121461482569925 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"1.edn_disable.114332584983924388773008221090135968215002389608160501961513624448643383700295","seed":114332584983924388773008221090135968215002389608160501961513624448643383700295,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3428854599 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3428854599' seed=114332584983924388773008221090135968215002389608160501961513624448643383700295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114332584983924388773008221090135968215002389608160501961513624448643383700295 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"1.edn_disable_auto_req_mode.98096115952266951054630804517763389907152518250363946222145474415101794060551","seed":98096115952266951054630804517763389907152518250363946222145474415101794060551,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404204295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3404204295' seed=98096115952266951054630804517763389907152518250363946222145474415101794060551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98096115952266951054630804517763389907152518250363946222145474415101794060551 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_sec_cm","qual_name":"1.edn_sec_cm.45024679628446223577582207144966396425880610532156408241573942067284427139149","seed":45024679628446223577582207144966396425880610532156408241573942067284427139149,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782573133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1782573133' seed=45024679628446223577582207144966396425880610532156408241573942067284427139149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45024679628446223577582207144966396425880610532156408241573942067284427139149 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"1.edn_tl_errors.30637352006842177058205142922878182838052580217702009384039190848277073411390","seed":30637352006842177058205142922878182838052580217702009384039190848277073411390,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123756350 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3123756350' seed=30637352006842177058205142922878182838052580217702009384039190848277073411390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30637352006842177058205142922878182838052580217702009384039190848277073411390 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"1.edn_tl_intg_err.56496493930425748071680854110649030925587516036476876343146637562261156508205","seed":56496493930425748071680854110649030925587516036476876343146637562261156508205,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916463149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2916463149' seed=56496493930425748071680854110649030925587516036476876343146637562261156508205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56496493930425748071680854110649030925587516036476876343146637562261156508205 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"1.edn_alert_test.43128905970470095061498909707671916848849211783733780969673693192466330206566","seed":43128905970470095061498909707671916848849211783733780969673693192466330206566,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1780138342 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1780138342' seed=43128905970470095061498909707671916848849211783733780969673693192466330206566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43128905970470095061498909707671916848849211783733780969673693192466330206566 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"1.edn_intr_test.72540246085776137316707980801892283618717036135639034714972621516643596931690","seed":72540246085776137316707980801892283618717036135639034714972621516643596931690,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3750138474 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3750138474' seed=72540246085776137316707980801892283618717036135639034714972621516643596931690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72540246085776137316707980801892283618717036135639034714972621516643596931690 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_rw","qual_name":"1.edn_csr_rw.16328066449792573297857817363289610660801186376918087035527707092677281490607","seed":16328066449792573297857817363289610660801186376918087035527707092677281490607,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3663767215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3663767215' seed=16328066449792573297857817363289610660801186376918087035527707092677281490607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16328066449792573297857817363289610660801186376918087035527707092677281490607 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_same_csr_outstanding","qual_name":"1.edn_same_csr_outstanding.72524773579649998265660041697636233841426728253396537513449354592075075839957","seed":72524773579649998265660041697636233841426728253396537513449354592075075839957,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702469077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.2702469077' seed=72524773579649998265660041697636233841426728253396537513449354592075075839957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72524773579649998265660041697636233841426728253396537513449354592075075839957 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_mem_rw_with_rand_reset","qual_name":"1.edn_csr_mem_rw_with_rand_reset.20609173648620910813378074148159842471768833191070878753321830615168048976217","seed":20609173648620910813378074148159842471768833191070878753321830615168048976217,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268797785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1268797785' seed=20609173648620910813378074148159842471768833191070878753321830615168048976217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20609173648620910813378074148159842471768833191070878753321830615168048976217 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"2.edn_smoke.81172621278267072569387814533084216246887358945009582038577066944158454798150","seed":81172621278267072569387814533084216246887358945009582038577066944158454798150,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117804358 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1117804358' seed=81172621278267072569387814533084216246887358945009582038577066944158454798150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81172621278267072569387814533084216246887358945009582038577066944158454798150 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_regwen","qual_name":"2.edn_regwen.12949479630443791285356527242134294548607817611552824844600898163295521687953","seed":12949479630443791285356527242134294548607817611552824844600898163295521687953,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_regwen/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049081233 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3049081233' seed=12949479630443791285356527242134294548607817611552824844600898163295521687953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12949479630443791285356527242134294548607817611552824844600898163295521687953 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"2.edn_genbits.49702749967977690347711387562561172069855956845370998030712134116860965241178","seed":49702749967977690347711387562561172069855956845370998030712134116860965241178,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3944300890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3944300890' seed=49702749967977690347711387562561172069855956845370998030712134116860965241178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49702749967977690347711387562561172069855956845370998030712134116860965241178 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"2.edn_stress_all_with_rand_reset.56822773696559359353588495632587678322168673165398076133664523065791845518399","seed":56822773696559359353588495632587678322168673165398076133664523065791845518399,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375830591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2375830591' seed=56822773696559359353588495632587678322168673165398076133664523065791845518399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56822773696559359353588495632587678322168673165398076133664523065791845518399 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"2.edn_intr.90113363100898159426583879120440097210149395933687495164276266981536472988209","seed":90113363100898159426583879120440097210149395933687495164276266981536472988209,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945781297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.945781297' seed=90113363100898159426583879120440097210149395933687495164276266981536472988209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90113363100898159426583879120440097210149395933687495164276266981536472988209 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"2.edn_alert.90286837796126570185496666038299827439341555959680476212615556767923727083135","seed":90286837796126570185496666038299827439341555959680476212615556767923727083135,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3855722111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3855722111' seed=90286837796126570185496666038299827439341555959680476212615556767923727083135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90286837796126570185496666038299827439341555959680476212615556767923727083135 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"2.edn_err.11444188751458273676252750780645291016615276097165711818573770976711334064232","seed":11444188751458273676252750780645291016615276097165711818573770976711334064232,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3862851688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3862851688' seed=11444188751458273676252750780645291016615276097165711818573770976711334064232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11444188751458273676252750780645291016615276097165711818573770976711334064232 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"2.edn_disable.92935895436106529996565667096681170759567382678358736424846902919149775494549","seed":92935895436106529996565667096681170759567382678358736424846902919149775494549,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2226920853 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2226920853' seed=92935895436106529996565667096681170759567382678358736424846902919149775494549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92935895436106529996565667096681170759567382678358736424846902919149775494549 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"2.edn_disable_auto_req_mode.66180595268133074209976595469903107744796723591609618568244015105181850262688","seed":66180595268133074209976595469903107744796723591609618568244015105181850262688,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113499296 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.113499296' seed=66180595268133074209976595469903107744796723591609618568244015105181850262688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66180595268133074209976595469903107744796723591609618568244015105181850262688 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_sec_cm","qual_name":"2.edn_sec_cm.77077874075919076547974820663960574843479217669854977147532581278584126820425","seed":77077874075919076547974820663960574843479217669854977147532581278584126820425,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=891015241 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.891015241' seed=77077874075919076547974820663960574843479217669854977147532581278584126820425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77077874075919076547974820663960574843479217669854977147532581278584126820425 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"2.edn_tl_errors.50434641188342149202668430866383563733548031045403618139961841128815720435492","seed":50434641188342149202668430866383563733548031045403618139961841128815720435492,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037054244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4037054244' seed=50434641188342149202668430866383563733548031045403618139961841128815720435492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50434641188342149202668430866383563733548031045403618139961841128815720435492 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"2.edn_tl_intg_err.101056729882556249885208327048930334523816376517644112928834763875833464844658","seed":101056729882556249885208327048930334523816376517644112928834763875833464844658,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717217138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2717217138' seed=101056729882556249885208327048930334523816376517644112928834763875833464844658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101056729882556249885208327048930334523816376517644112928834763875833464844658 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"2.edn_alert_test.54673928404163811292062116856141008719248991071201561208136019773597004156792","seed":54673928404163811292062116856141008719248991071201561208136019773597004156792,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3648868216 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3648868216' seed=54673928404163811292062116856141008719248991071201561208136019773597004156792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54673928404163811292062116856141008719248991071201561208136019773597004156792 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"2.edn_intr_test.23233637833914985149038271864980397451500191125983416841639532517069987785614","seed":23233637833914985149038271864980397451500191125983416841639532517069987785614,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263203726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.263203726' seed=23233637833914985149038271864980397451500191125983416841639532517069987785614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23233637833914985149038271864980397451500191125983416841639532517069987785614 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_rw","qual_name":"2.edn_csr_rw.80288285356700348846873121200651556411106285530473051713721690007322891264949","seed":80288285356700348846873121200651556411106285530473051713721690007322891264949,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3567133621 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3567133621' seed=80288285356700348846873121200651556411106285530473051713721690007322891264949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80288285356700348846873121200651556411106285530473051713721690007322891264949 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_same_csr_outstanding","qual_name":"2.edn_same_csr_outstanding.55900346622552854331766418906730784196244624920537675747003497982942045623308","seed":55900346622552854331766418906730784196244624920537675747003497982942045623308,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866893836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.2866893836' seed=55900346622552854331766418906730784196244624920537675747003497982942045623308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55900346622552854331766418906730784196244624920537675747003497982942045623308 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_mem_rw_with_rand_reset","qual_name":"2.edn_csr_mem_rw_with_rand_reset.99629240303301221372436552691260114166306757890998201877038281716086198808258","seed":99629240303301221372436552691260114166306757890998201877038281716086198808258,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2304552642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2304552642' seed=99629240303301221372436552691260114166306757890998201877038281716086198808258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99629240303301221372436552691260114166306757890998201877038281716086198808258 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"3.edn_smoke.112677867403832751682224171529564951769544968774368012439045201330332409860863","seed":112677867403832751682224171529564951769544968774368012439045201330332409860863,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2663453439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2663453439' seed=112677867403832751682224171529564951769544968774368012439045201330332409860863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112677867403832751682224171529564951769544968774368012439045201330332409860863 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_regwen","qual_name":"3.edn_regwen.2499122119778853188675149934008903413605826110375944905392748188495046392660","seed":2499122119778853188675149934008903413605826110375944905392748188495046392660,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_regwen/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1023818580 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1023818580' seed=2499122119778853188675149934008903413605826110375944905392748188495046392660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2499122119778853188675149934008903413605826110375944905392748188495046392660 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"3.edn_genbits.91639741670573665806489665514575939548234956166988674721131829736539053750613","seed":91639741670573665806489665514575939548234956166988674721131829736539053750613,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3728865621 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3728865621' seed=91639741670573665806489665514575939548234956166988674721131829736539053750613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91639741670573665806489665514575939548234956166988674721131829736539053750613 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"3.edn_stress_all_with_rand_reset.113610207456878149687948064514454736901069060622644735885325027417371771327176","seed":113610207456878149687948064514454736901069060622644735885325027417371771327176,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3509506760 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3509506760' seed=113610207456878149687948064514454736901069060622644735885325027417371771327176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113610207456878149687948064514454736901069060622644735885325027417371771327176 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"3.edn_intr.40885111463161709858456944305284657671296066869021465045430015524670158018810","seed":40885111463161709858456944305284657671296066869021465045430015524670158018810,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4145944826 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4145944826' seed=40885111463161709858456944305284657671296066869021465045430015524670158018810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40885111463161709858456944305284657671296066869021465045430015524670158018810 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"3.edn_alert.4187375029030213868817660097392371226209271528856586329150505508331689378295","seed":4187375029030213868817660097392371226209271528856586329150505508331689378295,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3079700983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3079700983' seed=4187375029030213868817660097392371226209271528856586329150505508331689378295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4187375029030213868817660097392371226209271528856586329150505508331689378295 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"3.edn_err.108102043074010552302158059600298737626717611559999470793679870714341614407504","seed":108102043074010552302158059600298737626717611559999470793679870714341614407504,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3735015248 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3735015248' seed=108102043074010552302158059600298737626717611559999470793679870714341614407504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108102043074010552302158059600298737626717611559999470793679870714341614407504 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"3.edn_disable.12330660222921056002714318239013685085790222031000239101433309064346271653885","seed":12330660222921056002714318239013685085790222031000239101433309064346271653885,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2961612797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2961612797' seed=12330660222921056002714318239013685085790222031000239101433309064346271653885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12330660222921056002714318239013685085790222031000239101433309064346271653885 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"3.edn_disable_auto_req_mode.12668278407919489107720145110268011305883977794486331221972562913284547318667","seed":12668278407919489107720145110268011305883977794486331221972562913284547318667,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=932877195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.932877195' seed=12668278407919489107720145110268011305883977794486331221972562913284547318667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12668278407919489107720145110268011305883977794486331221972562913284547318667 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_sec_cm","qual_name":"3.edn_sec_cm.50684208416491348080654295593843733892771586544088869139284224519418306827543","seed":50684208416491348080654295593843733892771586544088869139284224519418306827543,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2250970391 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2250970391' seed=50684208416491348080654295593843733892771586544088869139284224519418306827543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50684208416491348080654295593843733892771586544088869139284224519418306827543 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"3.edn_tl_errors.82387137020253062007031092947827225324390123100768567794862759349992449428758","seed":82387137020253062007031092947827225324390123100768567794862759349992449428758,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907857174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.907857174' seed=82387137020253062007031092947827225324390123100768567794862759349992449428758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82387137020253062007031092947827225324390123100768567794862759349992449428758 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"3.edn_tl_intg_err.43039888893242208763574452490839565306264273551190095238285645767044635372153","seed":43039888893242208763574452490839565306264273551190095238285645767044635372153,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2839095929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2839095929' seed=43039888893242208763574452490839565306264273551190095238285645767044635372153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43039888893242208763574452490839565306264273551190095238285645767044635372153 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"3.edn_alert_test.17249593023499342569578123647640001217646536534984530015939007554275560305191","seed":17249593023499342569578123647640001217646536534984530015939007554275560305191,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1887089191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1887089191' seed=17249593023499342569578123647640001217646536534984530015939007554275560305191 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17249593023499342569578123647640001217646536534984530015939007554275560305191 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"3.edn_intr_test.50890436603798376611063485368038896337014007683310846992100915554542043601349","seed":50890436603798376611063485368038896337014007683310846992100915554542043601349,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=537991621 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.537991621' seed=50890436603798376611063485368038896337014007683310846992100915554542043601349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50890436603798376611063485368038896337014007683310846992100915554542043601349 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_rw","qual_name":"3.edn_csr_rw.91542716316750103571299748552906110823542919180863978637211376535104668169094","seed":91542716316750103571299748552906110823542919180863978637211376535104668169094,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703698310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3703698310' seed=91542716316750103571299748552906110823542919180863978637211376535104668169094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91542716316750103571299748552906110823542919180863978637211376535104668169094 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_same_csr_outstanding","qual_name":"3.edn_same_csr_outstanding.3832076867688810119743241897337802781875539368203412079789447067724840258917","seed":3832076867688810119743241897337802781875539368203412079789447067724840258917,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493416293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.3493416293' seed=3832076867688810119743241897337802781875539368203412079789447067724840258917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3832076867688810119743241897337802781875539368203412079789447067724840258917 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_mem_rw_with_rand_reset","qual_name":"3.edn_csr_mem_rw_with_rand_reset.20941967091622067182620406586356509205308581783223201163215235945486802767319","seed":20941967091622067182620406586356509205308581783223201163215235945486802767319,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=622349783 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.622349783' seed=20941967091622067182620406586356509205308581783223201163215235945486802767319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20941967091622067182620406586356509205308581783223201163215235945486802767319 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"4.edn_smoke.32155706077177041844819466423586674789656315585137441163245640369206178033984","seed":32155706077177041844819466423586674789656315585137441163245640369206178033984,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=652947776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.652947776' seed=32155706077177041844819466423586674789656315585137441163245640369206178033984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32155706077177041844819466423586674789656315585137441163245640369206178033984 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_regwen","qual_name":"4.edn_regwen.85860591308955898521085726229243856695357073459315548487908484743747942744736","seed":85860591308955898521085726229243856695357073459315548487908484743747942744736,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_regwen/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3964142240 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3964142240' seed=85860591308955898521085726229243856695357073459315548487908484743747942744736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85860591308955898521085726229243856695357073459315548487908484743747942744736 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"4.edn_genbits.98901915251355745647799818399724709752640366265331570990866527746103173422008","seed":98901915251355745647799818399724709752640366265331570990866527746103173422008,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3293027256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3293027256' seed=98901915251355745647799818399724709752640366265331570990866527746103173422008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98901915251355745647799818399724709752640366265331570990866527746103173422008 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"4.edn_stress_all_with_rand_reset.58982482610568626785160825125263430913344215977361723529684439701621774951708","seed":58982482610568626785160825125263430913344215977361723529684439701621774951708,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292814108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4292814108' seed=58982482610568626785160825125263430913344215977361723529684439701621774951708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58982482610568626785160825125263430913344215977361723529684439701621774951708 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"4.edn_intr.16668690063590309891208355784954492256620232651744095440540868528245007282171","seed":16668690063590309891208355784954492256620232651744095440540868528245007282171,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3388829691 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3388829691' seed=16668690063590309891208355784954492256620232651744095440540868528245007282171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16668690063590309891208355784954492256620232651744095440540868528245007282171 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"4.edn_alert.37309388709092068167790019332881088819894414762215088526208631472739328292747","seed":37309388709092068167790019332881088819894414762215088526208631472739328292747,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1996584843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1996584843' seed=37309388709092068167790019332881088819894414762215088526208631472739328292747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37309388709092068167790019332881088819894414762215088526208631472739328292747 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"4.edn_err.108798420632222065154005317565142618625121559340315162535953167285547998740005","seed":108798420632222065154005317565142618625121559340315162535953167285547998740005,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385083941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2385083941' seed=108798420632222065154005317565142618625121559340315162535953167285547998740005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108798420632222065154005317565142618625121559340315162535953167285547998740005 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"4.edn_disable.86321943417390947431238573335546415458318600371557024935072110158531167934717","seed":86321943417390947431238573335546415458318600371557024935072110158531167934717,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2243844349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2243844349' seed=86321943417390947431238573335546415458318600371557024935072110158531167934717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86321943417390947431238573335546415458318600371557024935072110158531167934717 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"4.edn_disable_auto_req_mode.108874755452693383275640838046522963600487502916938488107947567437628106277834","seed":108874755452693383275640838046522963600487502916938488107947567437628106277834,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1799553994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.1799553994' seed=108874755452693383275640838046522963600487502916938488107947567437628106277834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108874755452693383275640838046522963600487502916938488107947567437628106277834 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_sec_cm","qual_name":"4.edn_sec_cm.65918193616373006095102693000895588349059575673106796770754509512508832900428","seed":65918193616373006095102693000895588349059575673106796770754509512508832900428,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4016203084 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4016203084' seed=65918193616373006095102693000895588349059575673106796770754509512508832900428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65918193616373006095102693000895588349059575673106796770754509512508832900428 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"4.edn_tl_errors.78539484775254134573326075439799746075742547987780548030926563716290774634456","seed":78539484775254134573326075439799746075742547987780548030926563716290774634456,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2821787608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2821787608' seed=78539484775254134573326075439799746075742547987780548030926563716290774634456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78539484775254134573326075439799746075742547987780548030926563716290774634456 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"4.edn_tl_intg_err.66641304923293169875924791565952606804890095785866683173645789251814779024510","seed":66641304923293169875924791565952606804890095785866683173645789251814779024510,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3595596926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3595596926' seed=66641304923293169875924791565952606804890095785866683173645789251814779024510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66641304923293169875924791565952606804890095785866683173645789251814779024510 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"4.edn_alert_test.43239835172947399476416530671664669085144459824379284435367697692404180636231","seed":43239835172947399476416530671664669085144459824379284435367697692404180636231,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3756577351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3756577351' seed=43239835172947399476416530671664669085144459824379284435367697692404180636231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43239835172947399476416530671664669085144459824379284435367697692404180636231 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"4.edn_intr_test.61785083731438355549331380480474298642601107585560787202420529173735720656448","seed":61785083731438355549331380480474298642601107585560787202420529173735720656448,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2070453824 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2070453824' seed=61785083731438355549331380480474298642601107585560787202420529173735720656448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61785083731438355549331380480474298642601107585560787202420529173735720656448 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_rw","qual_name":"4.edn_csr_rw.74390453129963566088067656570378231154078669500108577509758281213295671408951","seed":74390453129963566088067656570378231154078669500108577509758281213295671408951,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2849274167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2849274167' seed=74390453129963566088067656570378231154078669500108577509758281213295671408951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74390453129963566088067656570378231154078669500108577509758281213295671408951 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_same_csr_outstanding","qual_name":"4.edn_same_csr_outstanding.5508522356593928143026227237564766744082286783343899939492293121097378347073","seed":5508522356593928143026227237564766744082286783343899939492293121097378347073,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=158906433 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.158906433' seed=5508522356593928143026227237564766744082286783343899939492293121097378347073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5508522356593928143026227237564766744082286783343899939492293121097378347073 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_csr_mem_rw_with_rand_reset","qual_name":"4.edn_csr_mem_rw_with_rand_reset.87346622583949655167931966803316028152098583834350031552827646942826955855762","seed":87346622583949655167931966803316028152098583834350031552827646942826955855762,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334264722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3334264722' seed=87346622583949655167931966803316028152098583834350031552827646942826955855762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87346622583949655167931966803316028152098583834350031552827646942826955855762 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"5.edn_smoke.65800129091105224096587071717728801514656842769011301533598522152993049932172","seed":65800129091105224096587071717728801514656842769011301533598522152993049932172,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2162028940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2162028940' seed=65800129091105224096587071717728801514656842769011301533598522152993049932172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65800129091105224096587071717728801514656842769011301533598522152993049932172 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"5.edn_genbits.63687485653052521063675948236975650813285043530348891143389381582417362241894","seed":63687485653052521063675948236975650813285043530348891143389381582417362241894,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3367848294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3367848294' seed=63687485653052521063675948236975650813285043530348891143389381582417362241894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63687485653052521063675948236975650813285043530348891143389381582417362241894 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"5.edn_stress_all_with_rand_reset.62051354972330958080110492131103509574630165989667947286766442527039420904255","seed":62051354972330958080110492131103509574630165989667947286766442527039420904255,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260925759 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1260925759' seed=62051354972330958080110492131103509574630165989667947286766442527039420904255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62051354972330958080110492131103509574630165989667947286766442527039420904255 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"5.edn_intr.61359801631951850063927999157544926225908286841112997492262387397935136912754","seed":61359801631951850063927999157544926225908286841112997492262387397935136912754,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271622514 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2271622514' seed=61359801631951850063927999157544926225908286841112997492262387397935136912754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61359801631951850063927999157544926225908286841112997492262387397935136912754 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"5.edn_alert.9376087212669854655188353051728977459645355397299598011449051601234551026786","seed":9376087212669854655188353051728977459645355397299598011449051601234551026786,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=480687202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.480687202' seed=9376087212669854655188353051728977459645355397299598011449051601234551026786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9376087212669854655188353051728977459645355397299598011449051601234551026786 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"5.edn_err.78761335164583431607247288884574328003853779536234320994210870491794321306044","seed":78761335164583431607247288884574328003853779536234320994210870491794321306044,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3450991036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3450991036' seed=78761335164583431607247288884574328003853779536234320994210870491794321306044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78761335164583431607247288884574328003853779536234320994210870491794321306044 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"5.edn_disable.20115476886919812520937843764101582594217734303369835051034619235384396636029","seed":20115476886919812520937843764101582594217734303369835051034619235384396636029,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286078845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4286078845' seed=20115476886919812520937843764101582594217734303369835051034619235384396636029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20115476886919812520937843764101582594217734303369835051034619235384396636029 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"5.edn_disable_auto_req_mode.67330318986736339189155108122470964783402956692338507317860708041960290491222","seed":67330318986736339189155108122470964783402956692338507317860708041960290491222,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2218761046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.2218761046' seed=67330318986736339189155108122470964783402956692338507317860708041960290491222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67330318986736339189155108122470964783402956692338507317860708041960290491222 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"5.edn_tl_errors.75238826244405416399752006007084965961376864177366733630225559331551620000989","seed":75238826244405416399752006007084965961376864177366733630225559331551620000989,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=396258525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.396258525' seed=75238826244405416399752006007084965961376864177366733630225559331551620000989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75238826244405416399752006007084965961376864177366733630225559331551620000989 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"5.edn_tl_intg_err.14919654744344319047893277852447652969716089142998940505178102144375022672783","seed":14919654744344319047893277852447652969716089142998940505178102144375022672783,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043323791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1043323791' seed=14919654744344319047893277852447652969716089142998940505178102144375022672783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14919654744344319047893277852447652969716089142998940505178102144375022672783 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"5.edn_alert_test.109093443152616718039867837425981883365571574020993555680698846916479151550763","seed":109093443152616718039867837425981883365571574020993555680698846916479151550763,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2833821995 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2833821995' seed=109093443152616718039867837425981883365571574020993555680698846916479151550763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109093443152616718039867837425981883365571574020993555680698846916479151550763 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"5.edn_intr_test.53381567256355009491972988553865474445998211819656776308408581394949508899712","seed":53381567256355009491972988553865474445998211819656776308408581394949508899712,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=932127616 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.932127616' seed=53381567256355009491972988553865474445998211819656776308408581394949508899712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53381567256355009491972988553865474445998211819656776308408581394949508899712 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"6.edn_smoke.10362281803064859953496041799309032092307167532707001327881614941226601937086","seed":10362281803064859953496041799309032092307167532707001327881614941226601937086,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1608382654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1608382654' seed=10362281803064859953496041799309032092307167532707001327881614941226601937086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10362281803064859953496041799309032092307167532707001327881614941226601937086 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"6.edn_genbits.61069398672255247405408876825314248746310061964105480028546001803358283111790","seed":61069398672255247405408876825314248746310061964105480028546001803358283111790,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1990597998 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1990597998' seed=61069398672255247405408876825314248746310061964105480028546001803358283111790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61069398672255247405408876825314248746310061964105480028546001803358283111790 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"6.edn_stress_all_with_rand_reset.3481284735339916767733414975393100434413234517352345138553395100632665864594","seed":3481284735339916767733414975393100434413234517352345138553395100632665864594,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1859697042 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1859697042' seed=3481284735339916767733414975393100434413234517352345138553395100632665864594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3481284735339916767733414975393100434413234517352345138553395100632665864594 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"6.edn_intr.35410106500101187158768213093873117896230050793345928405098697622075188122327","seed":35410106500101187158768213093873117896230050793345928405098697622075188122327,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2591494871 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2591494871' seed=35410106500101187158768213093873117896230050793345928405098697622075188122327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35410106500101187158768213093873117896230050793345928405098697622075188122327 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"6.edn_alert.42221844528503344334058790080443700812659299302649051920637699783326808900730","seed":42221844528503344334058790080443700812659299302649051920637699783326808900730,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3020129402 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3020129402' seed=42221844528503344334058790080443700812659299302649051920637699783326808900730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42221844528503344334058790080443700812659299302649051920637699783326808900730 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"6.edn_err.32904017891137803350233982268843963750705351139358835047238640016814051722390","seed":32904017891137803350233982268843963750705351139358835047238640016814051722390,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2502722710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2502722710' seed=32904017891137803350233982268843963750705351139358835047238640016814051722390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32904017891137803350233982268843963750705351139358835047238640016814051722390 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"6.edn_disable.84557845820335261414684724002383585389945913810254873378243373000003545719874","seed":84557845820335261414684724002383585389945913810254873378243373000003545719874,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1035723842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1035723842' seed=84557845820335261414684724002383585389945913810254873378243373000003545719874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84557845820335261414684724002383585389945913810254873378243373000003545719874 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"6.edn_disable_auto_req_mode.49670124685950220946521101985091958506727193348242816231273310260178961197211","seed":49670124685950220946521101985091958506727193348242816231273310260178961197211,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=250767515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.250767515' seed=49670124685950220946521101985091958506727193348242816231273310260178961197211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49670124685950220946521101985091958506727193348242816231273310260178961197211 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"6.edn_tl_errors.53726790492701046297538145540220721883584200054167519317244846136767817076771","seed":53726790492701046297538145540220721883584200054167519317244846136767817076771,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3146928163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3146928163' seed=53726790492701046297538145540220721883584200054167519317244846136767817076771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53726790492701046297538145540220721883584200054167519317244846136767817076771 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"6.edn_tl_intg_err.33597423193462197689736400346928220995390945748089698815852819527554082070779","seed":33597423193462197689736400346928220995390945748089698815852819527554082070779,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659166971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1659166971' seed=33597423193462197689736400346928220995390945748089698815852819527554082070779 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33597423193462197689736400346928220995390945748089698815852819527554082070779 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"6.edn_alert_test.15502934460835093165174632123552489405636973820931160783065527672430283888698","seed":15502934460835093165174632123552489405636973820931160783065527672430283888698,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1486526522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1486526522' seed=15502934460835093165174632123552489405636973820931160783065527672430283888698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15502934460835093165174632123552489405636973820931160783065527672430283888698 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"6.edn_intr_test.91120292311919002318596510632864393820740689401398279131431656914550248870528","seed":91120292311919002318596510632864393820740689401398279131431656914550248870528,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3013251712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3013251712' seed=91120292311919002318596510632864393820740689401398279131431656914550248870528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91120292311919002318596510632864393820740689401398279131431656914550248870528 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"7.edn_smoke.71962247646460484087999730770668877932103371596340185363264210877543454993402","seed":71962247646460484087999730770668877932103371596340185363264210877543454993402,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4055755770 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4055755770' seed=71962247646460484087999730770668877932103371596340185363264210877543454993402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71962247646460484087999730770668877932103371596340185363264210877543454993402 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"7.edn_genbits.77673649943425225787493372454369970049703866874844735133755200743187453099211","seed":77673649943425225787493372454369970049703866874844735133755200743187453099211,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2135211211 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2135211211' seed=77673649943425225787493372454369970049703866874844735133755200743187453099211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77673649943425225787493372454369970049703866874844735133755200743187453099211 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"7.edn_stress_all_with_rand_reset.12758321306520266570486711751428892285453995899620354813208417285343075556000","seed":12758321306520266570486711751428892285453995899620354813208417285343075556000,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230953120 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1230953120' seed=12758321306520266570486711751428892285453995899620354813208417285343075556000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12758321306520266570486711751428892285453995899620354813208417285343075556000 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"7.edn_intr.105902250191759132817112522593145783593098824739846219788470980973450101776413","seed":105902250191759132817112522593145783593098824739846219788470980973450101776413,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2357190685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2357190685' seed=105902250191759132817112522593145783593098824739846219788470980973450101776413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105902250191759132817112522593145783593098824739846219788470980973450101776413 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"7.edn_alert.7039361976520523839064147399164360759088614924437505151263653568100750407109","seed":7039361976520523839064147399164360759088614924437505151263653568100750407109,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2061317573 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2061317573' seed=7039361976520523839064147399164360759088614924437505151263653568100750407109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7039361976520523839064147399164360759088614924437505151263653568100750407109 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"7.edn_err.103125389259248492824444875785549955725118815396134446711127122723800144086186","seed":103125389259248492824444875785549955725118815396134446711127122723800144086186,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2819556522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2819556522' seed=103125389259248492824444875785549955725118815396134446711127122723800144086186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103125389259248492824444875785549955725118815396134446711127122723800144086186 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"7.edn_disable.12764879695153002701147110327165404466871729860829636554681123188839308178389","seed":12764879695153002701147110327165404466871729860829636554681123188839308178389,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310752213 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.310752213' seed=12764879695153002701147110327165404466871729860829636554681123188839308178389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12764879695153002701147110327165404466871729860829636554681123188839308178389 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"7.edn_disable_auto_req_mode.99778595441365869597418712774600009026722484855100296815670171205012864153498","seed":99778595441365869597418712774600009026722484855100296815670171205012864153498,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3063986074 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.3063986074' seed=99778595441365869597418712774600009026722484855100296815670171205012864153498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99778595441365869597418712774600009026722484855100296815670171205012864153498 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"7.edn_tl_errors.68449726797658604352710011006610934424965066313920021451755832101208025612598","seed":68449726797658604352710011006610934424965066313920021451755832101208025612598,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3998630198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3998630198' seed=68449726797658604352710011006610934424965066313920021451755832101208025612598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68449726797658604352710011006610934424965066313920021451755832101208025612598 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"7.edn_tl_intg_err.107181039668199257835700773928307819093190878396228157218173769906154350770315","seed":107181039668199257835700773928307819093190878396228157218173769906154350770315,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286614667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2286614667' seed=107181039668199257835700773928307819093190878396228157218173769906154350770315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107181039668199257835700773928307819093190878396228157218173769906154350770315 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"7.edn_alert_test.43920298959907551719176327898231007336487351599260792920402360565362243154505","seed":43920298959907551719176327898231007336487351599260792920402360565362243154505,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3235394121 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3235394121' seed=43920298959907551719176327898231007336487351599260792920402360565362243154505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43920298959907551719176327898231007336487351599260792920402360565362243154505 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"7.edn_intr_test.114952835917349359672280760610031685584609731540962086985970866038694948266174","seed":114952835917349359672280760610031685584609731540962086985970866038694948266174,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2192203966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2192203966' seed=114952835917349359672280760610031685584609731540962086985970866038694948266174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114952835917349359672280760610031685584609731540962086985970866038694948266174 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"8.edn_smoke.90378696892830472959581104007571033286823628256108882323996396616467957537300","seed":90378696892830472959581104007571033286823628256108882323996396616467957537300,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1000200724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1000200724' seed=90378696892830472959581104007571033286823628256108882323996396616467957537300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90378696892830472959581104007571033286823628256108882323996396616467957537300 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"8.edn_genbits.9505668506463555175194568013944593333057399266424888158733899447506286121723","seed":9505668506463555175194568013944593333057399266424888158733899447506286121723,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3126825723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3126825723' seed=9505668506463555175194568013944593333057399266424888158733899447506286121723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9505668506463555175194568013944593333057399266424888158733899447506286121723 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"8.edn_stress_all_with_rand_reset.6279245072156468140503544402075154336341204056114507813065982823943522483963","seed":6279245072156468140503544402075154336341204056114507813065982823943522483963,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=200015611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.200015611' seed=6279245072156468140503544402075154336341204056114507813065982823943522483963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6279245072156468140503544402075154336341204056114507813065982823943522483963 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"8.edn_intr.47793885332155959445170359628297598761416658906057646775793862638748476099512","seed":47793885332155959445170359628297598761416658906057646775793862638748476099512,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4119579576 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4119579576' seed=47793885332155959445170359628297598761416658906057646775793862638748476099512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47793885332155959445170359628297598761416658906057646775793862638748476099512 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"8.edn_alert.32372937080789766430362934976786111086321277479929682799289153915797030425992","seed":32372937080789766430362934976786111086321277479929682799289153915797030425992,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1989531016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1989531016' seed=32372937080789766430362934976786111086321277479929682799289153915797030425992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32372937080789766430362934976786111086321277479929682799289153915797030425992 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"8.edn_err.59335478408910938125150380495675687955371853860935765880360936771481483992770","seed":59335478408910938125150380495675687955371853860935765880360936771481483992770,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=489807554 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.489807554' seed=59335478408910938125150380495675687955371853860935765880360936771481483992770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59335478408910938125150380495675687955371853860935765880360936771481483992770 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"8.edn_disable.15007763430898912685788916787369478982288857699586668151131617260033065382714","seed":15007763430898912685788916787369478982288857699586668151131617260033065382714,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2977198906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2977198906' seed=15007763430898912685788916787369478982288857699586668151131617260033065382714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15007763430898912685788916787369478982288857699586668151131617260033065382714 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"8.edn_disable_auto_req_mode.6711125535365380809573350304790565594392226122275358546351621112246451692742","seed":6711125535365380809573350304790565594392226122275358546351621112246451692742,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1354884294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.1354884294' seed=6711125535365380809573350304790565594392226122275358546351621112246451692742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6711125535365380809573350304790565594392226122275358546351621112246451692742 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"8.edn_tl_errors.85738778885636295000846213216699910668309513715448887782216508060097739347971","seed":85738778885636295000846213216699910668309513715448887782216508060097739347971,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1919801347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1919801347' seed=85738778885636295000846213216699910668309513715448887782216508060097739347971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85738778885636295000846213216699910668309513715448887782216508060097739347971 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"8.edn_tl_intg_err.22081807373123915256600299528219390100249412862368495809593351298297246818580","seed":22081807373123915256600299528219390100249412862368495809593351298297246818580,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054646548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1054646548' seed=22081807373123915256600299528219390100249412862368495809593351298297246818580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22081807373123915256600299528219390100249412862368495809593351298297246818580 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"8.edn_alert_test.11655797407934396113031616125237238321349720431570446808561971814193976356377","seed":11655797407934396113031616125237238321349720431570446808561971814193976356377,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2496179737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2496179737' seed=11655797407934396113031616125237238321349720431570446808561971814193976356377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11655797407934396113031616125237238321349720431570446808561971814193976356377 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"8.edn_intr_test.14101169255076288683764226181083027945405650937277864259446941168383690848025","seed":14101169255076288683764226181083027945405650937277864259446941168383690848025,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332445465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.332445465' seed=14101169255076288683764226181083027945405650937277864259446941168383690848025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14101169255076288683764226181083027945405650937277864259446941168383690848025 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_smoke","qual_name":"9.edn_smoke.66048563963756259847138406090830591926871966448069275123156694235263027556068","seed":66048563963756259847138406090830591926871966448069275123156694235263027556068,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518593252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2518593252' seed=66048563963756259847138406090830591926871966448069275123156694235263027556068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66048563963756259847138406090830591926871966448069275123156694235263027556068 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"9.edn_genbits.32507197772551194712942736287396658139221102233785712364443526992352278625768","seed":32507197772551194712942736287396658139221102233785712364443526992352278625768,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=980827624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.980827624' seed=32507197772551194712942736287396658139221102233785712364443526992352278625768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32507197772551194712942736287396658139221102233785712364443526992352278625768 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"9.edn_stress_all_with_rand_reset.6646697829999236957969615301080122575788450025495566585581120238631986974509","seed":6646697829999236957969615301080122575788450025495566585581120238631986974509,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2205208365 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2205208365' seed=6646697829999236957969615301080122575788450025495566585581120238631986974509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6646697829999236957969615301080122575788450025495566585581120238631986974509 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"9.edn_intr.54517943380848869392322360632060856359944007125262674554174354188193274505656","seed":54517943380848869392322360632060856359944007125262674554174354188193274505656,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=570141112 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.570141112' seed=54517943380848869392322360632060856359944007125262674554174354188193274505656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54517943380848869392322360632060856359944007125262674554174354188193274505656 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"9.edn_alert.108991519002874215184251287614886563842294431917454783803228295363878697542838","seed":108991519002874215184251287614886563842294431917454783803228295363878697542838,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2167383222 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2167383222' seed=108991519002874215184251287614886563842294431917454783803228295363878697542838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108991519002874215184251287614886563842294431917454783803228295363878697542838 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"9.edn_err.1568561277465832265276644154689893495977941793851450203717046292565501765395","seed":1568561277465832265276644154689893495977941793851450203717046292565501765395,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2825742099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2825742099' seed=1568561277465832265276644154689893495977941793851450203717046292565501765395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1568561277465832265276644154689893495977941793851450203717046292565501765395 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"9.edn_disable.83161322308805804150739609101627325981769357200285902211926578229119645370676","seed":83161322308805804150739609101627325981769357200285902211926578229119645370676,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2732050740 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2732050740' seed=83161322308805804150739609101627325981769357200285902211926578229119645370676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83161322308805804150739609101627325981769357200285902211926578229119645370676 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"9.edn_disable_auto_req_mode.18426547552859538340425736661131979282128827294146471834706488931464969062264","seed":18426547552859538340425736661131979282128827294146471834706488931464969062264,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2667972472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.2667972472' seed=18426547552859538340425736661131979282128827294146471834706488931464969062264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18426547552859538340425736661131979282128827294146471834706488931464969062264 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"9.edn_tl_errors.8544958041543538089311045537191402296476176654177710214940438400611755554169","seed":8544958041543538089311045537191402296476176654177710214940438400611755554169,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3354457465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3354457465' seed=8544958041543538089311045537191402296476176654177710214940438400611755554169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8544958041543538089311045537191402296476176654177710214940438400611755554169 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"9.edn_tl_intg_err.103618793740439083399343591404691121625850405345686154332291263331705229714134","seed":103618793740439083399343591404691121625850405345686154332291263331705229714134,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880583382 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.880583382' seed=103618793740439083399343591404691121625850405345686154332291263331705229714134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103618793740439083399343591404691121625850405345686154332291263331705229714134 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert_test","qual_name":"9.edn_alert_test.46947715628545611906174631096830746006353694321820574812221703443018384454432","seed":46947715628545611906174631096830746006353694321820574812221703443018384454432,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3244077856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3244077856' seed=46947715628545611906174631096830746006353694321820574812221703443018384454432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46947715628545611906174631096830746006353694321820574812221703443018384454432 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr_test","qual_name":"9.edn_intr_test.106958285649040299260163677009120289316535616424955222733124640304586572969907","seed":106958285649040299260163677009120289316535616424955222733124640304586572969907,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_intr_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706126771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2706126771' seed=106958285649040299260163677009120289316535616424955222733124640304586572969907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106958285649040299260163677009120289316535616424955222733124640304586572969907 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"10.edn_genbits.115785019248021824557146401165640533821012991462033706104033359902956512448084","seed":115785019248021824557146401165640533821012991462033706104033359902956512448084,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936559700 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1936559700' seed=115785019248021824557146401165640533821012991462033706104033359902956512448084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115785019248021824557146401165640533821012991462033706104033359902956512448084 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"10.edn_stress_all_with_rand_reset.108507644934388948236278000065313442361943892880849923945230681454175357594338","seed":108507644934388948236278000065313442361943892880849923945230681454175357594338,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1482517218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1482517218' seed=108507644934388948236278000065313442361943892880849923945230681454175357594338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108507644934388948236278000065313442361943892880849923945230681454175357594338 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"10.edn_intr.20635195876732922561274547009363975359853233036532641216408378663455303783123","seed":20635195876732922561274547009363975359853233036532641216408378663455303783123,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861762771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3861762771' seed=20635195876732922561274547009363975359853233036532641216408378663455303783123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20635195876732922561274547009363975359853233036532641216408378663455303783123 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"10.edn_alert.76770390218653366544664230497801228680662037330018145720835132428828873632977","seed":76770390218653366544664230497801228680662037330018145720835132428828873632977,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2503257297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2503257297' seed=76770390218653366544664230497801228680662037330018145720835132428828873632977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76770390218653366544664230497801228680662037330018145720835132428828873632977 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"10.edn_err.83376022503782163272427829166267679121157133749450239336169903288732707831659","seed":83376022503782163272427829166267679121157133749450239336169903288732707831659,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=481148779 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.481148779' seed=83376022503782163272427829166267679121157133749450239336169903288732707831659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83376022503782163272427829166267679121157133749450239336169903288732707831659 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"10.edn_disable.18749929252054839573801930425059417774833438917301402126247019546123130430343","seed":18749929252054839573801930425059417774833438917301402126247019546123130430343,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1546183559 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1546183559' seed=18749929252054839573801930425059417774833438917301402126247019546123130430343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18749929252054839573801930425059417774833438917301402126247019546123130430343 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"10.edn_disable_auto_req_mode.39323853769860527853834189556250213436637468628242728573161086409800429907507","seed":39323853769860527853834189556250213436637468628242728573161086409800429907507,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767602227 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.767602227' seed=39323853769860527853834189556250213436637468628242728573161086409800429907507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39323853769860527853834189556250213436637468628242728573161086409800429907507 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"10.edn_tl_errors.24567605802119868828941226376795907617651146799026805306113759530769897330800","seed":24567605802119868828941226376795907617651146799026805306113759530769897330800,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2602145904 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2602145904' seed=24567605802119868828941226376795907617651146799026805306113759530769897330800 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24567605802119868828941226376795907617651146799026805306113759530769897330800 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"10.edn_tl_intg_err.35874174636203070081596032136977754977477312286561520819299120142052763369569","seed":35874174636203070081596032136977754977477312286561520819299120142052763369569,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=624427105 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.624427105' seed=35874174636203070081596032136977754977477312286561520819299120142052763369569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35874174636203070081596032136977754977477312286561520819299120142052763369569 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/10.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"11.edn_genbits.65672876049867791170009129565642811500638339655578148917420872026442517059123","seed":65672876049867791170009129565642811500638339655578148917420872026442517059123,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2620003891 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2620003891' seed=65672876049867791170009129565642811500638339655578148917420872026442517059123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65672876049867791170009129565642811500638339655578148917420872026442517059123 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"11.edn_stress_all_with_rand_reset.93267219159139881728768009436837135726903649528435659787243676367661008041733","seed":93267219159139881728768009436837135726903649528435659787243676367661008041733,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3502126853 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3502126853' seed=93267219159139881728768009436837135726903649528435659787243676367661008041733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93267219159139881728768009436837135726903649528435659787243676367661008041733 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"11.edn_intr.58529195661746663979865853158531705124803844519300140732509359339969369000652","seed":58529195661746663979865853158531705124803844519300140732509359339969369000652,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1797966540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1797966540' seed=58529195661746663979865853158531705124803844519300140732509359339969369000652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58529195661746663979865853158531705124803844519300140732509359339969369000652 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"11.edn_alert.68794581717509686339196308142219925760878336320410354066066206386031799624806","seed":68794581717509686339196308142219925760878336320410354066066206386031799624806,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1594680422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1594680422' seed=68794581717509686339196308142219925760878336320410354066066206386031799624806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68794581717509686339196308142219925760878336320410354066066206386031799624806 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"11.edn_err.77521472023666081659818571685742686181076119580481924066980682943965790764658","seed":77521472023666081659818571685742686181076119580481924066980682943965790764658,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1451523698 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1451523698' seed=77521472023666081659818571685742686181076119580481924066980682943965790764658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77521472023666081659818571685742686181076119580481924066980682943965790764658 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"11.edn_disable.59602777474162208583116128681425136665770881893227622103118358075095115567648","seed":59602777474162208583116128681425136665770881893227622103118358075095115567648,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3216970272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3216970272' seed=59602777474162208583116128681425136665770881893227622103118358075095115567648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59602777474162208583116128681425136665770881893227622103118358075095115567648 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"11.edn_disable_auto_req_mode.70156865881644636338754005338993843724182132687687275517844396535165412738897","seed":70156865881644636338754005338993843724182132687687275517844396535165412738897,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2368767825 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.2368767825' seed=70156865881644636338754005338993843724182132687687275517844396535165412738897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70156865881644636338754005338993843724182132687687275517844396535165412738897 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"11.edn_tl_errors.64041806189826846358205243851632175282520596367186501686504061558298766416315","seed":64041806189826846358205243851632175282520596367186501686504061558298766416315,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3583187387 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3583187387' seed=64041806189826846358205243851632175282520596367186501686504061558298766416315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64041806189826846358205243851632175282520596367186501686504061558298766416315 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"11.edn_tl_intg_err.61038176131522060283250843608008836068529563443251515008968892164440361247339","seed":61038176131522060283250843608008836068529563443251515008968892164440361247339,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3877085803 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3877085803' seed=61038176131522060283250843608008836068529563443251515008968892164440361247339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61038176131522060283250843608008836068529563443251515008968892164440361247339 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/11.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"12.edn_genbits.83408380808049939060380111094477647009292530870717667127017310609324703777457","seed":83408380808049939060380111094477647009292530870717667127017310609324703777457,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1357415089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1357415089' seed=83408380808049939060380111094477647009292530870717667127017310609324703777457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83408380808049939060380111094477647009292530870717667127017310609324703777457 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"12.edn_stress_all_with_rand_reset.73944040024550822432106358131130780518568042582117898630043453452933430260869","seed":73944040024550822432106358131130780518568042582117898630043453452933430260869,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701407365 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2701407365' seed=73944040024550822432106358131130780518568042582117898630043453452933430260869 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73944040024550822432106358131130780518568042582117898630043453452933430260869 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"12.edn_intr.75538823621272398266111988244159739251862060699329229027410899730052321138173","seed":75538823621272398266111988244159739251862060699329229027410899730052321138173,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2959103485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2959103485' seed=75538823621272398266111988244159739251862060699329229027410899730052321138173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75538823621272398266111988244159739251862060699329229027410899730052321138173 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"12.edn_alert.100752033259708148406549741922726892576896532684550479238954785799723489474025","seed":100752033259708148406549741922726892576896532684550479238954785799723489474025,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3650663913 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3650663913' seed=100752033259708148406549741922726892576896532684550479238954785799723489474025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100752033259708148406549741922726892576896532684550479238954785799723489474025 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"12.edn_err.11981712150729904306284580569890133995997574262603212272541827492452412457222","seed":11981712150729904306284580569890133995997574262603212272541827492452412457222,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836772614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3836772614' seed=11981712150729904306284580569890133995997574262603212272541827492452412457222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11981712150729904306284580569890133995997574262603212272541827492452412457222 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"12.edn_disable.55692338441774717939459850753845535722084530294766052868279666922883121259209","seed":55692338441774717939459850753845535722084530294766052868279666922883121259209,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447825097 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3447825097' seed=55692338441774717939459850753845535722084530294766052868279666922883121259209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55692338441774717939459850753845535722084530294766052868279666922883121259209 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"12.edn_disable_auto_req_mode.17394135639376228625004189308798974232396951311578850630179516428231439753350","seed":17394135639376228625004189308798974232396951311578850630179516428231439753350,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2443124870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.2443124870' seed=17394135639376228625004189308798974232396951311578850630179516428231439753350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17394135639376228625004189308798974232396951311578850630179516428231439753350 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"12.edn_tl_errors.20849371676538892812801461400489265519485274909976773671519427478761740382065","seed":20849371676538892812801461400489265519485274909976773671519427478761740382065,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78327665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.78327665' seed=20849371676538892812801461400489265519485274909976773671519427478761740382065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20849371676538892812801461400489265519485274909976773671519427478761740382065 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"12.edn_tl_intg_err.59597245883210528640205088601125044633214289204998911407114588623652021970396","seed":59597245883210528640205088601125044633214289204998911407114588623652021970396,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2668733916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2668733916' seed=59597245883210528640205088601125044633214289204998911407114588623652021970396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59597245883210528640205088601125044633214289204998911407114588623652021970396 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"13.edn_genbits.65294630859522462266508326295967068182141356296372055463974270616329167041151","seed":65294630859522462266508326295967068182141356296372055463974270616329167041151,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1396961919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1396961919' seed=65294630859522462266508326295967068182141356296372055463974270616329167041151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65294630859522462266508326295967068182141356296372055463974270616329167041151 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"13.edn_stress_all_with_rand_reset.86559264018130992892635459213375005452272233868575717544830140081631215864157","seed":86559264018130992892635459213375005452272233868575717544830140081631215864157,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=728090973 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.728090973' seed=86559264018130992892635459213375005452272233868575717544830140081631215864157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86559264018130992892635459213375005452272233868575717544830140081631215864157 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"13.edn_intr.72634111566370587744548140667551995097787010682795001038925136718859461488054","seed":72634111566370587744548140667551995097787010682795001038925136718859461488054,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237689270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2237689270' seed=72634111566370587744548140667551995097787010682795001038925136718859461488054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72634111566370587744548140667551995097787010682795001038925136718859461488054 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"13.edn_alert.79912384920086735841006039037215158130960850033499614966432219012605784121333","seed":79912384920086735841006039037215158130960850033499614966432219012605784121333,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=530079733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.530079733' seed=79912384920086735841006039037215158130960850033499614966432219012605784121333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79912384920086735841006039037215158130960850033499614966432219012605784121333 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"13.edn_err.33589694082852689561888324719852914463401991159907622565386662390691355667177","seed":33589694082852689561888324719852914463401991159907622565386662390691355667177,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2796530409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2796530409' seed=33589694082852689561888324719852914463401991159907622565386662390691355667177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33589694082852689561888324719852914463401991159907622565386662390691355667177 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"13.edn_disable.103480836629436727185200906240172035063217953268159723495461863329542392031689","seed":103480836629436727185200906240172035063217953268159723495461863329542392031689,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3151276489 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3151276489' seed=103480836629436727185200906240172035063217953268159723495461863329542392031689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103480836629436727185200906240172035063217953268159723495461863329542392031689 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"13.edn_disable_auto_req_mode.54477463018106056450341090448368118439438469357948356668905398135042754217807","seed":54477463018106056450341090448368118439438469357948356668905398135042754217807,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=839124815 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.839124815' seed=54477463018106056450341090448368118439438469357948356668905398135042754217807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54477463018106056450341090448368118439438469357948356668905398135042754217807 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"13.edn_tl_errors.75201798119866343109375008594487446682877022916944000729695269049388128877782","seed":75201798119866343109375008594487446682877022916944000729695269049388128877782,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=479280342 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.479280342' seed=75201798119866343109375008594487446682877022916944000729695269049388128877782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75201798119866343109375008594487446682877022916944000729695269049388128877782 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"13.edn_tl_intg_err.5244679053223801019437186688517452144392289584962627018690377657527728790661","seed":5244679053223801019437186688517452144392289584962627018690377657527728790661,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=953080965 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.953080965' seed=5244679053223801019437186688517452144392289584962627018690377657527728790661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5244679053223801019437186688517452144392289584962627018690377657527728790661 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"14.edn_genbits.66754405586916221270388726757691793999430133951735126594980522932339336026842","seed":66754405586916221270388726757691793999430133951735126594980522932339336026842,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2545949402 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2545949402' seed=66754405586916221270388726757691793999430133951735126594980522932339336026842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66754405586916221270388726757691793999430133951735126594980522932339336026842 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"14.edn_stress_all_with_rand_reset.6523012869367515650847102027538580916691075436415614858842025929274276993907","seed":6523012869367515650847102027538580916691075436415614858842025929274276993907,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2411223923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2411223923' seed=6523012869367515650847102027538580916691075436415614858842025929274276993907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6523012869367515650847102027538580916691075436415614858842025929274276993907 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"14.edn_intr.98111310675044208902548682137265706687194606048971790692997696228061503237117","seed":98111310675044208902548682137265706687194606048971790692997696228061503237117,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797125629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.797125629' seed=98111310675044208902548682137265706687194606048971790692997696228061503237117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98111310675044208902548682137265706687194606048971790692997696228061503237117 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"14.edn_alert.92314125692336935478709197157221313456704690611081853208732616479771175054164","seed":92314125692336935478709197157221313456704690611081853208732616479771175054164,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218786644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.218786644' seed=92314125692336935478709197157221313456704690611081853208732616479771175054164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92314125692336935478709197157221313456704690611081853208732616479771175054164 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"14.edn_err.25898847596178209419188824740601147346036054092237480739711082031702185532324","seed":25898847596178209419188824740601147346036054092237480739711082031702185532324,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1001577380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1001577380' seed=25898847596178209419188824740601147346036054092237480739711082031702185532324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25898847596178209419188824740601147346036054092237480739711082031702185532324 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"14.edn_disable.36236260469187660906172230846194272529355879419044758255024791836810801642922","seed":36236260469187660906172230846194272529355879419044758255024791836810801642922,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=480837034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.480837034' seed=36236260469187660906172230846194272529355879419044758255024791836810801642922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36236260469187660906172230846194272529355879419044758255024791836810801642922 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"14.edn_disable_auto_req_mode.24889568743793970307356122020474938327569119735304356607541802657918840830459","seed":24889568743793970307356122020474938327569119735304356607541802657918840830459,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690480635 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.2690480635' seed=24889568743793970307356122020474938327569119735304356607541802657918840830459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24889568743793970307356122020474938327569119735304356607541802657918840830459 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"14.edn_tl_errors.2906426448017502134541936596274634703909946436785320453857608776205926469582","seed":2906426448017502134541936596274634703909946436785320453857608776205926469582,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570995150 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3570995150' seed=2906426448017502134541936596274634703909946436785320453857608776205926469582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2906426448017502134541936596274634703909946436785320453857608776205926469582 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"14.edn_tl_intg_err.67729331812516322978465663187456666224899958281678844520734917074489872439533","seed":67729331812516322978465663187456666224899958281678844520734917074489872439533,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1663260909 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1663260909' seed=67729331812516322978465663187456666224899958281678844520734917074489872439533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67729331812516322978465663187456666224899958281678844520734917074489872439533 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"15.edn_genbits.84149097758629774188559474506397919161754592869182283099582102217709572324090","seed":84149097758629774188559474506397919161754592869182283099582102217709572324090,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3976723194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3976723194' seed=84149097758629774188559474506397919161754592869182283099582102217709572324090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84149097758629774188559474506397919161754592869182283099582102217709572324090 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"15.edn_stress_all_with_rand_reset.20192407643918195284044623141503967687002152066161624078757877918590232909279","seed":20192407643918195284044623141503967687002152066161624078757877918590232909279,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=402609631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.402609631' seed=20192407643918195284044623141503967687002152066161624078757877918590232909279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20192407643918195284044623141503967687002152066161624078757877918590232909279 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"15.edn_intr.17420557018174657038199884551047783763056029450492247436607819439330639479372","seed":17420557018174657038199884551047783763056029450492247436607819439330639479372,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2405171788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2405171788' seed=17420557018174657038199884551047783763056029450492247436607819439330639479372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17420557018174657038199884551047783763056029450492247436607819439330639479372 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"15.edn_alert.28154951291040937227942784258326437123712288796399969394207604151064803261282","seed":28154951291040937227942784258326437123712288796399969394207604151064803261282,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1164032866 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1164032866' seed=28154951291040937227942784258326437123712288796399969394207604151064803261282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28154951291040937227942784258326437123712288796399969394207604151064803261282 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"15.edn_err.100245555854125024464896844887804030444332075207712555882854039939764589269138","seed":100245555854125024464896844887804030444332075207712555882854039939764589269138,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392428690 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2392428690' seed=100245555854125024464896844887804030444332075207712555882854039939764589269138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100245555854125024464896844887804030444332075207712555882854039939764589269138 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"15.edn_disable.106706151429721033115732653605515713165957817035797084149671508235175502764120","seed":106706151429721033115732653605515713165957817035797084149671508235175502764120,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=946821208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.946821208' seed=106706151429721033115732653605515713165957817035797084149671508235175502764120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106706151429721033115732653605515713165957817035797084149671508235175502764120 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.100175870999546391659770833578659790667216397571464829950246647408174863204533","seed":100175870999546391659770833578659790667216397571464829950246647408174863204533,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2889859253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2889859253' seed=100175870999546391659770833578659790667216397571464829950246647408174863204533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100175870999546391659770833578659790667216397571464829950246647408174863204533 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"15.edn_tl_errors.8192644374832894598057806572908348822572611014624349564867920695408742679902","seed":8192644374832894598057806572908348822572611014624349564867920695408742679902,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2107426142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2107426142' seed=8192644374832894598057806572908348822572611014624349564867920695408742679902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8192644374832894598057806572908348822572611014624349564867920695408742679902 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"15.edn_tl_intg_err.59097676978088718332926118927994570947887553473444342216289382227691134980703","seed":59097676978088718332926118927994570947887553473444342216289382227691134980703,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3729723999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3729723999' seed=59097676978088718332926118927994570947887553473444342216289382227691134980703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59097676978088718332926118927994570947887553473444342216289382227691134980703 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"16.edn_genbits.110181365552942210229682318216975096914024525244616702837403535355258501994155","seed":110181365552942210229682318216975096914024525244616702837403535355258501994155,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2368870059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2368870059' seed=110181365552942210229682318216975096914024525244616702837403535355258501994155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110181365552942210229682318216975096914024525244616702837403535355258501994155 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"16.edn_stress_all_with_rand_reset.20325184902709793790186075122508403199513391535776035302545021072923398071401","seed":20325184902709793790186075122508403199513391535776035302545021072923398071401,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1361667177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1361667177' seed=20325184902709793790186075122508403199513391535776035302545021072923398071401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20325184902709793790186075122508403199513391535776035302545021072923398071401 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"16.edn_intr.46361148217224723678758296182791034842003425674591401390639531636416785367502","seed":46361148217224723678758296182791034842003425674591401390639531636416785367502,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1602437582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1602437582' seed=46361148217224723678758296182791034842003425674591401390639531636416785367502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46361148217224723678758296182791034842003425674591401390639531636416785367502 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"16.edn_alert.89310345239074736537457566111573483298287663244877957988858256328556040046478","seed":89310345239074736537457566111573483298287663244877957988858256328556040046478,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2352367502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2352367502' seed=89310345239074736537457566111573483298287663244877957988858256328556040046478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89310345239074736537457566111573483298287663244877957988858256328556040046478 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"16.edn_err.82694305523723205212949643427955644714298980020716318481929825937818809991219","seed":82694305523723205212949643427955644714298980020716318481929825937818809991219,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2470379571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2470379571' seed=82694305523723205212949643427955644714298980020716318481929825937818809991219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82694305523723205212949643427955644714298980020716318481929825937818809991219 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"16.edn_disable.32577854013144031455854323353208445091084051827124405611060350450070386872338","seed":32577854013144031455854323353208445091084051827124405611060350450070386872338,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3711668242 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3711668242' seed=32577854013144031455854323353208445091084051827124405611060350450070386872338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32577854013144031455854323353208445091084051827124405611060350450070386872338 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"16.edn_disable_auto_req_mode.61929005812205340887503249771817805718842294925011511538892616571806133785354","seed":61929005812205340887503249771817805718842294925011511538892616571806133785354,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=785388298 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.785388298' seed=61929005812205340887503249771817805718842294925011511538892616571806133785354 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61929005812205340887503249771817805718842294925011511538892616571806133785354 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"16.edn_tl_errors.74895782577284254963372576129836891103974140112207716257472223441173452509129","seed":74895782577284254963372576129836891103974140112207716257472223441173452509129,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054166985 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1054166985' seed=74895782577284254963372576129836891103974140112207716257472223441173452509129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74895782577284254963372576129836891103974140112207716257472223441173452509129 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"16.edn_tl_intg_err.6359985393800137322841302008499737218599296660151644701453890073628090573519","seed":6359985393800137322841302008499737218599296660151644701453890073628090573519,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1717314255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1717314255' seed=6359985393800137322841302008499737218599296660151644701453890073628090573519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6359985393800137322841302008499737218599296660151644701453890073628090573519 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/16.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"17.edn_genbits.82406579078684396740756737750537809170939738582311446016749981913773663401341","seed":82406579078684396740756737750537809170939738582311446016749981913773663401341,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1859728765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1859728765' seed=82406579078684396740756737750537809170939738582311446016749981913773663401341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82406579078684396740756737750537809170939738582311446016749981913773663401341 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"17.edn_stress_all_with_rand_reset.101299848554303660741979039149797551190070496545316467758783430014322778898465","seed":101299848554303660741979039149797551190070496545316467758783430014322778898465,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153944097 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.153944097' seed=101299848554303660741979039149797551190070496545316467758783430014322778898465 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101299848554303660741979039149797551190070496545316467758783430014322778898465 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"17.edn_intr.81785897663739919494221293824721925346239661905142894934749267336525796979580","seed":81785897663739919494221293824721925346239661905142894934749267336525796979580,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2297541500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2297541500' seed=81785897663739919494221293824721925346239661905142894934749267336525796979580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81785897663739919494221293824721925346239661905142894934749267336525796979580 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"17.edn_alert.56026435639811495856293126463184618425769495993260740646337337701883809946286","seed":56026435639811495856293126463184618425769495993260740646337337701883809946286,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591532206 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1591532206' seed=56026435639811495856293126463184618425769495993260740646337337701883809946286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56026435639811495856293126463184618425769495993260740646337337701883809946286 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"17.edn_err.84514170154079282180058381567765830198733640838879139668146675323044444473994","seed":84514170154079282180058381567765830198733640838879139668146675323044444473994,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4688522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4688522' seed=84514170154079282180058381567765830198733640838879139668146675323044444473994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84514170154079282180058381567765830198733640838879139668146675323044444473994 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"17.edn_disable.101262570988589163610146112434129567215445105075349232828870967718850083235087","seed":101262570988589163610146112434129567215445105075349232828870967718850083235087,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2566989071 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2566989071' seed=101262570988589163610146112434129567215445105075349232828870967718850083235087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101262570988589163610146112434129567215445105075349232828870967718850083235087 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"17.edn_disable_auto_req_mode.111836707835149113910999000601382350389579339890824221568587493424844852037214","seed":111836707835149113910999000601382350389579339890824221568587493424844852037214,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=990774878 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.990774878' seed=111836707835149113910999000601382350389579339890824221568587493424844852037214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111836707835149113910999000601382350389579339890824221568587493424844852037214 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"17.edn_tl_errors.40533539650688413173207648843932284230916996410444332357158856992479258848033","seed":40533539650688413173207648843932284230916996410444332357158856992479258848033,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4265585441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4265585441' seed=40533539650688413173207648843932284230916996410444332357158856992479258848033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40533539650688413173207648843932284230916996410444332357158856992479258848033 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"17.edn_tl_intg_err.114370889945847857584620558299231129016102037222647151561304114151980472159585","seed":114370889945847857584620558299231129016102037222647151561304114151980472159585,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295549281 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2295549281' seed=114370889945847857584620558299231129016102037222647151561304114151980472159585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114370889945847857584620558299231129016102037222647151561304114151980472159585 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"18.edn_genbits.67419698935997924899243404469266020585982866193886438831238374388347056869904","seed":67419698935997924899243404469266020585982866193886438831238374388347056869904,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3233206800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3233206800' seed=67419698935997924899243404469266020585982866193886438831238374388347056869904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67419698935997924899243404469266020585982866193886438831238374388347056869904 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"18.edn_stress_all_with_rand_reset.68841427347304975558036969769976023217049103641586196128599406043399703222034","seed":68841427347304975558036969769976023217049103641586196128599406043399703222034,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846873362 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2846873362' seed=68841427347304975558036969769976023217049103641586196128599406043399703222034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68841427347304975558036969769976023217049103641586196128599406043399703222034 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"18.edn_intr.31892382034551270636816086588454280147582640139830378744673542351405290628138","seed":31892382034551270636816086588454280147582640139830378744673542351405290628138,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2158765098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2158765098' seed=31892382034551270636816086588454280147582640139830378744673542351405290628138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31892382034551270636816086588454280147582640139830378744673542351405290628138 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"18.edn_alert.58073836565873759359937946845956659713729553904664467797140490566865159151111","seed":58073836565873759359937946845956659713729553904664467797140490566865159151111,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=238247431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.238247431' seed=58073836565873759359937946845956659713729553904664467797140490566865159151111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58073836565873759359937946845956659713729553904664467797140490566865159151111 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"18.edn_err.84334069461514946445707056835903982651420292756930532241661476606807242901315","seed":84334069461514946445707056835903982651420292756930532241661476606807242901315,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776120643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3776120643' seed=84334069461514946445707056835903982651420292756930532241661476606807242901315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84334069461514946445707056835903982651420292756930532241661476606807242901315 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"18.edn_disable.102043236378607785645857700463050980999549724544762125926999654506821041299062","seed":102043236378607785645857700463050980999549724544762125926999654506821041299062,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=372809334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.372809334' seed=102043236378607785645857700463050980999549724544762125926999654506821041299062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102043236378607785645857700463050980999549724544762125926999654506821041299062 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"18.edn_disable_auto_req_mode.111220946345052342370141438709813818631944282517149051016447644656686378070448","seed":111220946345052342370141438709813818631944282517149051016447644656686378070448,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3326161328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.3326161328' seed=111220946345052342370141438709813818631944282517149051016447644656686378070448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111220946345052342370141438709813818631944282517149051016447644656686378070448 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"18.edn_tl_errors.59956456824684258315538669194412308358896404584418574242710008589105017391048","seed":59956456824684258315538669194412308358896404584418574242710008589105017391048,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511524296 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1511524296' seed=59956456824684258315538669194412308358896404584418574242710008589105017391048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59956456824684258315538669194412308358896404584418574242710008589105017391048 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"18.edn_tl_intg_err.59274641807526535070199848808624274216558842283754077974323499681026026021085","seed":59274641807526535070199848808624274216558842283754077974323499681026026021085,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2654249181 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2654249181' seed=59274641807526535070199848808624274216558842283754077974323499681026026021085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59274641807526535070199848808624274216558842283754077974323499681026026021085 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"19.edn_genbits.21318222351686402087033361689815432786015892463759542974274540114972613990642","seed":21318222351686402087033361689815432786015892463759542974274540114972613990642,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1548671218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1548671218' seed=21318222351686402087033361689815432786015892463759542974274540114972613990642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21318222351686402087033361689815432786015892463759542974274540114972613990642 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"19.edn_stress_all_with_rand_reset.94554779627952383355548492726782788944898305585931206524909553957606859627460","seed":94554779627952383355548492726782788944898305585931206524909553957606859627460,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3172096964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3172096964' seed=94554779627952383355548492726782788944898305585931206524909553957606859627460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94554779627952383355548492726782788944898305585931206524909553957606859627460 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_intr","qual_name":"19.edn_intr.27344412146334894720691625437790496286902838553319545524906070207276447830859","seed":27344412146334894720691625437790496286902838553319545524906070207276447830859,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_intr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2377782091 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2377782091' seed=27344412146334894720691625437790496286902838553319545524906070207276447830859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27344412146334894720691625437790496286902838553319545524906070207276447830859 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"19.edn_alert.69033688962602768553793495067419798885559035896678596998799885739867201730561","seed":69033688962602768553793495067419798885559035896678596998799885739867201730561,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241618945 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4241618945' seed=69033688962602768553793495067419798885559035896678596998799885739867201730561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69033688962602768553793495067419798885559035896678596998799885739867201730561 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"19.edn_err.31576851790742617449278382848143813014282751590265415240901270370531814320374","seed":31576851790742617449278382848143813014282751590265415240901270370531814320374,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1920641270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1920641270' seed=31576851790742617449278382848143813014282751590265415240901270370531814320374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31576851790742617449278382848143813014282751590265415240901270370531814320374 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"19.edn_disable.110114487453276830526266061171538880493638894139667869048615178009396857409993","seed":110114487453276830526266061171538880493638894139667869048615178009396857409993,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244978121 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.244978121' seed=110114487453276830526266061171538880493638894139667869048615178009396857409993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110114487453276830526266061171538880493638894139667869048615178009396857409993 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"19.edn_disable_auto_req_mode.72757467389325942190730005728429753240201072355287182618710993955908559301749","seed":72757467389325942190730005728429753240201072355287182618710993955908559301749,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021021813 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.4021021813' seed=72757467389325942190730005728429753240201072355287182618710993955908559301749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72757467389325942190730005728429753240201072355287182618710993955908559301749 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"19.edn_tl_errors.92549830460339319774443392809165386913901230739425576477307973885091483595781","seed":92549830460339319774443392809165386913901230739425576477307973885091483595781,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727640581 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1727640581' seed=92549830460339319774443392809165386913901230739425576477307973885091483595781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92549830460339319774443392809165386913901230739425576477307973885091483595781 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"19.edn_tl_intg_err.66935851240309913134604431091004155524946016412176110859935930919052056731353","seed":66935851240309913134604431091004155524946016412176110859935930919052056731353,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=597171929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.597171929' seed=66935851240309913134604431091004155524946016412176110859935930919052056731353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66935851240309913134604431091004155524946016412176110859935930919052056731353 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"20.edn_genbits.3509106083231900181765258185647208462891896657756267059445707724257715900763","seed":3509106083231900181765258185647208462891896657756267059445707724257715900763,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113856859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.113856859' seed=3509106083231900181765258185647208462891896657756267059445707724257715900763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3509106083231900181765258185647208462891896657756267059445707724257715900763 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"20.edn_stress_all_with_rand_reset.81746070589570527728224961473105710706242405545501765088117673664661645732584","seed":81746070589570527728224961473105710706242405545501765088117673664661645732584,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869575400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.869575400' seed=81746070589570527728224961473105710706242405545501765088117673664661645732584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81746070589570527728224961473105710706242405545501765088117673664661645732584 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"20.edn_alert.83297276064139283079553749372170201835520125652769717037476940042604640784396","seed":83297276064139283079553749372170201835520125652769717037476940042604640784396,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083732492 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4083732492' seed=83297276064139283079553749372170201835520125652769717037476940042604640784396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83297276064139283079553749372170201835520125652769717037476940042604640784396 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"20.edn_err.89281324011072876110157414464077876782202755957636949796023335207231572807193","seed":89281324011072876110157414464077876782202755957636949796023335207231572807193,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=881200665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.881200665' seed=89281324011072876110157414464077876782202755957636949796023335207231572807193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89281324011072876110157414464077876782202755957636949796023335207231572807193 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"20.edn_disable.81345042773845472030772707253372454371519769889420744767126869620991027822147","seed":81345042773845472030772707253372454371519769889420744767126869620991027822147,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1074249283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1074249283' seed=81345042773845472030772707253372454371519769889420744767126869620991027822147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81345042773845472030772707253372454371519769889420744767126869620991027822147 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"20.edn_disable_auto_req_mode.81440725604385942480667237447962011870285077613550980401239183044531521499220","seed":81440725604385942480667237447962011870285077613550980401239183044531521499220,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442937428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.442937428' seed=81440725604385942480667237447962011870285077613550980401239183044531521499220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81440725604385942480667237447962011870285077613550980401239183044531521499220 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"20.edn_tl_errors.36736202828477202840389818484375799076449109903632441659410763179521412238277","seed":36736202828477202840389818484375799076449109903632441659410763179521412238277,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=917048261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_tl_errors.917048261' seed=36736202828477202840389818484375799076449109903632441659410763179521412238277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36736202828477202840389818484375799076449109903632441659410763179521412238277 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"20.edn_tl_intg_err.61151860229741575776789913564092830039942814278658462707148394471548713727819","seed":61151860229741575776789913564092830039942814278658462707148394471548713727819,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2395240267 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_tl_intg_err.2395240267' seed=61151860229741575776789913564092830039942814278658462707148394471548713727819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61151860229741575776789913564092830039942814278658462707148394471548713727819 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"21.edn_genbits.4683406308978826980659822314371190902866768976463156379520737672786060947141","seed":4683406308978826980659822314371190902866768976463156379520737672786060947141,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3819089605 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3819089605' seed=4683406308978826980659822314371190902866768976463156379520737672786060947141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4683406308978826980659822314371190902866768976463156379520737672786060947141 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"21.edn_stress_all_with_rand_reset.84988460887834877852809575564121506270361195415336323099943706522374158634418","seed":84988460887834877852809575564121506270361195415336323099943706522374158634418,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903040434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.903040434' seed=84988460887834877852809575564121506270361195415336323099943706522374158634418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84988460887834877852809575564121506270361195415336323099943706522374158634418 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"21.edn_alert.72962970456027061365414214176366261601629048976062635712436027372618827466392","seed":72962970456027061365414214176366261601629048976062635712436027372618827466392,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1142458008 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1142458008' seed=72962970456027061365414214176366261601629048976062635712436027372618827466392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72962970456027061365414214176366261601629048976062635712436027372618827466392 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"21.edn_err.38451704287692670799585430672173756572485611368807108137351343577739231628447","seed":38451704287692670799585430672173756572485611368807108137351343577739231628447,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358485151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.358485151' seed=38451704287692670799585430672173756572485611368807108137351343577739231628447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38451704287692670799585430672173756572485611368807108137351343577739231628447 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"21.edn_disable.79449004972028929719009165665198342752997892510701402220031088116624820720698","seed":79449004972028929719009165665198342752997892510701402220031088116624820720698,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2849690682 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2849690682' seed=79449004972028929719009165665198342752997892510701402220031088116624820720698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79449004972028929719009165665198342752997892510701402220031088116624820720698 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"21.edn_disable_auto_req_mode.17570845117444707480581714087434237467227928701530344597405867266511219955543","seed":17570845117444707480581714087434237467227928701530344597405867266511219955543,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3945764695 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.3945764695' seed=17570845117444707480581714087434237467227928701530344597405867266511219955543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17570845117444707480581714087434237467227928701530344597405867266511219955543 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"21.edn_tl_errors.29393229887544393386078368973873658141232893414275923856624464359293796732955","seed":29393229887544393386078368973873658141232893414275923856624464359293796732955,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3769094171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_tl_errors.3769094171' seed=29393229887544393386078368973873658141232893414275923856624464359293796732955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29393229887544393386078368973873658141232893414275923856624464359293796732955 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"21.edn_tl_intg_err.10000269523353985050695730247347771744529097486531000442825817572534113699815","seed":10000269523353985050695730247347771744529097486531000442825817572534113699815,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3816458215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_tl_intg_err.3816458215' seed=10000269523353985050695730247347771744529097486531000442825817572534113699815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10000269523353985050695730247347771744529097486531000442825817572534113699815 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"22.edn_genbits.13264607592060437680757144471925145793200545812742088024884851803979537174233","seed":13264607592060437680757144471925145793200545812742088024884851803979537174233,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128858841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2128858841' seed=13264607592060437680757144471925145793200545812742088024884851803979537174233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13264607592060437680757144471925145793200545812742088024884851803979537174233 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"22.edn_stress_all_with_rand_reset.70818255390086703271592471347443871060081360962644576404142908538166723731786","seed":70818255390086703271592471347443871060081360962644576404142908538166723731786,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2993414474 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2993414474' seed=70818255390086703271592471347443871060081360962644576404142908538166723731786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70818255390086703271592471347443871060081360962644576404142908538166723731786 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"22.edn_alert.71205772615609028241889858335208678257128568286661313124367635477302586983724","seed":71205772615609028241889858335208678257128568286661313124367635477302586983724,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2455848236 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2455848236' seed=71205772615609028241889858335208678257128568286661313124367635477302586983724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71205772615609028241889858335208678257128568286661313124367635477302586983724 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"22.edn_err.95874470273254882783224798429351502947894110192715220252553438298081092835870","seed":95874470273254882783224798429351502947894110192715220252553438298081092835870,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1707743774 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1707743774' seed=95874470273254882783224798429351502947894110192715220252553438298081092835870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95874470273254882783224798429351502947894110192715220252553438298081092835870 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"22.edn_disable.18346321096005459212805296165865230798871304032190138027561142337659847692027","seed":18346321096005459212805296165865230798871304032190138027561142337659847692027,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1013305083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1013305083' seed=18346321096005459212805296165865230798871304032190138027561142337659847692027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18346321096005459212805296165865230798871304032190138027561142337659847692027 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"22.edn_disable_auto_req_mode.25675429823049190095229998001595073029509374214110957380153971221569305893851","seed":25675429823049190095229998001595073029509374214110957380153971221569305893851,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2851134427 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.2851134427' seed=25675429823049190095229998001595073029509374214110957380153971221569305893851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25675429823049190095229998001595073029509374214110957380153971221569305893851 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"22.edn_tl_errors.29466606801790762923357549530118237435901354716447028614122865835524874512876","seed":29466606801790762923357549530118237435901354716447028614122865835524874512876,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4218890732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_tl_errors.4218890732' seed=29466606801790762923357549530118237435901354716447028614122865835524874512876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29466606801790762923357549530118237435901354716447028614122865835524874512876 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"22.edn_tl_intg_err.2716190299609042219321033152584930945264667063070521579727205644321210797754","seed":2716190299609042219321033152584930945264667063070521579727205644321210797754,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706331834 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_tl_intg_err.1706331834' seed=2716190299609042219321033152584930945264667063070521579727205644321210797754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2716190299609042219321033152584930945264667063070521579727205644321210797754 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"23.edn_genbits.102823242082754207531732007458800157965486588484502222586436984625833292656631","seed":102823242082754207531732007458800157965486588484502222586436984625833292656631,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299143671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3299143671' seed=102823242082754207531732007458800157965486588484502222586436984625833292656631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102823242082754207531732007458800157965486588484502222586436984625833292656631 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"23.edn_stress_all_with_rand_reset.29984943168998560057459896301484223764762174928009315108859235727458324160933","seed":29984943168998560057459896301484223764762174928009315108859235727458324160933,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3024331173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3024331173' seed=29984943168998560057459896301484223764762174928009315108859235727458324160933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29984943168998560057459896301484223764762174928009315108859235727458324160933 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"23.edn_alert.114784331459631826781849832678198554273809630403869092379981945600341883753957","seed":114784331459631826781849832678198554273809630403869092379981945600341883753957,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1787565541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1787565541' seed=114784331459631826781849832678198554273809630403869092379981945600341883753957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114784331459631826781849832678198554273809630403869092379981945600341883753957 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"23.edn_err.13556588852829463187233243250007840758799441827347295386236082156900282272017","seed":13556588852829463187233243250007840758799441827347295386236082156900282272017,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3046902033 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3046902033' seed=13556588852829463187233243250007840758799441827347295386236082156900282272017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13556588852829463187233243250007840758799441827347295386236082156900282272017 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"23.edn_disable.114861426716552388462251637233118182016565196267143402099112824198401767430819","seed":114861426716552388462251637233118182016565196267143402099112824198401767430819,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748321955 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3748321955' seed=114861426716552388462251637233118182016565196267143402099112824198401767430819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114861426716552388462251637233118182016565196267143402099112824198401767430819 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"23.edn_disable_auto_req_mode.34009425724548325064436454943042967438196163359669602029792343291998594670653","seed":34009425724548325064436454943042967438196163359669602029792343291998594670653,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3052937277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.3052937277' seed=34009425724548325064436454943042967438196163359669602029792343291998594670653 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34009425724548325064436454943042967438196163359669602029792343291998594670653 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"23.edn_tl_errors.61757426350931865202991434798582656995555891889871750524264435523952205787271","seed":61757426350931865202991434798582656995555891889871750524264435523952205787271,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3003543687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_tl_errors.3003543687' seed=61757426350931865202991434798582656995555891889871750524264435523952205787271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61757426350931865202991434798582656995555891889871750524264435523952205787271 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"23.edn_tl_intg_err.81189191624696110768125764444370900365410371069795404173756346904428996377486","seed":81189191624696110768125764444370900365410371069795404173756346904428996377486,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=247905166 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_tl_intg_err.247905166' seed=81189191624696110768125764444370900365410371069795404173756346904428996377486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81189191624696110768125764444370900365410371069795404173756346904428996377486 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"24.edn_genbits.80703106590821188800979847148210949422030399546568573156812377356252900268689","seed":80703106590821188800979847148210949422030399546568573156812377356252900268689,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2006227601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2006227601' seed=80703106590821188800979847148210949422030399546568573156812377356252900268689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80703106590821188800979847148210949422030399546568573156812377356252900268689 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"24.edn_stress_all_with_rand_reset.110396639403291164013754875709456662910770732866807020954342796062158309669325","seed":110396639403291164013754875709456662910770732866807020954342796062158309669325,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1627765197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1627765197' seed=110396639403291164013754875709456662910770732866807020954342796062158309669325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110396639403291164013754875709456662910770732866807020954342796062158309669325 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"24.edn_alert.33722589769672737207932745801761729391007256825882042686261943766015889762002","seed":33722589769672737207932745801761729391007256825882042686261943766015889762002,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=602269394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.602269394' seed=33722589769672737207932745801761729391007256825882042686261943766015889762002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33722589769672737207932745801761729391007256825882042686261943766015889762002 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"24.edn_err.85543598800448862114068137499867611319611625499038759868312287247488400436333","seed":85543598800448862114068137499867611319611625499038759868312287247488400436333,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4229639277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4229639277' seed=85543598800448862114068137499867611319611625499038759868312287247488400436333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85543598800448862114068137499867611319611625499038759868312287247488400436333 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"24.edn_disable.20147127835513339981147990673454384950560750672881445358610607378956103141986","seed":20147127835513339981147990673454384950560750672881445358610607378956103141986,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214625378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3214625378' seed=20147127835513339981147990673454384950560750672881445358610607378956103141986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20147127835513339981147990673454384950560750672881445358610607378956103141986 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"24.edn_disable_auto_req_mode.26438813467175960539055797648025881608051622593747240266040898256360752371028","seed":26438813467175960539055797648025881608051622593747240266040898256360752371028,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170298196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.1170298196' seed=26438813467175960539055797648025881608051622593747240266040898256360752371028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26438813467175960539055797648025881608051622593747240266040898256360752371028 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_errors","qual_name":"24.edn_tl_errors.70998949158036556640901854242362796619252026300102505883561237002345441143976","seed":70998949158036556640901854242362796619252026300102505883561237002345441143976,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1610099880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_tl_errors.1610099880' seed=70998949158036556640901854242362796619252026300102505883561237002345441143976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70998949158036556640901854242362796619252026300102505883561237002345441143976 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_tl_intg_err","qual_name":"24.edn_tl_intg_err.70755595754942781993051068717192095219605190158598249030843504068922785104340","seed":70755595754942781993051068717192095219605190158598249030843504068922785104340,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=318210516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_tl_intg_err.318210516' seed=70755595754942781993051068717192095219605190158598249030843504068922785104340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70755595754942781993051068717192095219605190158598249030843504068922785104340 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"25.edn_genbits.107123868079229580876838212203757738851028707574367564767073229110680864279085","seed":107123868079229580876838212203757738851028707574367564767073229110680864279085,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557673517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3557673517' seed=107123868079229580876838212203757738851028707574367564767073229110680864279085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107123868079229580876838212203757738851028707574367564767073229110680864279085 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"25.edn_stress_all_with_rand_reset.15655630414926318356924373567054633198282092568599926872727365963745000221393","seed":15655630414926318356924373567054633198282092568599926872727365963745000221393,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=828697297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.828697297' seed=15655630414926318356924373567054633198282092568599926872727365963745000221393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15655630414926318356924373567054633198282092568599926872727365963745000221393 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"25.edn_alert.95235399509976540364901359907239006199617022854325232533545430536296189739854","seed":95235399509976540364901359907239006199617022854325232533545430536296189739854,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3293659982 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3293659982' seed=95235399509976540364901359907239006199617022854325232533545430536296189739854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95235399509976540364901359907239006199617022854325232533545430536296189739854 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"25.edn_err.114830554121535974926270824028909354859145907861331198679839648061075202774899","seed":114830554121535974926270824028909354859145907861331198679839648061075202774899,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=357832563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.357832563' seed=114830554121535974926270824028909354859145907861331198679839648061075202774899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114830554121535974926270824028909354859145907861331198679839648061075202774899 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"25.edn_disable.8821770422659614465960034007386631103150093561545088635793185288850311082700","seed":8821770422659614465960034007386631103150093561545088635793185288850311082700,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202399436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2202399436' seed=8821770422659614465960034007386631103150093561545088635793185288850311082700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8821770422659614465960034007386631103150093561545088635793185288850311082700 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"25.edn_disable_auto_req_mode.63195099132932874677933774530601455873157928035991144564620968982032216355521","seed":63195099132932874677933774530601455873157928035991144564620968982032216355521,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2259546817 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2259546817' seed=63195099132932874677933774530601455873157928035991144564620968982032216355521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63195099132932874677933774530601455873157928035991144564620968982032216355521 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"26.edn_genbits.98771871147478074192589096051572011962334497706652951251420363001707181044072","seed":98771871147478074192589096051572011962334497706652951251420363001707181044072,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2136142184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2136142184' seed=98771871147478074192589096051572011962334497706652951251420363001707181044072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98771871147478074192589096051572011962334497706652951251420363001707181044072 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"26.edn_stress_all_with_rand_reset.17893983024581822602596300044721967917269906778485042941190857578851698061021","seed":17893983024581822602596300044721967917269906778485042941190857578851698061021,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112307933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.112307933' seed=17893983024581822602596300044721967917269906778485042941190857578851698061021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17893983024581822602596300044721967917269906778485042941190857578851698061021 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"26.edn_alert.48481379582792585815538906993182387700608258074841333894718845953072178784460","seed":48481379582792585815538906993182387700608258074841333894718845953072178784460,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1310058700 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1310058700' seed=48481379582792585815538906993182387700608258074841333894718845953072178784460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48481379582792585815538906993182387700608258074841333894718845953072178784460 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"26.edn_err.23742080054492617641238541773450535993727538084091153372706975968732125178459","seed":23742080054492617641238541773450535993727538084091153372706975968732125178459,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3917326939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3917326939' seed=23742080054492617641238541773450535993727538084091153372706975968732125178459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23742080054492617641238541773450535993727538084091153372706975968732125178459 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"26.edn_disable.93533143816365773350617641849030948286692567235056921235313519728142845284883","seed":93533143816365773350617641849030948286692567235056921235313519728142845284883,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3308589587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3308589587' seed=93533143816365773350617641849030948286692567235056921235313519728142845284883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93533143816365773350617641849030948286692567235056921235313519728142845284883 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"26.edn_disable_auto_req_mode.99359007213819931232785869983139156650083891361073017547798212576132447195877","seed":99359007213819931232785869983139156650083891361073017547798212576132447195877,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1356190437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.1356190437' seed=99359007213819931232785869983139156650083891361073017547798212576132447195877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99359007213819931232785869983139156650083891361073017547798212576132447195877 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"27.edn_genbits.4039121555004361954569995943520755256559869880147740231402138765327281609785","seed":4039121555004361954569995943520755256559869880147740231402138765327281609785,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3509247033 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3509247033' seed=4039121555004361954569995943520755256559869880147740231402138765327281609785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4039121555004361954569995943520755256559869880147740231402138765327281609785 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"27.edn_stress_all_with_rand_reset.114317524801043430779551887963972839017351856056837059902581340899071556891382","seed":114317524801043430779551887963972839017351856056837059902581340899071556891382,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=823964406 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.823964406' seed=114317524801043430779551887963972839017351856056837059902581340899071556891382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114317524801043430779551887963972839017351856056837059902581340899071556891382 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"27.edn_alert.44671502866119913934724123628368400273135212100437677830235152584852292447628","seed":44671502866119913934724123628368400273135212100437677830235152584852292447628,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676698508 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2676698508' seed=44671502866119913934724123628368400273135212100437677830235152584852292447628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44671502866119913934724123628368400273135212100437677830235152584852292447628 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"27.edn_err.57357229069451349312209951950189395096607724075202183380381718520137435419481","seed":57357229069451349312209951950189395096607724075202183380381718520137435419481,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2418119513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2418119513' seed=57357229069451349312209951950189395096607724075202183380381718520137435419481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57357229069451349312209951950189395096607724075202183380381718520137435419481 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"27.edn_disable.9223259805966461450812063268884463019363848101362132890822085759245726251963","seed":9223259805966461450812063268884463019363848101362132890822085759245726251963,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688913339 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.688913339' seed=9223259805966461450812063268884463019363848101362132890822085759245726251963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9223259805966461450812063268884463019363848101362132890822085759245726251963 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"27.edn_disable_auto_req_mode.44796519433376983051945791695268824728160245735945330605398608986693735324373","seed":44796519433376983051945791695268824728160245735945330605398608986693735324373,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037057237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.4037057237' seed=44796519433376983051945791695268824728160245735945330605398608986693735324373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44796519433376983051945791695268824728160245735945330605398608986693735324373 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"28.edn_genbits.91090903348596984511936489732494100019136710659315436523968393820090098821772","seed":91090903348596984511936489732494100019136710659315436523968393820090098821772,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052813964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1052813964' seed=91090903348596984511936489732494100019136710659315436523968393820090098821772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91090903348596984511936489732494100019136710659315436523968393820090098821772 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"28.edn_stress_all_with_rand_reset.83819314808311279826021630925716332050133326613447370461978424559645690842615","seed":83819314808311279826021630925716332050133326613447370461978424559645690842615,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286991863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.4286991863' seed=83819314808311279826021630925716332050133326613447370461978424559645690842615 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83819314808311279826021630925716332050133326613447370461978424559645690842615 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"28.edn_alert.65602212309450356421977995866588016304823342583845476332933019968665280345912","seed":65602212309450356421977995866588016304823342583845476332933019968665280345912,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3684726584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3684726584' seed=65602212309450356421977995866588016304823342583845476332933019968665280345912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65602212309450356421977995866588016304823342583845476332933019968665280345912 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"28.edn_err.15680508974418118820047820706334601319048779348068021048878193682275693711865","seed":15680508974418118820047820706334601319048779348068021048878193682275693711865,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2516275705 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2516275705' seed=15680508974418118820047820706334601319048779348068021048878193682275693711865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15680508974418118820047820706334601319048779348068021048878193682275693711865 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"28.edn_disable.19027523791477786408952196789177384852587197141144839603016861181781078013581","seed":19027523791477786408952196789177384852587197141144839603016861181781078013581,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2756802189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2756802189' seed=19027523791477786408952196789177384852587197141144839603016861181781078013581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19027523791477786408952196789177384852587197141144839603016861181781078013581 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"28.edn_disable_auto_req_mode.79048014466751114323706770287892094182200440296366952200417880476334384923674","seed":79048014466751114323706770287892094182200440296366952200417880476334384923674,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2802500634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2802500634' seed=79048014466751114323706770287892094182200440296366952200417880476334384923674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79048014466751114323706770287892094182200440296366952200417880476334384923674 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"29.edn_genbits.27581386304688994363270059337345482236507407078294056744770854173064397384355","seed":27581386304688994363270059337345482236507407078294056744770854173064397384355,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65333923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.65333923' seed=27581386304688994363270059337345482236507407078294056744770854173064397384355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27581386304688994363270059337345482236507407078294056744770854173064397384355 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"29.edn_stress_all_with_rand_reset.63011402372498439630957977631707403583255872235030562616948592096285994400242","seed":63011402372498439630957977631707403583255872235030562616948592096285994400242,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1356216818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1356216818' seed=63011402372498439630957977631707403583255872235030562616948592096285994400242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63011402372498439630957977631707403583255872235030562616948592096285994400242 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"29.edn_alert.81016493671925325058757578172609212126496730629029613705409347815258755513391","seed":81016493671925325058757578172609212126496730629029613705409347815258755513391,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603536431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.603536431' seed=81016493671925325058757578172609212126496730629029613705409347815258755513391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81016493671925325058757578172609212126496730629029613705409347815258755513391 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"29.edn_err.44383390438656324324902950262300028590739902348244689404583318821068234987458","seed":44383390438656324324902950262300028590739902348244689404583318821068234987458,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169149378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2169149378' seed=44383390438656324324902950262300028590739902348244689404583318821068234987458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44383390438656324324902950262300028590739902348244689404583318821068234987458 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"29.edn_disable.27776181254758972333595667694829254326485228265145001539667493969136455557788","seed":27776181254758972333595667694829254326485228265145001539667493969136455557788,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=568107676 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.568107676' seed=27776181254758972333595667694829254326485228265145001539667493969136455557788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27776181254758972333595667694829254326485228265145001539667493969136455557788 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"29.edn_disable_auto_req_mode.80669055418605196109475532871454062012629173180497973363548317586314678555816","seed":80669055418605196109475532871454062012629173180497973363548317586314678555816,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1675678888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1675678888' seed=80669055418605196109475532871454062012629173180497973363548317586314678555816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80669055418605196109475532871454062012629173180497973363548317586314678555816 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"30.edn_genbits.19277662220113400744643288768531255241520991467505373852194359064243796609481","seed":19277662220113400744643288768531255241520991467505373852194359064243796609481,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3260189129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3260189129' seed=19277662220113400744643288768531255241520991467505373852194359064243796609481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19277662220113400744643288768531255241520991467505373852194359064243796609481 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"30.edn_alert.102639551966230625542010056939116218588376724374457213462084525750605882601027","seed":102639551966230625542010056939116218588376724374457213462084525750605882601027,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1185164867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1185164867' seed=102639551966230625542010056939116218588376724374457213462084525750605882601027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102639551966230625542010056939116218588376724374457213462084525750605882601027 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"30.edn_err.94726606925577246854540170946525611974725306593411812288427590901203095819005","seed":94726606925577246854540170946525611974725306593411812288427590901203095819005,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2142016253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2142016253' seed=94726606925577246854540170946525611974725306593411812288427590901203095819005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94726606925577246854540170946525611974725306593411812288427590901203095819005 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"30.edn_disable.42626287274392174303742029309316915916048234828592869192313232356039758629219","seed":42626287274392174303742029309316915916048234828592869192313232356039758629219,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4051618147 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4051618147' seed=42626287274392174303742029309316915916048234828592869192313232356039758629219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42626287274392174303742029309316915916048234828592869192313232356039758629219 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"30.edn_disable_auto_req_mode.73651396665746958848626090796739757815763382321515084289237559956396562571827","seed":73651396665746958848626090796739757815763382321515084289237559956396562571827,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1359340083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1359340083' seed=73651396665746958848626090796739757815763382321515084289237559956396562571827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73651396665746958848626090796739757815763382321515084289237559956396562571827 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"31.edn_genbits.98511275922266663523415700874396763184309121930584503997654775444256157185613","seed":98511275922266663523415700874396763184309121930584503997654775444256157185613,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=83211853 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.83211853' seed=98511275922266663523415700874396763184309121930584503997654775444256157185613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98511275922266663523415700874396763184309121930584503997654775444256157185613 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"31.edn_alert.37161862689166152460475177955332437064931083907311724049486563207759292808166","seed":37161862689166152460475177955332437064931083907311724049486563207759292808166,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1809595366 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1809595366' seed=37161862689166152460475177955332437064931083907311724049486563207759292808166 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37161862689166152460475177955332437064931083907311724049486563207759292808166 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"31.edn_err.90473150702769517885707663631831053515794739401599712329833805783887689514276","seed":90473150702769517885707663631831053515794739401599712329833805783887689514276,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3749412132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3749412132' seed=90473150702769517885707663631831053515794739401599712329833805783887689514276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90473150702769517885707663631831053515794739401599712329833805783887689514276 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"31.edn_disable.48300457165638179140077191077436505174727748923763790973250545615138548786014","seed":48300457165638179140077191077436505174727748923763790973250545615138548786014,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2433655646 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2433655646' seed=48300457165638179140077191077436505174727748923763790973250545615138548786014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48300457165638179140077191077436505174727748923763790973250545615138548786014 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"31.edn_disable_auto_req_mode.65334543705157145998961837021709073648413081718489149802750220749713497445076","seed":65334543705157145998961837021709073648413081718489149802750220749713497445076,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=377541332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.377541332' seed=65334543705157145998961837021709073648413081718489149802750220749713497445076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65334543705157145998961837021709073648413081718489149802750220749713497445076 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"32.edn_genbits.4136962189467490539556570384293888069065070665712831042573419432523629642065","seed":4136962189467490539556570384293888069065070665712831042573419432523629642065,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3259285841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3259285841' seed=4136962189467490539556570384293888069065070665712831042573419432523629642065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4136962189467490539556570384293888069065070665712831042573419432523629642065 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"32.edn_alert.88429167411104671626104658365890712119159978362736908250601851128100028570916","seed":88429167411104671626104658365890712119159978362736908250601851128100028570916,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1251106084 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1251106084' seed=88429167411104671626104658365890712119159978362736908250601851128100028570916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88429167411104671626104658365890712119159978362736908250601851128100028570916 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"32.edn_err.27962374181049128564498798674746112154255486213539132417024361481697527705242","seed":27962374181049128564498798674746112154255486213539132417024361481697527705242,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576119962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1576119962' seed=27962374181049128564498798674746112154255486213539132417024361481697527705242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27962374181049128564498798674746112154255486213539132417024361481697527705242 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"32.edn_disable.3708800465339184913841011132570734286669631861159716256023916665072462173346","seed":3708800465339184913841011132570734286669631861159716256023916665072462173346,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605656226 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.605656226' seed=3708800465339184913841011132570734286669631861159716256023916665072462173346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3708800465339184913841011132570734286669631861159716256023916665072462173346 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.37137238927156931194735475291142891995190003599066175941912476072225330193715","seed":37137238927156931194735475291142891995190003599066175941912476072225330193715,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3952895283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.3952895283' seed=37137238927156931194735475291142891995190003599066175941912476072225330193715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37137238927156931194735475291142891995190003599066175941912476072225330193715 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"33.edn_genbits.44825881237754794584259250464739278287112118533892967697517710386688315540613","seed":44825881237754794584259250464739278287112118533892967697517710386688315540613,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3620390021 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3620390021' seed=44825881237754794584259250464739278287112118533892967697517710386688315540613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44825881237754794584259250464739278287112118533892967697517710386688315540613 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"33.edn_alert.101406167082815858235617759527453607188743832267365378908921684027804269362346","seed":101406167082815858235617759527453607188743832267365378908921684027804269362346,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171654314 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.171654314' seed=101406167082815858235617759527453607188743832267365378908921684027804269362346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101406167082815858235617759527453607188743832267365378908921684027804269362346 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"33.edn_err.74953783552163527176073621351891628287025522181542229833813925295435177190825","seed":74953783552163527176073621351891628287025522181542229833813925295435177190825,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=842720681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.842720681' seed=74953783552163527176073621351891628287025522181542229833813925295435177190825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74953783552163527176073621351891628287025522181542229833813925295435177190825 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"33.edn_disable.30627655841380182542557394310072587699653744631895410301255061847529263145819","seed":30627655841380182542557394310072587699653744631895410301255061847529263145819,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018372955 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1018372955' seed=30627655841380182542557394310072587699653744631895410301255061847529263145819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30627655841380182542557394310072587699653744631895410301255061847529263145819 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"33.edn_disable_auto_req_mode.104305582008186794715817328102209065731549550514338244444350582447071242705754","seed":104305582008186794715817328102209065731549550514338244444350582447071242705754,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3122355034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.3122355034' seed=104305582008186794715817328102209065731549550514338244444350582447071242705754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104305582008186794715817328102209065731549550514338244444350582447071242705754 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"34.edn_genbits.81151531947262354353224442045147416660340769941238499276152143982966027961313","seed":81151531947262354353224442045147416660340769941238499276152143982966027961313,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3534603233 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3534603233' seed=81151531947262354353224442045147416660340769941238499276152143982966027961313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81151531947262354353224442045147416660340769941238499276152143982966027961313 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"34.edn_alert.79594955612975580190465414011489650664595179864225417819125726167714618368323","seed":79594955612975580190465414011489650664595179864225417819125726167714618368323,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212716867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2212716867' seed=79594955612975580190465414011489650664595179864225417819125726167714618368323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79594955612975580190465414011489650664595179864225417819125726167714618368323 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"34.edn_err.27668292464483497388201706148478560895682594236414343209608265046931842459872","seed":27668292464483497388201706148478560895682594236414343209608265046931842459872,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4066830560 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4066830560' seed=27668292464483497388201706148478560895682594236414343209608265046931842459872 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27668292464483497388201706148478560895682594236414343209608265046931842459872 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"34.edn_disable.44608704285511832069579017439624194236903377255493541063521364708440567155038","seed":44608704285511832069579017439624194236903377255493541063521364708440567155038,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=796625246 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.796625246' seed=44608704285511832069579017439624194236903377255493541063521364708440567155038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44608704285511832069579017439624194236903377255493541063521364708440567155038 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"34.edn_disable_auto_req_mode.84480349331372206932436539348411329764088317426283673346508557585733737661873","seed":84480349331372206932436539348411329764088317426283673346508557585733737661873,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2398242225 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.2398242225' seed=84480349331372206932436539348411329764088317426283673346508557585733737661873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84480349331372206932436539348411329764088317426283673346508557585733737661873 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"35.edn_genbits.88941464859304624725088512719018644240551614743857312017926280352856935121401","seed":88941464859304624725088512719018644240551614743857312017926280352856935121401,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=96092665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.96092665' seed=88941464859304624725088512719018644240551614743857312017926280352856935121401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88941464859304624725088512719018644240551614743857312017926280352856935121401 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"35.edn_alert.7039848542787445782279185795652188879371834370660406421995249620804457758741","seed":7039848542787445782279185795652188879371834370660406421995249620804457758741,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1057783829 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1057783829' seed=7039848542787445782279185795652188879371834370660406421995249620804457758741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7039848542787445782279185795652188879371834370660406421995249620804457758741 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"35.edn_err.82058617241330995556838897694869086486846743275620159823477313546816899210041","seed":82058617241330995556838897694869086486846743275620159823477313546816899210041,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1785682745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1785682745' seed=82058617241330995556838897694869086486846743275620159823477313546816899210041 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82058617241330995556838897694869086486846743275620159823477313546816899210041 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"35.edn_disable.58014226965296057172990660933764045673199789260501001114592396879158726169416","seed":58014226965296057172990660933764045673199789260501001114592396879158726169416,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3726709576 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3726709576' seed=58014226965296057172990660933764045673199789260501001114592396879158726169416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58014226965296057172990660933764045673199789260501001114592396879158726169416 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"35.edn_disable_auto_req_mode.112096861518787627158245683688259643174349229245454024879578168703809835023111","seed":112096861518787627158245683688259643174349229245454024879578168703809835023111,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3231759111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.3231759111' seed=112096861518787627158245683688259643174349229245454024879578168703809835023111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112096861518787627158245683688259643174349229245454024879578168703809835023111 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/35.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"36.edn_genbits.86832056240624003187089283195478427776196919974739168958430151382988447741737","seed":86832056240624003187089283195478427776196919974739168958430151382988447741737,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3358521129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3358521129' seed=86832056240624003187089283195478427776196919974739168958430151382988447741737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86832056240624003187089283195478427776196919974739168958430151382988447741737 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"36.edn_alert.28751254112889998257455864870302869046427927150061175293922283896848202183676","seed":28751254112889998257455864870302869046427927150061175293922283896848202183676,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1748612092 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1748612092' seed=28751254112889998257455864870302869046427927150061175293922283896848202183676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28751254112889998257455864870302869046427927150061175293922283896848202183676 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"36.edn_err.88372977757090528371561685887676611094561165284719064304943749699034933947295","seed":88372977757090528371561685887676611094561165284719064304943749699034933947295,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2836196255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2836196255' seed=88372977757090528371561685887676611094561165284719064304943749699034933947295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88372977757090528371561685887676611094561165284719064304943749699034933947295 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"36.edn_disable.34718807628121578443402179394149158939464309344124014500383685953157048735887","seed":34718807628121578443402179394149158939464309344124014500383685953157048735887,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2140051599 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2140051599' seed=34718807628121578443402179394149158939464309344124014500383685953157048735887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34718807628121578443402179394149158939464309344124014500383685953157048735887 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"36.edn_disable_auto_req_mode.27664938110884572463990883248105012089145478784476026260475313145613065434978","seed":27664938110884572463990883248105012089145478784476026260475313145613065434978,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281589602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.281589602' seed=27664938110884572463990883248105012089145478784476026260475313145613065434978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27664938110884572463990883248105012089145478784476026260475313145613065434978 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/36.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"37.edn_genbits.105652772446567312270047475744124158149587778247001602672266785098993567574756","seed":105652772446567312270047475744124158149587778247001602672266785098993567574756,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2500111076 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2500111076' seed=105652772446567312270047475744124158149587778247001602672266785098993567574756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105652772446567312270047475744124158149587778247001602672266785098993567574756 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"37.edn_alert.56556146549404500138559901272760992433584187395817655322505505187712672154706","seed":56556146549404500138559901272760992433584187395817655322505505187712672154706,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2671461458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2671461458' seed=56556146549404500138559901272760992433584187395817655322505505187712672154706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56556146549404500138559901272760992433584187395817655322505505187712672154706 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"37.edn_err.104915687822583922646393052570582780268199028622369557664433115894044736230441","seed":104915687822583922646393052570582780268199028622369557664433115894044736230441,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3426358313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3426358313' seed=104915687822583922646393052570582780268199028622369557664433115894044736230441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104915687822583922646393052570582780268199028622369557664433115894044736230441 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"37.edn_disable.50844250478282947114446166498086158719213198583191313579062342770051934193054","seed":50844250478282947114446166498086158719213198583191313579062342770051934193054,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2420508062 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2420508062' seed=50844250478282947114446166498086158719213198583191313579062342770051934193054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50844250478282947114446166498086158719213198583191313579062342770051934193054 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"37.edn_disable_auto_req_mode.106580796482200021186505212618903882688316933893497383235117877070915739126900","seed":106580796482200021186505212618903882688316933893497383235117877070915739126900,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1007225972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.1007225972' seed=106580796482200021186505212618903882688316933893497383235117877070915739126900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106580796482200021186505212618903882688316933893497383235117877070915739126900 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"38.edn_genbits.69798006536160124776020482825010957928133693313460414375941174045494623047942","seed":69798006536160124776020482825010957928133693313460414375941174045494623047942,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1857523974 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1857523974' seed=69798006536160124776020482825010957928133693313460414375941174045494623047942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69798006536160124776020482825010957928133693313460414375941174045494623047942 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"38.edn_alert.74017190336921823005924012360063418952594446403875193584011342483225376006346","seed":74017190336921823005924012360063418952594446403875193584011342483225376006346,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4116521162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4116521162' seed=74017190336921823005924012360063418952594446403875193584011342483225376006346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74017190336921823005924012360063418952594446403875193584011342483225376006346 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"38.edn_err.92118412144618264515596886100134029064321031767012641643786091094080952676320","seed":92118412144618264515596886100134029064321031767012641643786091094080952676320,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1580937184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1580937184' seed=92118412144618264515596886100134029064321031767012641643786091094080952676320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92118412144618264515596886100134029064321031767012641643786091094080952676320 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"38.edn_disable.32805287135423003982198929576590768594804650834036972084399235186969852103361","seed":32805287135423003982198929576590768594804650834036972084399235186969852103361,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4013017793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4013017793' seed=32805287135423003982198929576590768594804650834036972084399235186969852103361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32805287135423003982198929576590768594804650834036972084399235186969852103361 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"38.edn_disable_auto_req_mode.81524373355540767293403304283357085447296857733701105810716405300129708275293","seed":81524373355540767293403304283357085447296857733701105810716405300129708275293,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=899577437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.899577437' seed=81524373355540767293403304283357085447296857733701105810716405300129708275293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81524373355540767293403304283357085447296857733701105810716405300129708275293 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"39.edn_genbits.7362150476854832373435073574780057465886702936629352918268787659504868744982","seed":7362150476854832373435073574780057465886702936629352918268787659504868744982,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1981374230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1981374230' seed=7362150476854832373435073574780057465886702936629352918268787659504868744982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7362150476854832373435073574780057465886702936629352918268787659504868744982 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"39.edn_alert.59381220055086354590382341544955013910107861571568632532612433180677877989006","seed":59381220055086354590382341544955013910107861571568632532612433180677877989006,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557490318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3557490318' seed=59381220055086354590382341544955013910107861571568632532612433180677877989006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59381220055086354590382341544955013910107861571568632532612433180677877989006 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"39.edn_err.44918283208789370424802144109607142142813721844562467334189322813073705008863","seed":44918283208789370424802144109607142142813721844562467334189322813073705008863,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3349020383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3349020383' seed=44918283208789370424802144109607142142813721844562467334189322813073705008863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44918283208789370424802144109607142142813721844562467334189322813073705008863 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"39.edn_disable.82291932053817827483668540975576565876692602363023370665146289289950609430279","seed":82291932053817827483668540975576565876692602363023370665146289289950609430279,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1976719111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1976719111' seed=82291932053817827483668540975576565876692602363023370665146289289950609430279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82291932053817827483668540975576565876692602363023370665146289289950609430279 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"39.edn_disable_auto_req_mode.1461382739976169970536428872299703187911871800884268507175559375654748539170","seed":1461382739976169970536428872299703187911871800884268507175559375654748539170,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179661602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.3179661602' seed=1461382739976169970536428872299703187911871800884268507175559375654748539170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1461382739976169970536428872299703187911871800884268507175559375654748539170 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/39.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"40.edn_genbits.70512608000841802848556143512568130971918458687258623201507075537232864457801","seed":70512608000841802848556143512568130971918458687258623201507075537232864457801,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=970961993 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.970961993' seed=70512608000841802848556143512568130971918458687258623201507075537232864457801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70512608000841802848556143512568130971918458687258623201507075537232864457801 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"40.edn_alert.62751348313954818313445119688459618556526586826329472067076949692809437330648","seed":62751348313954818313445119688459618556526586826329472067076949692809437330648,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379300056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2379300056' seed=62751348313954818313445119688459618556526586826329472067076949692809437330648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62751348313954818313445119688459618556526586826329472067076949692809437330648 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"40.edn_err.28374591361711778745319354563243925400755743470883909103058299216055316812232","seed":28374591361711778745319354563243925400755743470883909103058299216055316812232,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2756219336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2756219336' seed=28374591361711778745319354563243925400755743470883909103058299216055316812232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28374591361711778745319354563243925400755743470883909103058299216055316812232 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"40.edn_disable.114530496326118767121766180945941282550758024595190290168692511085025234321456","seed":114530496326118767121766180945941282550758024595190290168692511085025234321456,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1215103024 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1215103024' seed=114530496326118767121766180945941282550758024595190290168692511085025234321456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114530496326118767121766180945941282550758024595190290168692511085025234321456 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"40.edn_disable_auto_req_mode.8649137725528477918179343555388681117786358085198450254250786928944031938601","seed":8649137725528477918179343555388681117786358085198450254250786928944031938601,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2565290025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.2565290025' seed=8649137725528477918179343555388681117786358085198450254250786928944031938601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8649137725528477918179343555388681117786358085198450254250786928944031938601 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"41.edn_genbits.73238322802822926650348340675436507341095040093391696337068149353649813989825","seed":73238322802822926650348340675436507341095040093391696337068149353649813989825,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111632321 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1111632321' seed=73238322802822926650348340675436507341095040093391696337068149353649813989825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73238322802822926650348340675436507341095040093391696337068149353649813989825 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"41.edn_alert.10610092794951520110019859959695523669873011012162682364814961090208620461190","seed":10610092794951520110019859959695523669873011012162682364814961090208620461190,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1734720646 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1734720646' seed=10610092794951520110019859959695523669873011012162682364814961090208620461190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10610092794951520110019859959695523669873011012162682364814961090208620461190 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"41.edn_err.56193031175969495875416481988687285525440047920034687841401690537555988406391","seed":56193031175969495875416481988687285525440047920034687841401690537555988406391,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=252010615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.252010615' seed=56193031175969495875416481988687285525440047920034687841401690537555988406391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56193031175969495875416481988687285525440047920034687841401690537555988406391 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"41.edn_disable.54328223179541654822474654009857560434513181609254243982215133838672031519171","seed":54328223179541654822474654009857560434513181609254243982215133838672031519171,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4183953859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4183953859' seed=54328223179541654822474654009857560434513181609254243982215133838672031519171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54328223179541654822474654009857560434513181609254243982215133838672031519171 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"41.edn_disable_auto_req_mode.109816681154435658444535543471149839100546976338869223459347420747508436059980","seed":109816681154435658444535543471149839100546976338869223459347420747508436059980,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2296530764 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.2296530764' seed=109816681154435658444535543471149839100546976338869223459347420747508436059980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109816681154435658444535543471149839100546976338869223459347420747508436059980 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"42.edn_genbits.69416915689643857367257472086432873682099771851027459973597492709918978580174","seed":69416915689643857367257472086432873682099771851027459973597492709918978580174,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4149976782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4149976782' seed=69416915689643857367257472086432873682099771851027459973597492709918978580174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69416915689643857367257472086432873682099771851027459973597492709918978580174 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"42.edn_alert.46580224116014737857107413276028985894055587343879257974352453191498419184179","seed":46580224116014737857107413276028985894055587343879257974352453191498419184179,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841340979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1841340979' seed=46580224116014737857107413276028985894055587343879257974352453191498419184179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46580224116014737857107413276028985894055587343879257974352453191498419184179 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"42.edn_err.68707551018750844785309678992322996826565963002612125170442589201412659871383","seed":68707551018750844785309678992322996826565963002612125170442589201412659871383,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3165126295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3165126295' seed=68707551018750844785309678992322996826565963002612125170442589201412659871383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68707551018750844785309678992322996826565963002612125170442589201412659871383 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"42.edn_disable.46803779910912175930872647121788652038211802023422579834935351222915423622414","seed":46803779910912175930872647121788652038211802023422579834935351222915423622414,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833522446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1833522446' seed=46803779910912175930872647121788652038211802023422579834935351222915423622414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46803779910912175930872647121788652038211802023422579834935351222915423622414 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"42.edn_disable_auto_req_mode.19389419514959424563938034331157979614099031065514706799377702592607853139126","seed":19389419514959424563938034331157979614099031065514706799377702592607853139126,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2257245366 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2257245366' seed=19389419514959424563938034331157979614099031065514706799377702592607853139126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19389419514959424563938034331157979614099031065514706799377702592607853139126 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"43.edn_genbits.51095275851429397709045443782834373496634892371067608923908764988182225524694","seed":51095275851429397709045443782834373496634892371067608923908764988182225524694,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=343709654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.343709654' seed=51095275851429397709045443782834373496634892371067608923908764988182225524694 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51095275851429397709045443782834373496634892371067608923908764988182225524694 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"43.edn_alert.25894884091505830320909036855733780360542284659276316104913798395785423392011","seed":25894884091505830320909036855733780360542284659276316104913798395785423392011,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2767752459 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2767752459' seed=25894884091505830320909036855733780360542284659276316104913798395785423392011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25894884091505830320909036855733780360542284659276316104913798395785423392011 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"43.edn_err.13146019205396903555219133049576075966657557289609775907315455493533636462894","seed":13146019205396903555219133049576075966657557289609775907315455493533636462894,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3855583534 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3855583534' seed=13146019205396903555219133049576075966657557289609775907315455493533636462894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13146019205396903555219133049576075966657557289609775907315455493533636462894 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"43.edn_disable.63332571907867462254089989928382581614273569109782810636510325282798382858799","seed":63332571907867462254089989928382581614273569109782810636510325282798382858799,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=970965551 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.970965551' seed=63332571907867462254089989928382581614273569109782810636510325282798382858799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63332571907867462254089989928382581614273569109782810636510325282798382858799 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"43.edn_disable_auto_req_mode.101992681343459806742953936138716403172017586848826525314322041740539215364337","seed":101992681343459806742953936138716403172017586848826525314322041740539215364337,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4122099953 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.4122099953' seed=101992681343459806742953936138716403172017586848826525314322041740539215364337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101992681343459806742953936138716403172017586848826525314322041740539215364337 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"44.edn_genbits.21928713945612037103986381461453090054312436076442773852446792457890340862776","seed":21928713945612037103986381461453090054312436076442773852446792457890340862776,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4008770360 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4008770360' seed=21928713945612037103986381461453090054312436076442773852446792457890340862776 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21928713945612037103986381461453090054312436076442773852446792457890340862776 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"44.edn_alert.80109358429627467635753089243231667932261940967971102980323036644612245276496","seed":80109358429627467635753089243231667932261940967971102980323036644612245276496,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4118529872 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4118529872' seed=80109358429627467635753089243231667932261940967971102980323036644612245276496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80109358429627467635753089243231667932261940967971102980323036644612245276496 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"44.edn_err.71166948566614946690255112732321464888811212235461234301257528837515900371784","seed":71166948566614946690255112732321464888811212235461234301257528837515900371784,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064480584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3064480584' seed=71166948566614946690255112732321464888811212235461234301257528837515900371784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71166948566614946690255112732321464888811212235461234301257528837515900371784 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"44.edn_disable.54513043023861689091751078803754482267678969419799444209436287674704758704595","seed":54513043023861689091751078803754482267678969419799444209436287674704758704595,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2532444627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2532444627' seed=54513043023861689091751078803754482267678969419799444209436287674704758704595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54513043023861689091751078803754482267678969419799444209436287674704758704595 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"44.edn_disable_auto_req_mode.17403658564230575022254355003919090185100806124793886139847584363062687556123","seed":17403658564230575022254355003919090185100806124793886139847584363062687556123,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518016539 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.2518016539' seed=17403658564230575022254355003919090185100806124793886139847584363062687556123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17403658564230575022254355003919090185100806124793886139847584363062687556123 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"45.edn_genbits.50873816923303690614826987256834190179672996715009578931836634402610318695660","seed":50873816923303690614826987256834190179672996715009578931836634402610318695660,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3306183916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3306183916' seed=50873816923303690614826987256834190179672996715009578931836634402610318695660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50873816923303690614826987256834190179672996715009578931836634402610318695660 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"45.edn_alert.46393578268889147399413066049443370407266555425114777400078738548118929671456","seed":46393578268889147399413066049443370407266555425114777400078738548118929671456,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4191028512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4191028512' seed=46393578268889147399413066049443370407266555425114777400078738548118929671456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46393578268889147399413066049443370407266555425114777400078738548118929671456 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"45.edn_err.49638455695694011438058105432272458184716408787362956355380989009530541707333","seed":49638455695694011438058105432272458184716408787362956355380989009530541707333,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3485077573 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3485077573' seed=49638455695694011438058105432272458184716408787362956355380989009530541707333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49638455695694011438058105432272458184716408787362956355380989009530541707333 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"45.edn_disable.43551935892731462801489463264138896293532948493911252572142902133260111411878","seed":43551935892731462801489463264138896293532948493911252572142902133260111411878,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=939096742 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.939096742' seed=43551935892731462801489463264138896293532948493911252572142902133260111411878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43551935892731462801489463264138896293532948493911252572142902133260111411878 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"45.edn_disable_auto_req_mode.87603288845748915584004771707316184343748053927775938177373298073277798376650","seed":87603288845748915584004771707316184343748053927775938177373298073277798376650,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085867722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.4085867722' seed=87603288845748915584004771707316184343748053927775938177373298073277798376650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87603288845748915584004771707316184343748053927775938177373298073277798376650 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"46.edn_genbits.86921742715051580243822961535144155444027579071937054784350757824721895213535","seed":86921742715051580243822961535144155444027579071937054784350757824721895213535,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1229638111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1229638111' seed=86921742715051580243822961535144155444027579071937054784350757824721895213535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86921742715051580243822961535144155444027579071937054784350757824721895213535 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"46.edn_alert.76207743971483775229957518715681303071065118746950654070388411249995869236404","seed":76207743971483775229957518715681303071065118746950654070388411249995869236404,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2398792884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2398792884' seed=76207743971483775229957518715681303071065118746950654070388411249995869236404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76207743971483775229957518715681303071065118746950654070388411249995869236404 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"46.edn_err.46922311921270404431653221317636601338366621259173143573817861375429296244307","seed":46922311921270404431653221317636601338366621259173143573817861375429296244307,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595735123 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2595735123' seed=46922311921270404431653221317636601338366621259173143573817861375429296244307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46922311921270404431653221317636601338366621259173143573817861375429296244307 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"46.edn_disable.91520884010242290493103011851693058289661407399376294655543380128816810126585","seed":91520884010242290493103011851693058289661407399376294655543380128816810126585,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=626486521 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.626486521' seed=91520884010242290493103011851693058289661407399376294655543380128816810126585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91520884010242290493103011851693058289661407399376294655543380128816810126585 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"46.edn_disable_auto_req_mode.84122331937845652569295743985959172321256794466648203403059635585676018147959","seed":84122331937845652569295743985959172321256794466648203403059635585676018147959,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2152686199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.2152686199' seed=84122331937845652569295743985959172321256794466648203403059635585676018147959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84122331937845652569295743985959172321256794466648203403059635585676018147959 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"47.edn_genbits.15809887649402406279362966995373956776894926279732338544052245359571961300526","seed":15809887649402406279362966995373956776894926279732338544052245359571961300526,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3612263982 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3612263982' seed=15809887649402406279362966995373956776894926279732338544052245359571961300526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15809887649402406279362966995373956776894926279732338544052245359571961300526 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"47.edn_alert.41612421683704864712218710327733118351223839926632834325358719854005191891650","seed":41612421683704864712218710327733118351223839926632834325358719854005191891650,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3599948482 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3599948482' seed=41612421683704864712218710327733118351223839926632834325358719854005191891650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41612421683704864712218710327733118351223839926632834325358719854005191891650 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"47.edn_err.17470256884726555895264511066454308110228342896248148930830619862638149743770","seed":17470256884726555895264511066454308110228342896248148930830619862638149743770,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1340847258 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1340847258' seed=17470256884726555895264511066454308110228342896248148930830619862638149743770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17470256884726555895264511066454308110228342896248148930830619862638149743770 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"47.edn_disable.9816540781109677371956020365174930609028745049856196577540012374955014907713","seed":9816540781109677371956020365174930609028745049856196577540012374955014907713,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3746981697 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3746981697' seed=9816540781109677371956020365174930609028745049856196577540012374955014907713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9816540781109677371956020365174930609028745049856196577540012374955014907713 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"47.edn_disable_auto_req_mode.25464908677018706797123535401152331077818670906939443141656707035480064428717","seed":25464908677018706797123535401152331077818670906939443141656707035480064428717,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2318830253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.2318830253' seed=25464908677018706797123535401152331077818670906939443141656707035480064428717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25464908677018706797123535401152331077818670906939443141656707035480064428717 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"48.edn_genbits.82019169295261448387013510093847396466942337884408040666282234945520265304208","seed":82019169295261448387013510093847396466942337884408040666282234945520265304208,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=761501840 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.761501840' seed=82019169295261448387013510093847396466942337884408040666282234945520265304208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82019169295261448387013510093847396466942337884408040666282234945520265304208 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"48.edn_alert.81007282613779359173693407476898296442020023655553484394511213201181111139547","seed":81007282613779359173693407476898296442020023655553484394511213201181111139547,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1219411163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1219411163' seed=81007282613779359173693407476898296442020023655553484394511213201181111139547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81007282613779359173693407476898296442020023655553484394511213201181111139547 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"48.edn_err.15653341620908028431717829243606592033307861024917440239077860578675419034935","seed":15653341620908028431717829243606592033307861024917440239077860578675419034935,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3658790199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3658790199' seed=15653341620908028431717829243606592033307861024917440239077860578675419034935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15653341620908028431717829243606592033307861024917440239077860578675419034935 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"48.edn_disable.104086187789896143026008421034488895240648460983900131632297519047674215335759","seed":104086187789896143026008421034488895240648460983900131632297519047674215335759,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753365839 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2753365839' seed=104086187789896143026008421034488895240648460983900131632297519047674215335759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104086187789896143026008421034488895240648460983900131632297519047674215335759 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"48.edn_disable_auto_req_mode.64995488297915083973941374882026665293662092350316627511220889453848738131034","seed":64995488297915083973941374882026665293662092350316627511220889453848738131034,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289298522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.2289298522' seed=64995488297915083973941374882026665293662092350316627511220889453848738131034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64995488297915083973941374882026665293662092350316627511220889453848738131034 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"49.edn_genbits.63995154026054947286594904132603750387335618525044276230332419727555124820903","seed":63995154026054947286594904132603750387335618525044276230332419727555124820903,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2669181863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2669181863' seed=63995154026054947286594904132603750387335618525044276230332419727555124820903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63995154026054947286594904132603750387335618525044276230332419727555124820903 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"49.edn_alert.71483321179756639468781309963083809401538714547956425688438086583562833428751","seed":71483321179756639468781309963083809401538714547956425688438086583562833428751,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324707087 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3324707087' seed=71483321179756639468781309963083809401538714547956425688438086583562833428751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71483321179756639468781309963083809401538714547956425688438086583562833428751 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"49.edn_err.45292430666262270798866410435255393641038782972406272939570073783305757847687","seed":45292430666262270798866410435255393641038782972406272939570073783305757847687,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3683971207 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3683971207' seed=45292430666262270798866410435255393641038782972406272939570073783305757847687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45292430666262270798866410435255393641038782972406272939570073783305757847687 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable","qual_name":"49.edn_disable.104854695165408129650256633074212599414902751550365047899595744176731057755416","seed":104854695165408129650256633074212599414902751550365047899595744176731057755416,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_disable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4179301656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4179301656' seed=104854695165408129650256633074212599414902751550365047899595744176731057755416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104854695165408129650256633074212599414902751550365047899595744176731057755416 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"49.edn_disable_auto_req_mode.40076621764177902782174986696808165997946351769482664191016706123263305530976","seed":40076621764177902782174986696808165997946351769482664191016706123263305530976,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_disable_auto_req_mode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=479673952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.479673952' seed=40076621764177902782174986696808165997946351769482664191016706123263305530976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40076621764177902782174986696808165997946351769482664191016706123263305530976 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/49.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"50.edn_genbits.6917006153989503641750693246714153791484445695334003372503662405898606969054","seed":6917006153989503641750693246714153791484445695334003372503662405898606969054,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955823838 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1955823838' seed=6917006153989503641750693246714153791484445695334003372503662405898606969054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6917006153989503641750693246714153791484445695334003372503662405898606969054 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"50.edn_alert.26307591975253164827561251422305974112135102490550764261688467362580298467510","seed":26307591975253164827561251422305974112135102490550764261688467362580298467510,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2782922934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2782922934' seed=26307591975253164827561251422305974112135102490550764261688467362580298467510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26307591975253164827561251422305974112135102490550764261688467362580298467510 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"50.edn_err.25584350842745828836189548889681616616971388396157947598881280187434474200150","seed":25584350842745828836189548889681616616971388396157947598881280187434474200150,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2856377430 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2856377430' seed=25584350842745828836189548889681616616971388396157947598881280187434474200150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25584350842745828836189548889681616616971388396157947598881280187434474200150 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/50.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"51.edn_genbits.76295734980173872070322613898225559003281822273543594687989916843292922397165","seed":76295734980173872070322613898225559003281822273543594687989916843292922397165,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=202031597 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.202031597' seed=76295734980173872070322613898225559003281822273543594687989916843292922397165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76295734980173872070322613898225559003281822273543594687989916843292922397165 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"51.edn_alert.87625014261740175911595351654039303142395496284499315604259225389842573149551","seed":87625014261740175911595351654039303142395496284499315604259225389842573149551,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=221889903 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.221889903' seed=87625014261740175911595351654039303142395496284499315604259225389842573149551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87625014261740175911595351654039303142395496284499315604259225389842573149551 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"51.edn_err.90306426137376475734135482999081009517176646929416061535898771580584778051645","seed":90306426137376475734135482999081009517176646929416061535898771580584778051645,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=963686461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.963686461' seed=90306426137376475734135482999081009517176646929416061535898771580584778051645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90306426137376475734135482999081009517176646929416061535898771580584778051645 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/51.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"52.edn_genbits.28107567880919427615438813778250544388104719313982130554010905669880736770383","seed":28107567880919427615438813778250544388104719313982130554010905669880736770383,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268981583 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2268981583' seed=28107567880919427615438813778250544388104719313982130554010905669880736770383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28107567880919427615438813778250544388104719313982130554010905669880736770383 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"52.edn_alert.39457689455681406873831255347725843293450249502448967714959556057199824390795","seed":39457689455681406873831255347725843293450249502448967714959556057199824390795,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597033099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1597033099' seed=39457689455681406873831255347725843293450249502448967714959556057199824390795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39457689455681406873831255347725843293450249502448967714959556057199824390795 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"52.edn_err.91363577405439109195170027775076984307349434375342269023866086307826845590672","seed":91363577405439109195170027775076984307349434375342269023866086307826845590672,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4263486608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4263486608' seed=91363577405439109195170027775076984307349434375342269023866086307826845590672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91363577405439109195170027775076984307349434375342269023866086307826845590672 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/52.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"53.edn_genbits.33230623623744263682780954070742915637387387647007443288205323145276916507298","seed":33230623623744263682780954070742915637387387647007443288205323145276916507298,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59253410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.59253410' seed=33230623623744263682780954070742915637387387647007443288205323145276916507298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33230623623744263682780954070742915637387387647007443288205323145276916507298 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"53.edn_alert.85922839101620464731261273271743556155684782283790594271593275679933319769912","seed":85922839101620464731261273271743556155684782283790594271593275679933319769912,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4248727352 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.4248727352' seed=85922839101620464731261273271743556155684782283790594271593275679933319769912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85922839101620464731261273271743556155684782283790594271593275679933319769912 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"53.edn_err.21923783561365972764830072191860051533067217402973056635217776143859091939702","seed":21923783561365972764830072191860051533067217402973056635217776143859091939702,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3798638966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3798638966' seed=21923783561365972764830072191860051533067217402973056635217776143859091939702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21923783561365972764830072191860051533067217402973056635217776143859091939702 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/53.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"54.edn_genbits.47460664875280627383133045744628148780319154167038538416012471129404796724703","seed":47460664875280627383133045744628148780319154167038538416012471129404796724703,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3067504095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3067504095' seed=47460664875280627383133045744628148780319154167038538416012471129404796724703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47460664875280627383133045744628148780319154167038538416012471129404796724703 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"54.edn_alert.43733252362524958315499293559276028114280227556344090633504056030703277262306","seed":43733252362524958315499293559276028114280227556344090633504056030703277262306,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=366691810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.366691810' seed=43733252362524958315499293559276028114280227556344090633504056030703277262306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43733252362524958315499293559276028114280227556344090633504056030703277262306 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"54.edn_err.67284264839142016277005585476666151877372333329080595017097631569803547750000","seed":67284264839142016277005585476666151877372333329080595017097631569803547750000,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=131575408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.131575408' seed=67284264839142016277005585476666151877372333329080595017097631569803547750000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67284264839142016277005585476666151877372333329080595017097631569803547750000 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/54.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"55.edn_genbits.45283914732418416160094312219852777334487871015602137521161507840543808086559","seed":45283914732418416160094312219852777334487871015602137521161507840543808086559,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2193416735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2193416735' seed=45283914732418416160094312219852777334487871015602137521161507840543808086559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45283914732418416160094312219852777334487871015602137521161507840543808086559 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"55.edn_alert.36400572196205492593012970526691017152972357612702434873141187967768955954930","seed":36400572196205492593012970526691017152972357612702434873141187967768955954930,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=629909234 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.629909234' seed=36400572196205492593012970526691017152972357612702434873141187967768955954930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36400572196205492593012970526691017152972357612702434873141187967768955954930 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"55.edn_err.88827400979444787945561953994302842460404659155624629792140485763559159775474","seed":88827400979444787945561953994302842460404659155624629792140485763559159775474,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1128022258 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1128022258' seed=88827400979444787945561953994302842460404659155624629792140485763559159775474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88827400979444787945561953994302842460404659155624629792140485763559159775474 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/55.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"56.edn_genbits.61164722897035139120214816981693460225660562380686678517345122863818535753118","seed":61164722897035139120214816981693460225660562380686678517345122863818535753118,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947279262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.947279262' seed=61164722897035139120214816981693460225660562380686678517345122863818535753118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61164722897035139120214816981693460225660562380686678517345122863818535753118 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"56.edn_alert.70088653327336164285142662573491783627704623422214105100402816493207498708569","seed":70088653327336164285142662573491783627704623422214105100402816493207498708569,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1426249305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1426249305' seed=70088653327336164285142662573491783627704623422214105100402816493207498708569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70088653327336164285142662573491783627704623422214105100402816493207498708569 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"56.edn_err.53684707550004087385453645694227336421312300714696181605063563259413609483132","seed":53684707550004087385453645694227336421312300714696181605063563259413609483132,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=928156540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.928156540' seed=53684707550004087385453645694227336421312300714696181605063563259413609483132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53684707550004087385453645694227336421312300714696181605063563259413609483132 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/56.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"57.edn_genbits.100000615953175435644779340768306498987119742068350747923328714388852813783531","seed":100000615953175435644779340768306498987119742068350747923328714388852813783531,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2306269675 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2306269675' seed=100000615953175435644779340768306498987119742068350747923328714388852813783531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100000615953175435644779340768306498987119742068350747923328714388852813783531 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"57.edn_alert.17649315278801182543567101632166728141645049334098219193358853011104900507886","seed":17649315278801182543567101632166728141645049334098219193358853011104900507886,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2424760558 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2424760558' seed=17649315278801182543567101632166728141645049334098219193358853011104900507886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17649315278801182543567101632166728141645049334098219193358853011104900507886 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"57.edn_err.47814877909127105088493732127941086997414189282853632860105818352587815454152","seed":47814877909127105088493732127941086997414189282853632860105818352587815454152,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262945736 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1262945736' seed=47814877909127105088493732127941086997414189282853632860105818352587815454152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47814877909127105088493732127941086997414189282853632860105818352587815454152 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/57.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"58.edn_genbits.70751071214592051313113339080312362649611465411544679809302539245962911954314","seed":70751071214592051313113339080312362649611465411544679809302539245962911954314,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1753625994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1753625994' seed=70751071214592051313113339080312362649611465411544679809302539245962911954314 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70751071214592051313113339080312362649611465411544679809302539245962911954314 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"58.edn_alert.99599942438308824856763669919711646007095466544725169174637571859570559975766","seed":99599942438308824856763669919711646007095466544725169174637571859570559975766,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171344214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.171344214' seed=99599942438308824856763669919711646007095466544725169174637571859570559975766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99599942438308824856763669919711646007095466544725169174637571859570559975766 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"58.edn_err.5635523950745804955566414097126588220783052535069876015510474830059358139719","seed":5635523950745804955566414097126588220783052535069876015510474830059358139719,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290469191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.290469191' seed=5635523950745804955566414097126588220783052535069876015510474830059358139719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5635523950745804955566414097126588220783052535069876015510474830059358139719 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/58.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"59.edn_genbits.90846549687786162339086157636466762121676513788125932527773064671363535498274","seed":90846549687786162339086157636466762121676513788125932527773064671363535498274,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1526754338 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1526754338' seed=90846549687786162339086157636466762121676513788125932527773064671363535498274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90846549687786162339086157636466762121676513788125932527773064671363535498274 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"59.edn_alert.54296117462020731468771564635853558584369720203228846613124256319100328720380","seed":54296117462020731468771564635853558584369720203228846613124256319100328720380,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3016603644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3016603644' seed=54296117462020731468771564635853558584369720203228846613124256319100328720380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54296117462020731468771564635853558584369720203228846613124256319100328720380 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"59.edn_err.79620756809821455621440741940913005420518795441338696046407558622454529915205","seed":79620756809821455621440741940913005420518795441338696046407558622454529915205,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244054341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.244054341' seed=79620756809821455621440741940913005420518795441338696046407558622454529915205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79620756809821455621440741940913005420518795441338696046407558622454529915205 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/59.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"60.edn_genbits.92362119510372258513203497230124665143036963950255513337024335639628496308169","seed":92362119510372258513203497230124665143036963950255513337024335639628496308169,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088123849 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3088123849' seed=92362119510372258513203497230124665143036963950255513337024335639628496308169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92362119510372258513203497230124665143036963950255513337024335639628496308169 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"60.edn_alert.20404147511570330404426782855043952075843349474817372068057477816422469008570","seed":20404147511570330404426782855043952075843349474817372068057477816422469008570,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1960901818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1960901818' seed=20404147511570330404426782855043952075843349474817372068057477816422469008570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20404147511570330404426782855043952075843349474817372068057477816422469008570 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"60.edn_err.92184503439059403448829889793657052737497712861443325146407711882579117663460","seed":92184503439059403448829889793657052737497712861443325146407711882579117663460,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1314186468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1314186468' seed=92184503439059403448829889793657052737497712861443325146407711882579117663460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92184503439059403448829889793657052737497712861443325146407711882579117663460 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/60.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"61.edn_genbits.62385600606886620140669175323492321420431908571260682639082324119490459208509","seed":62385600606886620140669175323492321420431908571260682639082324119490459208509,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=788663101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.788663101' seed=62385600606886620140669175323492321420431908571260682639082324119490459208509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62385600606886620140669175323492321420431908571260682639082324119490459208509 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"61.edn_alert.48729924236503947770003847916183440313284582298520912579635013823896105069135","seed":48729924236503947770003847916183440313284582298520912579635013823896105069135,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846698063 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2846698063' seed=48729924236503947770003847916183440313284582298520912579635013823896105069135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48729924236503947770003847916183440313284582298520912579635013823896105069135 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"61.edn_err.38073747131191720536069899648003419443961819070455327210283865899829737243398","seed":38073747131191720536069899648003419443961819070455327210283865899829737243398,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3696968454 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3696968454' seed=38073747131191720536069899648003419443961819070455327210283865899829737243398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38073747131191720536069899648003419443961819070455327210283865899829737243398 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/61.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"62.edn_genbits.112683155522117577648062379332352112921096176330761718162096190184401000944783","seed":112683155522117577648062379332352112921096176330761718162096190184401000944783,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3694875791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3694875791' seed=112683155522117577648062379332352112921096176330761718162096190184401000944783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112683155522117577648062379332352112921096176330761718162096190184401000944783 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"62.edn_alert.16565556864019630581238592689539226995438708983919753043456051644089705770883","seed":16565556864019630581238592689539226995438708983919753043456051644089705770883,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1571368835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1571368835' seed=16565556864019630581238592689539226995438708983919753043456051644089705770883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16565556864019630581238592689539226995438708983919753043456051644089705770883 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"62.edn_err.70547744736340213900927582530366747160274399576935002239331629928230697465986","seed":70547744736340213900927582530366747160274399576935002239331629928230697465986,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1214412930 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1214412930' seed=70547744736340213900927582530366747160274399576935002239331629928230697465986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70547744736340213900927582530366747160274399576935002239331629928230697465986 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/62.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"63.edn_genbits.54693233870767316210861229375390335407913199509881693955678930243491524225622","seed":54693233870767316210861229375390335407913199509881693955678930243491524225622,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=832809558 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.832809558' seed=54693233870767316210861229375390335407913199509881693955678930243491524225622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54693233870767316210861229375390335407913199509881693955678930243491524225622 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"63.edn_alert.5306261640269026399799915311751557619977104394053103416390694577428492121279","seed":5306261640269026399799915311751557619977104394053103416390694577428492121279,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3550409919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3550409919' seed=5306261640269026399799915311751557619977104394053103416390694577428492121279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5306261640269026399799915311751557619977104394053103416390694577428492121279 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"63.edn_err.49947262309700770484563545926034288719404854509023638228680198184626354086344","seed":49947262309700770484563545926034288719404854509023638228680198184626354086344,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1541890504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1541890504' seed=49947262309700770484563545926034288719404854509023638228680198184626354086344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49947262309700770484563545926034288719404854509023638228680198184626354086344 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/63.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"64.edn_genbits.94374342510998800902237097556411869235603880154906656741439879392311827546300","seed":94374342510998800902237097556411869235603880154906656741439879392311827546300,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2387394748 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2387394748' seed=94374342510998800902237097556411869235603880154906656741439879392311827546300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94374342510998800902237097556411869235603880154906656741439879392311827546300 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"64.edn_alert.90208727888846855697672271168781614571028135628761223228776261024671275873087","seed":90208727888846855697672271168781614571028135628761223228776261024671275873087,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3450008383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3450008383' seed=90208727888846855697672271168781614571028135628761223228776261024671275873087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90208727888846855697672271168781614571028135628761223228776261024671275873087 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"64.edn_err.14861992310936109046349765609639871221414994167559212497861630768411776757660","seed":14861992310936109046349765609639871221414994167559212497861630768411776757660,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=728870812 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.728870812' seed=14861992310936109046349765609639871221414994167559212497861630768411776757660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14861992310936109046349765609639871221414994167559212497861630768411776757660 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/64.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"65.edn_genbits.85023031651823795008633163407108036686581489031364753967023959934356449622482","seed":85023031651823795008633163407108036686581489031364753967023959934356449622482,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1027307986 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1027307986' seed=85023031651823795008633163407108036686581489031364753967023959934356449622482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85023031651823795008633163407108036686581489031364753967023959934356449622482 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"65.edn_alert.102612926095163334896411371554094462227236422086920668328213357131701971330574","seed":102612926095163334896411371554094462227236422086920668328213357131701971330574,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913033230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3913033230' seed=102612926095163334896411371554094462227236422086920668328213357131701971330574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102612926095163334896411371554094462227236422086920668328213357131701971330574 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"65.edn_err.42452147511951046282847910502537604269410579660684533105163484559146809573058","seed":42452147511951046282847910502537604269410579660684533105163484559146809573058,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59522754 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.59522754' seed=42452147511951046282847910502537604269410579660684533105163484559146809573058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42452147511951046282847910502537604269410579660684533105163484559146809573058 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/65.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"66.edn_genbits.68370922751130893938523419771689654728333258967220179807043792306294583626808","seed":68370922751130893938523419771689654728333258967220179807043792306294583626808,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=623021112 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.623021112' seed=68370922751130893938523419771689654728333258967220179807043792306294583626808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68370922751130893938523419771689654728333258967220179807043792306294583626808 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"66.edn_alert.14632885973508922741969834045635181833709773109229016836385709488466684959453","seed":14632885973508922741969834045635181833709773109229016836385709488466684959453,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4108475101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4108475101' seed=14632885973508922741969834045635181833709773109229016836385709488466684959453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14632885973508922741969834045635181833709773109229016836385709488466684959453 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"66.edn_err.39213879721809037285346787325520366514465670966317826122553564120090859885379","seed":39213879721809037285346787325520366514465670966317826122553564120090859885379,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416347459 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3416347459' seed=39213879721809037285346787325520366514465670966317826122553564120090859885379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39213879721809037285346787325520366514465670966317826122553564120090859885379 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/66.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"67.edn_genbits.5204060049666485700382980351528927288574244962337115740372724372292048470951","seed":5204060049666485700382980351528927288574244962337115740372724372292048470951,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286530471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4286530471' seed=5204060049666485700382980351528927288574244962337115740372724372292048470951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5204060049666485700382980351528927288574244962337115740372724372292048470951 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"67.edn_alert.25352012925494986599046717880012091374140971251686220381119211368773697163547","seed":25352012925494986599046717880012091374140971251686220381119211368773697163547,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2423279899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2423279899' seed=25352012925494986599046717880012091374140971251686220381119211368773697163547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25352012925494986599046717880012091374140971251686220381119211368773697163547 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"67.edn_err.59442215950296464801294528988279320495591136595171450909229035523774827254261","seed":59442215950296464801294528988279320495591136595171450909229035523774827254261,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1346163189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1346163189' seed=59442215950296464801294528988279320495591136595171450909229035523774827254261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59442215950296464801294528988279320495591136595171450909229035523774827254261 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/67.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"68.edn_genbits.8091180319521351046078498189213711468941047466775084950076612698648123614216","seed":8091180319521351046078498189213711468941047466775084950076612698648123614216,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=523576328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.523576328' seed=8091180319521351046078498189213711468941047466775084950076612698648123614216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8091180319521351046078498189213711468941047466775084950076612698648123614216 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"68.edn_alert.34344115825205757422564547690387243753494729991260963411577808526417729665903","seed":34344115825205757422564547690387243753494729991260963411577808526417729665903,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4136614767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.4136614767' seed=34344115825205757422564547690387243753494729991260963411577808526417729665903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34344115825205757422564547690387243753494729991260963411577808526417729665903 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"68.edn_err.81453264063784192428972202309137841377395499434472665983736893447742372080945","seed":81453264063784192428972202309137841377395499434472665983736893447742372080945,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119593265 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2119593265' seed=81453264063784192428972202309137841377395499434472665983736893447742372080945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81453264063784192428972202309137841377395499434472665983736893447742372080945 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/68.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"69.edn_genbits.42669189608085139743098929159242859190157557388560251769775797592594630076267","seed":42669189608085139743098929159242859190157557388560251769775797592594630076267,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=130312043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.130312043' seed=42669189608085139743098929159242859190157557388560251769775797592594630076267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42669189608085139743098929159242859190157557388560251769775797592594630076267 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"69.edn_alert.78436028754801525729138455688737322333605655729077680968551670521765530431398","seed":78436028754801525729138455688737322333605655729077680968551670521765530431398,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=98037670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.98037670' seed=78436028754801525729138455688737322333605655729077680968551670521765530431398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78436028754801525729138455688737322333605655729077680968551670521765530431398 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"69.edn_err.46277079089784842862729415527214017839514776844946594233257949757847190823196","seed":46277079089784842862729415527214017839514776844946594233257949757847190823196,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836507420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1836507420' seed=46277079089784842862729415527214017839514776844946594233257949757847190823196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46277079089784842862729415527214017839514776844946594233257949757847190823196 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/69.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"70.edn_genbits.54341805509344364415951645256719657139060038452524625952101793439681662029109","seed":54341805509344364415951645256719657139060038452524625952101793439681662029109,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795375925 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2795375925' seed=54341805509344364415951645256719657139060038452524625952101793439681662029109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54341805509344364415951645256719657139060038452524625952101793439681662029109 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"70.edn_alert.29153163893953036995777825711768889683337602797071581348469871582418068319268","seed":29153163893953036995777825711768889683337602797071581348469871582418068319268,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2921606180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2921606180' seed=29153163893953036995777825711768889683337602797071581348469871582418068319268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29153163893953036995777825711768889683337602797071581348469871582418068319268 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"70.edn_err.105684877210242809346867192844932620149548588509150916362135993348439931906461","seed":105684877210242809346867192844932620149548588509150916362135993348439931906461,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4233128349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.4233128349' seed=105684877210242809346867192844932620149548588509150916362135993348439931906461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105684877210242809346867192844932620149548588509150916362135993348439931906461 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/70.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"71.edn_genbits.86538923936870726762720024893619942787768564707499961740662401186503802716274","seed":86538923936870726762720024893619942787768564707499961740662401186503802716274,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2750382194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2750382194' seed=86538923936870726762720024893619942787768564707499961740662401186503802716274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86538923936870726762720024893619942787768564707499961740662401186503802716274 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"71.edn_alert.91780590453787365754623572280373794022404744697430910946538593209826049684319","seed":91780590453787365754623572280373794022404744697430910946538593209826049684319,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348367199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1348367199' seed=91780590453787365754623572280373794022404744697430910946538593209826049684319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91780590453787365754623572280373794022404744697430910946538593209826049684319 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"71.edn_err.67194797771973552395798901467556581282526007202552526858458691858612278615189","seed":67194797771973552395798901467556581282526007202552526858458691858612278615189,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=785472661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.785472661' seed=67194797771973552395798901467556581282526007202552526858458691858612278615189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67194797771973552395798901467556581282526007202552526858458691858612278615189 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/71.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"72.edn_genbits.57579433750269572503645341938773171982699767221529185052882323333724707408049","seed":57579433750269572503645341938773171982699767221529185052882323333724707408049,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=756992177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.756992177' seed=57579433750269572503645341938773171982699767221529185052882323333724707408049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57579433750269572503645341938773171982699767221529185052882323333724707408049 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"72.edn_alert.4298386392893104038839553585156211080754268886549355304270233617387755180240","seed":4298386392893104038839553585156211080754268886549355304270233617387755180240,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4143485136 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.4143485136' seed=4298386392893104038839553585156211080754268886549355304270233617387755180240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4298386392893104038839553585156211080754268886549355304270233617387755180240 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"72.edn_err.39167828283892491518972697841186072161119050180831399855060643213417765884422","seed":39167828283892491518972697841186072161119050180831399855060643213417765884422,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3682816518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3682816518' seed=39167828283892491518972697841186072161119050180831399855060643213417765884422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39167828283892491518972697841186072161119050180831399855060643213417765884422 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/72.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"73.edn_genbits.43515022615339961030271267678589891844181957109376703692167419121779684403641","seed":43515022615339961030271267678589891844181957109376703692167419121779684403641,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3581143481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3581143481' seed=43515022615339961030271267678589891844181957109376703692167419121779684403641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43515022615339961030271267678589891844181957109376703692167419121779684403641 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"73.edn_alert.104759371405330195864715403705628945023300777470632889059892924115328055066234","seed":104759371405330195864715403705628945023300777470632889059892924115328055066234,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2357673594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2357673594' seed=104759371405330195864715403705628945023300777470632889059892924115328055066234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104759371405330195864715403705628945023300777470632889059892924115328055066234 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"73.edn_err.88370562939746883202362633406720769755982682912948665243690707257439059494601","seed":88370562939746883202362633406720769755982682912948665243690707257439059494601,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2588722889 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2588722889' seed=88370562939746883202362633406720769755982682912948665243690707257439059494601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88370562939746883202362633406720769755982682912948665243690707257439059494601 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/73.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"74.edn_genbits.59582025086937118975570685776378830315510435568149456998833977936959839403278","seed":59582025086937118975570685776378830315510435568149456998833977936959839403278,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806878478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.806878478' seed=59582025086937118975570685776378830315510435568149456998833977936959839403278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59582025086937118975570685776378830315510435568149456998833977936959839403278 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"74.edn_alert.104389283176104181479437310000389222849454665499755610789308821908951901885095","seed":104389283176104181479437310000389222849454665499755610789308821908951901885095,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833128615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1833128615' seed=104389283176104181479437310000389222849454665499755610789308821908951901885095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104389283176104181479437310000389222849454665499755610789308821908951901885095 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"74.edn_err.82810932909336268897329302446259634174687205702687473174006662768249345488381","seed":82810932909336268897329302446259634174687205702687473174006662768249345488381,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3837605373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3837605373' seed=82810932909336268897329302446259634174687205702687473174006662768249345488381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82810932909336268897329302446259634174687205702687473174006662768249345488381 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/74.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"75.edn_genbits.56945402109412622522080824514174500680365526877062799018669183203546132730490","seed":56945402109412622522080824514174500680365526877062799018669183203546132730490,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540262010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2540262010' seed=56945402109412622522080824514174500680365526877062799018669183203546132730490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56945402109412622522080824514174500680365526877062799018669183203546132730490 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"75.edn_alert.74693362558239186508435512247733810016596753049538904512163879547472054226358","seed":74693362558239186508435512247733810016596753049538904512163879547472054226358,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=932089270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.932089270' seed=74693362558239186508435512247733810016596753049538904512163879547472054226358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74693362558239186508435512247733810016596753049538904512163879547472054226358 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"75.edn_err.44045670570059526262012607684049451620383695425786231535997872568795750548654","seed":44045670570059526262012607684049451620383695425786231535997872568795750548654,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1486963886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1486963886' seed=44045670570059526262012607684049451620383695425786231535997872568795750548654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44045670570059526262012607684049451620383695425786231535997872568795750548654 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/75.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"76.edn_genbits.86933130662403096324927159290012586314838668850453025085637084639652344073855","seed":86933130662403096324927159290012586314838668850453025085637084639652344073855,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3956641407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3956641407' seed=86933130662403096324927159290012586314838668850453025085637084639652344073855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86933130662403096324927159290012586314838668850453025085637084639652344073855 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"76.edn_alert.112715968876747157639015007279276326677176803039526718855382906433440954090169","seed":112715968876747157639015007279276326677176803039526718855382906433440954090169,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3392307897 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3392307897' seed=112715968876747157639015007279276326677176803039526718855382906433440954090169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112715968876747157639015007279276326677176803039526718855382906433440954090169 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"76.edn_err.110313571367302647819561915834911280829243152399125572250613769528861525208256","seed":110313571367302647819561915834911280829243152399125572250613769528861525208256,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575859904 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.575859904' seed=110313571367302647819561915834911280829243152399125572250613769528861525208256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110313571367302647819561915834911280829243152399125572250613769528861525208256 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/76.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"77.edn_genbits.85796685615410292599485938145798815536869224459187495119458410475893836127062","seed":85796685615410292599485938145798815536869224459187495119458410475893836127062,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=222206806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.222206806' seed=85796685615410292599485938145798815536869224459187495119458410475893836127062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85796685615410292599485938145798815536869224459187495119458410475893836127062 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"77.edn_alert.17037848581242360898861888936001338836312182109696033202026574723151716807307","seed":17037848581242360898861888936001338836312182109696033202026574723151716807307,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3249402507 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3249402507' seed=17037848581242360898861888936001338836312182109696033202026574723151716807307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17037848581242360898861888936001338836312182109696033202026574723151716807307 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"77.edn_err.74306751805217620710457018990863959328284448323690364554356555833562075344779","seed":74306751805217620710457018990863959328284448323690364554356555833562075344779,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2400038795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2400038795' seed=74306751805217620710457018990863959328284448323690364554356555833562075344779 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74306751805217620710457018990863959328284448323690364554356555833562075344779 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/77.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"78.edn_genbits.30738352079511004677094040758212106348361358845483541388568966642953487447151","seed":30738352079511004677094040758212106348361358845483541388568966642953487447151,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278983791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.278983791' seed=30738352079511004677094040758212106348361358845483541388568966642953487447151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30738352079511004677094040758212106348361358845483541388568966642953487447151 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"78.edn_alert.58106421843148629191640957981671674124816248105090720658995094488519579615939","seed":58106421843148629191640957981671674124816248105090720658995094488519579615939,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1171342019 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1171342019' seed=58106421843148629191640957981671674124816248105090720658995094488519579615939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58106421843148629191640957981671674124816248105090720658995094488519579615939 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"78.edn_err.64579375524469048005222291759851596549437424563124244023130829196073334188224","seed":64579375524469048005222291759851596549437424563124244023130829196073334188224,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=224635072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.224635072' seed=64579375524469048005222291759851596549437424563124244023130829196073334188224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64579375524469048005222291759851596549437424563124244023130829196073334188224 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/78.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"79.edn_genbits.50344512147698684772136006679652426363362983696891638427366355458024774838807","seed":50344512147698684772136006679652426363362983696891638427366355458024774838807,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=253504023 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.253504023' seed=50344512147698684772136006679652426363362983696891638427366355458024774838807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50344512147698684772136006679652426363362983696891638427366355458024774838807 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"79.edn_alert.70361261293860468852157321030065673422200787054971731971216051894512402193950","seed":70361261293860468852157321030065673422200787054971731971216051894512402193950,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445696542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2445696542' seed=70361261293860468852157321030065673422200787054971731971216051894512402193950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70361261293860468852157321030065673422200787054971731971216051894512402193950 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"79.edn_err.90756717368390193034550860454196370120257741674875455571109275715566711524621","seed":90756717368390193034550860454196370120257741674875455571109275715566711524621,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1347865869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1347865869' seed=90756717368390193034550860454196370120257741674875455571109275715566711524621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90756717368390193034550860454196370120257741674875455571109275715566711524621 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/79.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"80.edn_genbits.36110909924984872426274728933734977556650068703546952763945648434145245977200","seed":36110909924984872426274728933734977556650068703546952763945648434145245977200,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513989232 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.513989232' seed=36110909924984872426274728933734977556650068703546952763945648434145245977200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36110909924984872426274728933734977556650068703546952763945648434145245977200 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"80.edn_alert.12145054293902085046922563221971397841371086949731595435001679216040518142390","seed":12145054293902085046922563221971397841371086949731595435001679216040518142390,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3239627190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3239627190' seed=12145054293902085046922563221971397841371086949731595435001679216040518142390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12145054293902085046922563221971397841371086949731595435001679216040518142390 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"80.edn_err.103131605017730093946718015898746714103172215228177986163976136301346083474269","seed":103131605017730093946718015898746714103172215228177986163976136301346083474269,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463533917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2463533917' seed=103131605017730093946718015898746714103172215228177986163976136301346083474269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103131605017730093946718015898746714103172215228177986163976136301346083474269 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/80.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"81.edn_genbits.16124557784537715437539767754048621858830811704332781507149366032956377097734","seed":16124557784537715437539767754048621858830811704332781507149366032956377097734,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=906323462 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.906323462' seed=16124557784537715437539767754048621858830811704332781507149366032956377097734 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16124557784537715437539767754048621858830811704332781507149366032956377097734 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"81.edn_alert.83088637205954392465289349785492187192004294770158852177061695540531622832722","seed":83088637205954392465289349785492187192004294770158852177061695540531622832722,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256688722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.4256688722' seed=83088637205954392465289349785492187192004294770158852177061695540531622832722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83088637205954392465289349785492187192004294770158852177061695540531622832722 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"81.edn_err.86330318784215139248221856183564010819031627604596136011110869100394554026180","seed":86330318784215139248221856183564010819031627604596136011110869100394554026180,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1768122564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1768122564' seed=86330318784215139248221856183564010819031627604596136011110869100394554026180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86330318784215139248221856183564010819031627604596136011110869100394554026180 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/81.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"82.edn_genbits.104000020259000788010168344762334899658068356590814998888853455305503848549289","seed":104000020259000788010168344762334899658068356590814998888853455305503848549289,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1449151401 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1449151401' seed=104000020259000788010168344762334899658068356590814998888853455305503848549289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104000020259000788010168344762334899658068356590814998888853455305503848549289 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"82.edn_alert.108033818582220740018487580108746170879399583927897304971397318121938610682411","seed":108033818582220740018487580108746170879399583927897304971397318121938610682411,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2434398763 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2434398763' seed=108033818582220740018487580108746170879399583927897304971397318121938610682411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108033818582220740018487580108746170879399583927897304971397318121938610682411 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"82.edn_err.35357223486062932311117644518423884057391106361481517546712328486109652845983","seed":35357223486062932311117644518423884057391106361481517546712328486109652845983,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65144223 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.65144223' seed=35357223486062932311117644518423884057391106361481517546712328486109652845983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35357223486062932311117644518423884057391106361481517546712328486109652845983 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/82.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"83.edn_genbits.61868070897160304029697365426745418617542879191134056680820652977470886030161","seed":61868070897160304029697365426745418617542879191134056680820652977470886030161,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3285101393 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3285101393' seed=61868070897160304029697365426745418617542879191134056680820652977470886030161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61868070897160304029697365426745418617542879191134056680820652977470886030161 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"83.edn_alert.24791331786368180167805335730636275828242405818177585379040725716690968425492","seed":24791331786368180167805335730636275828242405818177585379040725716690968425492,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560879124 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3560879124' seed=24791331786368180167805335730636275828242405818177585379040725716690968425492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24791331786368180167805335730636275828242405818177585379040725716690968425492 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"83.edn_err.81884833105008315875448539160008126602005765527556952754286089217363178288095","seed":81884833105008315875448539160008126602005765527556952754286089217363178288095,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=620884959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.620884959' seed=81884833105008315875448539160008126602005765527556952754286089217363178288095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81884833105008315875448539160008126602005765527556952754286089217363178288095 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/83.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"84.edn_genbits.39952627018207290467149119398526785556299950101766950905469806201050802164025","seed":39952627018207290467149119398526785556299950101766950905469806201050802164025,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=644878649 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.644878649' seed=39952627018207290467149119398526785556299950101766950905469806201050802164025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39952627018207290467149119398526785556299950101766950905469806201050802164025 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"84.edn_alert.109906219057146326291731002448486594920324320443318742415171151435123086368121","seed":109906219057146326291731002448486594920324320443318742415171151435123086368121,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034277753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2034277753' seed=109906219057146326291731002448486594920324320443318742415171151435123086368121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109906219057146326291731002448486594920324320443318742415171151435123086368121 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"84.edn_err.8571755971420470027940537255485200412039706045841077929431132955423022563982","seed":8571755971420470027940537255485200412039706045841077929431132955423022563982,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1093976718 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1093976718' seed=8571755971420470027940537255485200412039706045841077929431132955423022563982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8571755971420470027940537255485200412039706045841077929431132955423022563982 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/84.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"85.edn_genbits.74452333857372373834259758514327485162043791015145030700223894896912729244783","seed":74452333857372373834259758514327485162043791015145030700223894896912729244783,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3312321647 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3312321647' seed=74452333857372373834259758514327485162043791015145030700223894896912729244783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74452333857372373834259758514327485162043791015145030700223894896912729244783 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"85.edn_alert.36416028917517699692168482151859148162485862483737642814806362184581863296897","seed":36416028917517699692168482151859148162485862483737642814806362184581863296897,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2695745409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2695745409' seed=36416028917517699692168482151859148162485862483737642814806362184581863296897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36416028917517699692168482151859148162485862483737642814806362184581863296897 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"85.edn_err.109729023580464847933187735413791997098429511136485956118531563970430463854376","seed":109729023580464847933187735413791997098429511136485956118531563970430463854376,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3922413352 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3922413352' seed=109729023580464847933187735413791997098429511136485956118531563970430463854376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109729023580464847933187735413791997098429511136485956118531563970430463854376 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/85.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"86.edn_genbits.89981483970645636052582408896877541979109416532805385895728344276974420101219","seed":89981483970645636052582408896877541979109416532805385895728344276974420101219,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2338850915 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2338850915' seed=89981483970645636052582408896877541979109416532805385895728344276974420101219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89981483970645636052582408896877541979109416532805385895728344276974420101219 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"86.edn_alert.42640877621988175916927188273817440195230846307420511879977843144182769103098","seed":42640877621988175916927188273817440195230846307420511879977843144182769103098,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3211243770 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3211243770' seed=42640877621988175916927188273817440195230846307420511879977843144182769103098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42640877621988175916927188273817440195230846307420511879977843144182769103098 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"86.edn_err.17747500766470219921590056467541352343572898761027859401774584179942878953295","seed":17747500766470219921590056467541352343572898761027859401774584179942878953295,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3761061711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3761061711' seed=17747500766470219921590056467541352343572898761027859401774584179942878953295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17747500766470219921590056467541352343572898761027859401774584179942878953295 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/86.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"87.edn_genbits.96861394583895967588517640266685937009821988241845589240332815284849338144560","seed":96861394583895967588517640266685937009821988241845589240332815284849338144560,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2084493104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2084493104' seed=96861394583895967588517640266685937009821988241845589240332815284849338144560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96861394583895967588517640266685937009821988241845589240332815284849338144560 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"87.edn_alert.94650903001680289733180897361119674505217377037806447667396798301321336438227","seed":94650903001680289733180897361119674505217377037806447667396798301321336438227,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1116454355 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1116454355' seed=94650903001680289733180897361119674505217377037806447667396798301321336438227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94650903001680289733180897361119674505217377037806447667396798301321336438227 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"87.edn_err.105506849932709762722138065242003619246325600611814217846601635787772684558422","seed":105506849932709762722138065242003619246325600611814217846601635787772684558422,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4008337494 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4008337494' seed=105506849932709762722138065242003619246325600611814217846601635787772684558422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105506849932709762722138065242003619246325600611814217846601635787772684558422 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/87.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"88.edn_genbits.18101649536697533704326542743601887478437555631223205490516943339895335052033","seed":18101649536697533704326542743601887478437555631223205490516943339895335052033,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287021313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1287021313' seed=18101649536697533704326542743601887478437555631223205490516943339895335052033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18101649536697533704326542743601887478437555631223205490516943339895335052033 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"88.edn_alert.76536428728631101436632358760736467311341688737770988497723044621357029333293","seed":76536428728631101436632358760736467311341688737770988497723044621357029333293,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2804750637 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2804750637' seed=76536428728631101436632358760736467311341688737770988497723044621357029333293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76536428728631101436632358760736467311341688737770988497723044621357029333293 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"88.edn_err.96509861100150616832408392941635235675998850273816646393015671265851762537320","seed":96509861100150616832408392941635235675998850273816646393015671265851762537320,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3970167656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3970167656' seed=96509861100150616832408392941635235675998850273816646393015671265851762537320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96509861100150616832408392941635235675998850273816646393015671265851762537320 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/88.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"89.edn_genbits.29595768881815919344890296454948615787922403843793125961214080684798566813632","seed":29595768881815919344890296454948615787922403843793125961214080684798566813632,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1049710528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1049710528' seed=29595768881815919344890296454948615787922403843793125961214080684798566813632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29595768881815919344890296454948615787922403843793125961214080684798566813632 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"89.edn_alert.55999479347535866254247949042724955210262802754827235511990517219719737300151","seed":55999479347535866254247949042724955210262802754827235511990517219719737300151,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3135034551 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3135034551' seed=55999479347535866254247949042724955210262802754827235511990517219719737300151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55999479347535866254247949042724955210262802754827235511990517219719737300151 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"89.edn_err.34314843344940256501837392904494379018378250550638727263481863595615263781591","seed":34314843344940256501837392904494379018378250550638727263481863595615263781591,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363197143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.363197143' seed=34314843344940256501837392904494379018378250550638727263481863595615263781591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34314843344940256501837392904494379018378250550638727263481863595615263781591 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/89.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"90.edn_genbits.58944719265831548151105067015040156574495094619773294844594064860320564057635","seed":58944719265831548151105067015040156574495094619773294844594064860320564057635,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3133478435 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3133478435' seed=58944719265831548151105067015040156574495094619773294844594064860320564057635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58944719265831548151105067015040156574495094619773294844594064860320564057635 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"90.edn_alert.12641456454124642093726812765672856004300302800546938693975171404213337479306","seed":12641456454124642093726812765672856004300302800546938693975171404213337479306,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=939022474 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.939022474' seed=12641456454124642093726812765672856004300302800546938693975171404213337479306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12641456454124642093726812765672856004300302800546938693975171404213337479306 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"90.edn_err.41052847395833644441778046899220222578473330579757394340936458209199038617374","seed":41052847395833644441778046899220222578473330579757394340936458209199038617374,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27481886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.27481886' seed=41052847395833644441778046899220222578473330579757394340936458209199038617374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41052847395833644441778046899220222578473330579757394340936458209199038617374 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/90.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"91.edn_genbits.56001740513074980920636804316795922311496758639175611298375133529459934693398","seed":56001740513074980920636804316795922311496758639175611298375133529459934693398,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=254871574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.254871574' seed=56001740513074980920636804316795922311496758639175611298375133529459934693398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56001740513074980920636804316795922311496758639175611298375133529459934693398 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"91.edn_alert.75876648891379639483295970807862837082812041821029885916245775011290204050861","seed":75876648891379639483295970807862837082812041821029885916245775011290204050861,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841010093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1841010093' seed=75876648891379639483295970807862837082812041821029885916245775011290204050861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75876648891379639483295970807862837082812041821029885916245775011290204050861 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"91.edn_err.33737633673787120503257019553855396424916464772666795004781948052308422094711","seed":33737633673787120503257019553855396424916464772666795004781948052308422094711,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3784372087 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3784372087' seed=33737633673787120503257019553855396424916464772666795004781948052308422094711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33737633673787120503257019553855396424916464772666795004781948052308422094711 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/91.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"92.edn_genbits.83587730957514545821153488830024462393036894823715634190760800853692882865496","seed":83587730957514545821153488830024462393036894823715634190760800853692882865496,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727515992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1727515992' seed=83587730957514545821153488830024462393036894823715634190760800853692882865496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83587730957514545821153488830024462393036894823715634190760800853692882865496 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"92.edn_alert.17606378277368340179096218717365109909256406771824802936448619033779139462864","seed":17606378277368340179096218717365109909256406771824802936448619033779139462864,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=127092432 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.127092432' seed=17606378277368340179096218717365109909256406771824802936448619033779139462864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17606378277368340179096218717365109909256406771824802936448619033779139462864 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"92.edn_err.71715141458568535373292505638164523366999604436443967649433117162566547410255","seed":71715141458568535373292505638164523366999604436443967649433117162566547410255,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939241295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3939241295' seed=71715141458568535373292505638164523366999604436443967649433117162566547410255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71715141458568535373292505638164523366999604436443967649433117162566547410255 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/92.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"93.edn_genbits.103192685399086373926928090231519437524383484346142705098010408990103633871063","seed":103192685399086373926928090231519437524383484346142705098010408990103633871063,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743208663 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1743208663' seed=103192685399086373926928090231519437524383484346142705098010408990103633871063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103192685399086373926928090231519437524383484346142705098010408990103633871063 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"93.edn_alert.1610579823604173766893515446056631700074720118301423393047052614188743844164","seed":1610579823604173766893515446056631700074720118301423393047052614188743844164,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010098500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1010098500' seed=1610579823604173766893515446056631700074720118301423393047052614188743844164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1610579823604173766893515446056631700074720118301423393047052614188743844164 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"93.edn_err.81000988164888339677964499883253892766961064878922728888260936646208282134313","seed":81000988164888339677964499883253892766961064878922728888260936646208282134313,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2976876329 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2976876329' seed=81000988164888339677964499883253892766961064878922728888260936646208282134313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81000988164888339677964499883253892766961064878922728888260936646208282134313 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/93.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"94.edn_genbits.104096828558556065583015419961250878424128038955516056719225351739908541161605","seed":104096828558556065583015419961250878424128038955516056719225351739908541161605,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1211146373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1211146373' seed=104096828558556065583015419961250878424128038955516056719225351739908541161605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104096828558556065583015419961250878424128038955516056719225351739908541161605 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"94.edn_alert.25668808566574320465887068637761590038916961115311784910006316219694362983183","seed":25668808566574320465887068637761590038916961115311784910006316219694362983183,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3935632143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3935632143' seed=25668808566574320465887068637761590038916961115311784910006316219694362983183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25668808566574320465887068637761590038916961115311784910006316219694362983183 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"94.edn_err.58033390776821657695005152862661657451863461328945449517951748718806005061786","seed":58033390776821657695005152862661657451863461328945449517951748718806005061786,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140622490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3140622490' seed=58033390776821657695005152862661657451863461328945449517951748718806005061786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58033390776821657695005152862661657451863461328945449517951748718806005061786 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/94.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"95.edn_genbits.21151789564169799289941944867712340022812196818637515565775572718544654682437","seed":21151789564169799289941944867712340022812196818637515565775572718544654682437,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=608684357 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.608684357' seed=21151789564169799289941944867712340022812196818637515565775572718544654682437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21151789564169799289941944867712340022812196818637515565775572718544654682437 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"95.edn_alert.59370130352599876931524012218666935278456727514903793121063949925711024180459","seed":59370130352599876931524012218666935278456727514903793121063949925711024180459,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3034008811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3034008811' seed=59370130352599876931524012218666935278456727514903793121063949925711024180459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59370130352599876931524012218666935278456727514903793121063949925711024180459 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"95.edn_err.31937782437497248864077719102242497162803864553614212000629314040765336821589","seed":31937782437497248864077719102242497162803864553614212000629314040765336821589,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3549994837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3549994837' seed=31937782437497248864077719102242497162803864553614212000629314040765336821589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31937782437497248864077719102242497162803864553614212000629314040765336821589 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/95.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"96.edn_genbits.4412492567919218140978686096384947730935441676294885732397094145646651989555","seed":4412492567919218140978686096384947730935441676294885732397094145646651989555,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2926272051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2926272051' seed=4412492567919218140978686096384947730935441676294885732397094145646651989555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4412492567919218140978686096384947730935441676294885732397094145646651989555 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"96.edn_alert.115456807240274340907700084920526048158743574616338566239251478848725638952385","seed":115456807240274340907700084920526048158743574616338566239251478848725638952385,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1028109761 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1028109761' seed=115456807240274340907700084920526048158743574616338566239251478848725638952385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115456807240274340907700084920526048158743574616338566239251478848725638952385 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"96.edn_err.84016710554585863748171161385562609155760784865098580938984899841112284392944","seed":84016710554585863748171161385562609155760784865098580938984899841112284392944,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319169520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1319169520' seed=84016710554585863748171161385562609155760784865098580938984899841112284392944 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84016710554585863748171161385562609155760784865098580938984899841112284392944 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/96.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"97.edn_genbits.19602535456338024700514668775728433562290665417046351010102855662531459775647","seed":19602535456338024700514668775728433562290665417046351010102855662531459775647,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=106790047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.106790047' seed=19602535456338024700514668775728433562290665417046351010102855662531459775647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19602535456338024700514668775728433562290665417046351010102855662531459775647 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"97.edn_alert.73041387855728834258373702093944639872417796696150818155758813011387675554619","seed":73041387855728834258373702093944639872417796696150818155758813011387675554619,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2142745403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2142745403' seed=73041387855728834258373702093944639872417796696150818155758813011387675554619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73041387855728834258373702093944639872417796696150818155758813011387675554619 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"97.edn_err.8373848385963980671069294293768115360068830889617278274852794424555977919404","seed":8373848385963980671069294293768115360068830889617278274852794424555977919404,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1375292332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1375292332' seed=8373848385963980671069294293768115360068830889617278274852794424555977919404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8373848385963980671069294293768115360068830889617278274852794424555977919404 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/97.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"98.edn_genbits.68517303446640549423655181480683313345326680307639086320158599887084714190916","seed":68517303446640549423655181480683313345326680307639086320158599887084714190916,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2473846852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2473846852' seed=68517303446640549423655181480683313345326680307639086320158599887084714190916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68517303446640549423655181480683313345326680307639086320158599887084714190916 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"98.edn_alert.80345525436166575984649768445920398853105354980859716870256407731335154809972","seed":80345525436166575984649768445920398853105354980859716870256407731335154809972,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4017273972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.4017273972' seed=80345525436166575984649768445920398853105354980859716870256407731335154809972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80345525436166575984649768445920398853105354980859716870256407731335154809972 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"98.edn_err.85104520391288794853146155634504589630930314681190212002355812336477965337926","seed":85104520391288794853146155634504589630930314681190212002355812336477965337926,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2820883782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2820883782' seed=85104520391288794853146155634504589630930314681190212002355812336477965337926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85104520391288794853146155634504589630930314681190212002355812336477965337926 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/98.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_genbits","qual_name":"99.edn_genbits.63240212486218008031606257573138070089991722964554969033333763122202405757970","seed":63240212486218008031606257573138070089991722964554969033333763122202405757970,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_genbits/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2068833298 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2068833298' seed=63240212486218008031606257573138070089991722964554969033333763122202405757970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63240212486218008031606257573138070089991722964554969033333763122202405757970 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"99.edn_alert.115313274103677249327286772735935965254107944046516304456826383133761482283288","seed":115313274103677249327286772735935965254107944046516304456826383133761482283288,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1078221080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1078221080' seed=115313274103677249327286772735935965254107944046516304456826383133761482283288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115313274103677249327286772735935965254107944046516304456826383133761482283288 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_err","qual_name":"99.edn_err.88161853844914383976546458073512982287071056160923521384364055774246563654491","seed":88161853844914383976546458073512982287071056160923521384364055774246563654491,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443174235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3443174235' seed=88161853844914383976546458073512982287071056160923521384364055774246563654491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88161853844914383976546458073512982287071056160923521384364055774246563654491 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/99.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"100.edn_alert.83933368278090226210459585410861717491940543952375318621271281799350919339923","seed":83933368278090226210459585410861717491940543952375318621271281799350919339923,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/100.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/100.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417125779 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1417125779' seed=83933368278090226210459585410861717491940543952375318621271281799350919339923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83933368278090226210459585410861717491940543952375318621271281799350919339923 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/100.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"101.edn_alert.115553942931971738877321666614255188684023390457098387282134015107376356716702","seed":115553942931971738877321666614255188684023390457098387282134015107376356716702,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/101.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/101.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1993535646 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1993535646' seed=115553942931971738877321666614255188684023390457098387282134015107376356716702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115553942931971738877321666614255188684023390457098387282134015107376356716702 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/101.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"102.edn_alert.39536042760152981070191949780428474021548901175820152823840888480971406607874","seed":39536042760152981070191949780428474021548901175820152823840888480971406607874,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/102.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/102.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3739387394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3739387394' seed=39536042760152981070191949780428474021548901175820152823840888480971406607874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39536042760152981070191949780428474021548901175820152823840888480971406607874 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/102.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"103.edn_alert.26929419612769004784592958848507948769196776795306101212107546844579886707080","seed":26929419612769004784592958848507948769196776795306101212107546844579886707080,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/103.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/103.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1808445832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1808445832' seed=26929419612769004784592958848507948769196776795306101212107546844579886707080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26929419612769004784592958848507948769196776795306101212107546844579886707080 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/103.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"104.edn_alert.54054510448988328725071506568346366788788767821747297345515561832743894328777","seed":54054510448988328725071506568346366788788767821747297345515561832743894328777,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/104.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/104.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667755977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.667755977' seed=54054510448988328725071506568346366788788767821747297345515561832743894328777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54054510448988328725071506568346366788788767821747297345515561832743894328777 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/104.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"105.edn_alert.88244584665567215567005323298600043472625845768927988260310211521316231816018","seed":88244584665567215567005323298600043472625845768927988260310211521316231816018,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/105.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/105.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1979949906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1979949906' seed=88244584665567215567005323298600043472625845768927988260310211521316231816018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88244584665567215567005323298600043472625845768927988260310211521316231816018 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/105.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"106.edn_alert.109693251109148606975027788275821411219133895453335731111194372367868999666952","seed":109693251109148606975027788275821411219133895453335731111194372367868999666952,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/106.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/106.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2443611400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2443611400' seed=109693251109148606975027788275821411219133895453335731111194372367868999666952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109693251109148606975027788275821411219133895453335731111194372367868999666952 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/106.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"107.edn_alert.32443595888841678027883595074029881635110982970346013374257680796894952245762","seed":32443595888841678027883595074029881635110982970346013374257680796894952245762,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/107.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/107.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321186818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3321186818' seed=32443595888841678027883595074029881635110982970346013374257680796894952245762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32443595888841678027883595074029881635110982970346013374257680796894952245762 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/107.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"108.edn_alert.14976256454511954719191033356957048569017622027474953625937741006492962110299","seed":14976256454511954719191033356957048569017622027474953625937741006492962110299,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/108.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/108.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2414328667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2414328667' seed=14976256454511954719191033356957048569017622027474953625937741006492962110299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14976256454511954719191033356957048569017622027474953625937741006492962110299 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/108.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"109.edn_alert.53968916241481776168631137126009084238748502757541226598971133340492543493294","seed":53968916241481776168631137126009084238748502757541226598971133340492543493294,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/109.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/109.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1346831534 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1346831534' seed=53968916241481776168631137126009084238748502757541226598971133340492543493294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53968916241481776168631137126009084238748502757541226598971133340492543493294 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/109.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"110.edn_alert.6857684987553785914754139987864281159016703504182153049995185677408396068274","seed":6857684987553785914754139987864281159016703504182153049995185677408396068274,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/110.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/110.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3784263090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3784263090' seed=6857684987553785914754139987864281159016703504182153049995185677408396068274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6857684987553785914754139987864281159016703504182153049995185677408396068274 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/110.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"111.edn_alert.87292669671189680093020389075563458189652525060760610612009680384888455169630","seed":87292669671189680093020389075563458189652525060760610612009680384888455169630,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/111.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/111.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4260234846 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4260234846' seed=87292669671189680093020389075563458189652525060760610612009680384888455169630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87292669671189680093020389075563458189652525060760610612009680384888455169630 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/111.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"112.edn_alert.55536496820819767873417344742528004207038480795269221411245163545557234578103","seed":55536496820819767873417344742528004207038480795269221411245163545557234578103,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/112.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/112.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2116252343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2116252343' seed=55536496820819767873417344742528004207038480795269221411245163545557234578103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55536496820819767873417344742528004207038480795269221411245163545557234578103 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/112.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"113.edn_alert.104458633821903832168480067581245898508989563960298286337294788187046713184250","seed":104458633821903832168480067581245898508989563960298286337294788187046713184250,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/113.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/113.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740932602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2740932602' seed=104458633821903832168480067581245898508989563960298286337294788187046713184250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104458633821903832168480067581245898508989563960298286337294788187046713184250 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/113.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"114.edn_alert.57784108229113002198283747556754092313495569402987451785255351292478034215493","seed":57784108229113002198283747556754092313495569402987451785255351292478034215493,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/114.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/114.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317367365 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3317367365' seed=57784108229113002198283747556754092313495569402987451785255351292478034215493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57784108229113002198283747556754092313495569402987451785255351292478034215493 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/114.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"115.edn_alert.37201769511507524443206575514706825942021141122155936315614899233263339742999","seed":37201769511507524443206575514706825942021141122155936315614899233263339742999,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/115.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/115.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286724887 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2286724887' seed=37201769511507524443206575514706825942021141122155936315614899233263339742999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37201769511507524443206575514706825942021141122155936315614899233263339742999 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/115.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"116.edn_alert.21089142291633334141333672515435065348922692565738589589620409381064490223164","seed":21089142291633334141333672515435065348922692565738589589620409381064490223164,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/116.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/116.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3624273468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3624273468' seed=21089142291633334141333672515435065348922692565738589589620409381064490223164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21089142291633334141333672515435065348922692565738589589620409381064490223164 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/116.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"117.edn_alert.12842119495764276783124031295738392741405038965639118531490849236583895191015","seed":12842119495764276783124031295738392741405038965639118531490849236583895191015,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/117.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/117.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=715050471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.715050471' seed=12842119495764276783124031295738392741405038965639118531490849236583895191015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12842119495764276783124031295738392741405038965639118531490849236583895191015 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/117.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"118.edn_alert.50664948241407566729844627178446558062761771697752618371000482094850081566475","seed":50664948241407566729844627178446558062761771697752618371000482094850081566475,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/118.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/118.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1258827531 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1258827531' seed=50664948241407566729844627178446558062761771697752618371000482094850081566475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50664948241407566729844627178446558062761771697752618371000482094850081566475 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/118.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"119.edn_alert.16325962644419582459042521744772445066780018922360572866113985150911600340757","seed":16325962644419582459042521744772445066780018922360572866113985150911600340757,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/119.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/119.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1350250261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1350250261' seed=16325962644419582459042521744772445066780018922360572866113985150911600340757 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16325962644419582459042521744772445066780018922360572866113985150911600340757 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/119.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"120.edn_alert.18171663860423136718093529517439738747185907168885453570044364273820393449210","seed":18171663860423136718093529517439738747185907168885453570044364273820393449210,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/120.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/120.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1945544442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1945544442' seed=18171663860423136718093529517439738747185907168885453570044364273820393449210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18171663860423136718093529517439738747185907168885453570044364273820393449210 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/120.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"121.edn_alert.74623447886532150169421850739075074758983750385013975475840919012935534074901","seed":74623447886532150169421850739075074758983750385013975475840919012935534074901,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/121.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/121.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3632225301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3632225301' seed=74623447886532150169421850739075074758983750385013975475840919012935534074901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74623447886532150169421850739075074758983750385013975475840919012935534074901 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/121.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"122.edn_alert.63989241293484871414175974120512803431316744377182587291558731535972834828612","seed":63989241293484871414175974120512803431316744377182587291558731535972834828612,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/122.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/122.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2954191172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2954191172' seed=63989241293484871414175974120512803431316744377182587291558731535972834828612 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63989241293484871414175974120512803431316744377182587291558731535972834828612 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/122.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"123.edn_alert.46601231667634011720525807492408703079381687720435762411965667541016662599908","seed":46601231667634011720525807492408703079381687720435762411965667541016662599908,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/123.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/123.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812031716 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1812031716' seed=46601231667634011720525807492408703079381687720435762411965667541016662599908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46601231667634011720525807492408703079381687720435762411965667541016662599908 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/123.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"124.edn_alert.64279369394316093998357939484148025796497852578935937383859877869923438332549","seed":64279369394316093998357939484148025796497852578935937383859877869923438332549,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/124.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/124.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=813075077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.813075077' seed=64279369394316093998357939484148025796497852578935937383859877869923438332549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64279369394316093998357939484148025796497852578935937383859877869923438332549 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/124.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"125.edn_alert.67739825252228266786938090143662292619256103267973267906938098575310642791438","seed":67739825252228266786938090143662292619256103267973267906938098575310642791438,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/125.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/125.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2955199502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2955199502' seed=67739825252228266786938090143662292619256103267973267906938098575310642791438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67739825252228266786938090143662292619256103267973267906938098575310642791438 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/125.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"126.edn_alert.59485781604751607648550189948063160840883159609253846555352173075005922514215","seed":59485781604751607648550189948063160840883159609253846555352173075005922514215,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/126.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/126.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1810011431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1810011431' seed=59485781604751607648550189948063160840883159609253846555352173075005922514215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59485781604751607648550189948063160840883159609253846555352173075005922514215 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/126.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"127.edn_alert.46749736726665220382122172216487687514479125108739249982971492641068652642092","seed":46749736726665220382122172216487687514479125108739249982971492641068652642092,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/127.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/127.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1306214188 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1306214188' seed=46749736726665220382122172216487687514479125108739249982971492641068652642092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46749736726665220382122172216487687514479125108739249982971492641068652642092 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/127.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"128.edn_alert.76569410318509936305412157790017252433370606080848024323749991347513782469133","seed":76569410318509936305412157790017252433370606080848024323749991347513782469133,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/128.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/128.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083974669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.4083974669' seed=76569410318509936305412157790017252433370606080848024323749991347513782469133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76569410318509936305412157790017252433370606080848024323749991347513782469133 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/128.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"129.edn_alert.68429596064133079764703321181671924606095739775740253112439739102610084992765","seed":68429596064133079764703321181671924606095739775740253112439739102610084992765,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/129.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/129.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1579816701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1579816701' seed=68429596064133079764703321181671924606095739775740253112439739102610084992765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68429596064133079764703321181671924606095739775740253112439739102610084992765 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/129.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"130.edn_alert.18961595705945401168434827791003190900646581505583750608340937840118342499962","seed":18961595705945401168434827791003190900646581505583750608340937840118342499962,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/130.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/130.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3099213434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3099213434' seed=18961595705945401168434827791003190900646581505583750608340937840118342499962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18961595705945401168434827791003190900646581505583750608340937840118342499962 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/130.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"131.edn_alert.9329351883278659117434832922010342761447528589147717605689430832198156408922","seed":9329351883278659117434832922010342761447528589147717605689430832198156408922,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/131.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/131.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=170776666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.170776666' seed=9329351883278659117434832922010342761447528589147717605689430832198156408922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9329351883278659117434832922010342761447528589147717605689430832198156408922 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/131.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"132.edn_alert.105076597082005388673332959696200090301975599707837775736055540019715654253615","seed":105076597082005388673332959696200090301975599707837775736055540019715654253615,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/132.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/132.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2898492463 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2898492463' seed=105076597082005388673332959696200090301975599707837775736055540019715654253615 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105076597082005388673332959696200090301975599707837775736055540019715654253615 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/132.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"133.edn_alert.13852206313477981680308371689136966304238617726502198435237597630750058471414","seed":13852206313477981680308371689136966304238617726502198435237597630750058471414,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/133.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/133.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1804197878 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1804197878' seed=13852206313477981680308371689136966304238617726502198435237597630750058471414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13852206313477981680308371689136966304238617726502198435237597630750058471414 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/133.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"134.edn_alert.78585181815432713788455711097099997592970770625353543175586154298671201218176","seed":78585181815432713788455711097099997592970770625353543175586154298671201218176,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/134.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/134.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4018892416 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.4018892416' seed=78585181815432713788455711097099997592970770625353543175586154298671201218176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78585181815432713788455711097099997592970770625353543175586154298671201218176 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/134.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"135.edn_alert.3392709058350101131091372779298881334995026483983465269003778519247711004336","seed":3392709058350101131091372779298881334995026483983465269003778519247711004336,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/135.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/135.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2011850416 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2011850416' seed=3392709058350101131091372779298881334995026483983465269003778519247711004336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3392709058350101131091372779298881334995026483983465269003778519247711004336 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/135.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"136.edn_alert.7373800569971891240124831436305801474594452263716001153133815090710411349117","seed":7373800569971891240124831436305801474594452263716001153133815090710411349117,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/136.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/136.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56495229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.56495229' seed=7373800569971891240124831436305801474594452263716001153133815090710411349117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7373800569971891240124831436305801474594452263716001153133815090710411349117 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/136.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"137.edn_alert.1206761973504526038644872748014151082965354053161577271979251873865707953696","seed":1206761973504526038644872748014151082965354053161577271979251873865707953696,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/137.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/137.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=495328800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.495328800' seed=1206761973504526038644872748014151082965354053161577271979251873865707953696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1206761973504526038644872748014151082965354053161577271979251873865707953696 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/137.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"138.edn_alert.87382770634495956177437902365291047099141815812652861821545211137942673785258","seed":87382770634495956177437902365291047099141815812652861821545211137942673785258,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/138.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/138.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3350299050 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3350299050' seed=87382770634495956177437902365291047099141815812652861821545211137942673785258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87382770634495956177437902365291047099141815812652861821545211137942673785258 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/138.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"139.edn_alert.55241111376851925081456715927793589997406157502963964253500106785898369426375","seed":55241111376851925081456715927793589997406157502963964253500106785898369426375,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/139.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/139.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3804537799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3804537799' seed=55241111376851925081456715927793589997406157502963964253500106785898369426375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55241111376851925081456715927793589997406157502963964253500106785898369426375 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/139.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"140.edn_alert.80710939288060616581717596324615799951800152979310141919862657406684985105970","seed":80710939288060616581717596324615799951800152979310141919862657406684985105970,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/140.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/140.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415809586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3415809586' seed=80710939288060616581717596324615799951800152979310141919862657406684985105970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80710939288060616581717596324615799951800152979310141919862657406684985105970 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/140.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"141.edn_alert.59914622153448329061156411565132271550621786329890217774673707779015251975881","seed":59914622153448329061156411565132271550621786329890217774673707779015251975881,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/141.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/141.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=506846921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.506846921' seed=59914622153448329061156411565132271550621786329890217774673707779015251975881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59914622153448329061156411565132271550621786329890217774673707779015251975881 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/141.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"142.edn_alert.60125970320441853614945118672407499473374304145697947970003768773944077071469","seed":60125970320441853614945118672407499473374304145697947970003768773944077071469,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/142.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/142.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=884356205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.884356205' seed=60125970320441853614945118672407499473374304145697947970003768773944077071469 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60125970320441853614945118672407499473374304145697947970003768773944077071469 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/142.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"143.edn_alert.32805520919701654525590054885789231034170039541378824566031121223644112667177","seed":32805520919701654525590054885789231034170039541378824566031121223644112667177,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/143.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/143.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2559754793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2559754793' seed=32805520919701654525590054885789231034170039541378824566031121223644112667177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32805520919701654525590054885789231034170039541378824566031121223644112667177 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/143.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"144.edn_alert.22987429031330822123336033339728118296797228995337107982270247490236753219662","seed":22987429031330822123336033339728118296797228995337107982270247490236753219662,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/144.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/144.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=390434894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.390434894' seed=22987429031330822123336033339728118296797228995337107982270247490236753219662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22987429031330822123336033339728118296797228995337107982270247490236753219662 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/144.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"145.edn_alert.101611255027699486125114025071502675367383123012964964727842294897765921067970","seed":101611255027699486125114025071502675367383123012964964727842294897765921067970,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/145.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/145.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376785346 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1376785346' seed=101611255027699486125114025071502675367383123012964964727842294897765921067970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101611255027699486125114025071502675367383123012964964727842294897765921067970 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/145.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"146.edn_alert.16618459565379945898248184773110136329999049844365840782604438306142851993704","seed":16618459565379945898248184773110136329999049844365840782604438306142851993704,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/146.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/146.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1749061736 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1749061736' seed=16618459565379945898248184773110136329999049844365840782604438306142851993704 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16618459565379945898248184773110136329999049844365840782604438306142851993704 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/146.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"147.edn_alert.111699082805546832848314152485097571946628076868348941897894337692839681288135","seed":111699082805546832848314152485097571946628076868348941897894337692839681288135,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/147.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/147.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=54355911 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.54355911' seed=111699082805546832848314152485097571946628076868348941897894337692839681288135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111699082805546832848314152485097571946628076868348941897894337692839681288135 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/147.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"148.edn_alert.14352414380516717973333454698383923369392884604929355736313088570647327581505","seed":14352414380516717973333454698383923369392884604929355736313088570647327581505,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/148.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/148.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3015746881 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3015746881' seed=14352414380516717973333454698383923369392884604929355736313088570647327581505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14352414380516717973333454698383923369392884604929355736313088570647327581505 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/148.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"149.edn_alert.29011129196210920849878820441377252316666707426935751099504509961211808420736","seed":29011129196210920849878820441377252316666707426935751099504509961211808420736,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/149.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/149.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208038784 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.4208038784' seed=29011129196210920849878820441377252316666707426935751099504509961211808420736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29011129196210920849878820441377252316666707426935751099504509961211808420736 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/149.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"150.edn_alert.111878135349193344570747508248273487847071651271083494398453221049928632135400","seed":111878135349193344570747508248273487847071651271083494398453221049928632135400,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/150.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/150.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=544370408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.544370408' seed=111878135349193344570747508248273487847071651271083494398453221049928632135400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111878135349193344570747508248273487847071651271083494398453221049928632135400 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/150.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"151.edn_alert.18640965896391782824224798045572259401712395383305737226415712439409560469798","seed":18640965896391782824224798045572259401712395383305737226415712439409560469798,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/151.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/151.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3627237670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3627237670' seed=18640965896391782824224798045572259401712395383305737226415712439409560469798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18640965896391782824224798045572259401712395383305737226415712439409560469798 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/151.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"152.edn_alert.69066393641330899772744335104251759966428181445076298959713227136535976177962","seed":69066393641330899772744335104251759966428181445076298959713227136535976177962,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/152.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/152.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2537779498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2537779498' seed=69066393641330899772744335104251759966428181445076298959713227136535976177962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69066393641330899772744335104251759966428181445076298959713227136535976177962 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/152.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"153.edn_alert.4198393738833253336195331106153286304227516588877058384709861142265754716673","seed":4198393738833253336195331106153286304227516588877058384709861142265754716673,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/153.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/153.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3445000705 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3445000705' seed=4198393738833253336195331106153286304227516588877058384709861142265754716673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4198393738833253336195331106153286304227516588877058384709861142265754716673 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/153.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"154.edn_alert.71179466440413443455189118113229933821001253722026176120818172077670435489965","seed":71179466440413443455189118113229933821001253722026176120818172077670435489965,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/154.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/154.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3164440749 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3164440749' seed=71179466440413443455189118113229933821001253722026176120818172077670435489965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71179466440413443455189118113229933821001253722026176120818172077670435489965 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/154.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"155.edn_alert.50259967895389882503687687118880867592547338669980211498976893694357549007393","seed":50259967895389882503687687118880867592547338669980211498976893694357549007393,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/155.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/155.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3539649057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3539649057' seed=50259967895389882503687687118880867592547338669980211498976893694357549007393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50259967895389882503687687118880867592547338669980211498976893694357549007393 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/155.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"156.edn_alert.96048618042487716108131198560311734989497522741058698137466621028556827249180","seed":96048618042487716108131198560311734989497522741058698137466621028556827249180,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/156.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/156.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052232220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1052232220' seed=96048618042487716108131198560311734989497522741058698137466621028556827249180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96048618042487716108131198560311734989497522741058698137466621028556827249180 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/156.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"157.edn_alert.40574000649766728072131951157347390374497457722160096105226551377278605578805","seed":40574000649766728072131951157347390374497457722160096105226551377278605578805,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/157.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/157.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2724844085 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2724844085' seed=40574000649766728072131951157347390374497457722160096105226551377278605578805 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40574000649766728072131951157347390374497457722160096105226551377278605578805 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/157.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"158.edn_alert.73663812610720663797141189516229245221573327773576322881698608558152762780849","seed":73663812610720663797141189516229245221573327773576322881698608558152762780849,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/158.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/158.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051351217 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3051351217' seed=73663812610720663797141189516229245221573327773576322881698608558152762780849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73663812610720663797141189516229245221573327773576322881698608558152762780849 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/158.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"159.edn_alert.16315269601169386048038959982840998190728225238451407224074573915173467638327","seed":16315269601169386048038959982840998190728225238451407224074573915173467638327,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/159.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/159.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2611399223 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2611399223' seed=16315269601169386048038959982840998190728225238451407224074573915173467638327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16315269601169386048038959982840998190728225238451407224074573915173467638327 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/159.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"160.edn_alert.3288974250269979593017616229281057939130753583304165835566565921393244054836","seed":3288974250269979593017616229281057939130753583304165835566565921393244054836,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/160.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/160.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2131961140 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2131961140' seed=3288974250269979593017616229281057939130753583304165835566565921393244054836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3288974250269979593017616229281057939130753583304165835566565921393244054836 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/160.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"161.edn_alert.4501923149801445123353077200500893311272912305320797331359562997793743620652","seed":4501923149801445123353077200500893311272912305320797331359562997793743620652,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/161.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/161.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3297167916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3297167916' seed=4501923149801445123353077200500893311272912305320797331359562997793743620652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4501923149801445123353077200500893311272912305320797331359562997793743620652 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/161.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"162.edn_alert.64946415088815156456761104833154349001641547105303397293469660102276840357067","seed":64946415088815156456761104833154349001641547105303397293469660102276840357067,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/162.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/162.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208131275 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.4208131275' seed=64946415088815156456761104833154349001641547105303397293469660102276840357067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64946415088815156456761104833154349001641547105303397293469660102276840357067 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/162.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"163.edn_alert.53589034903355529190148130499157864923148398262551918678133375767773694539561","seed":53589034903355529190148130499157864923148398262551918678133375767773694539561,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/163.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/163.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1573795625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1573795625' seed=53589034903355529190148130499157864923148398262551918678133375767773694539561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53589034903355529190148130499157864923148398262551918678133375767773694539561 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/163.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"164.edn_alert.37247006802988837880698529342016118700587770526771255632404449298292066075260","seed":37247006802988837880698529342016118700587770526771255632404449298292066075260,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/164.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/164.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835282044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3835282044' seed=37247006802988837880698529342016118700587770526771255632404449298292066075260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37247006802988837880698529342016118700587770526771255632404449298292066075260 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/164.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"165.edn_alert.91465040501682215979806710416968740824637159026253247915870150790975745484030","seed":91465040501682215979806710416968740824637159026253247915870150790975745484030,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/165.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/165.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740774142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2740774142' seed=91465040501682215979806710416968740824637159026253247915870150790975745484030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91465040501682215979806710416968740824637159026253247915870150790975745484030 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/165.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"166.edn_alert.15364065132578869862426586147436871062734468082057456469141668688511196173715","seed":15364065132578869862426586147436871062734468082057456469141668688511196173715,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/166.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/166.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953469843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1953469843' seed=15364065132578869862426586147436871062734468082057456469141668688511196173715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15364065132578869862426586147436871062734468082057456469141668688511196173715 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/166.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"167.edn_alert.114942648665034232517782901532307178458537868700489760723704539310586243945913","seed":114942648665034232517782901532307178458537868700489760723704539310586243945913,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/167.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/167.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=495818169 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.495818169' seed=114942648665034232517782901532307178458537868700489760723704539310586243945913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114942648665034232517782901532307178458537868700489760723704539310586243945913 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/167.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"168.edn_alert.92330749355755308657976149536207215156264848542094654241142816485635088769661","seed":92330749355755308657976149536207215156264848542094654241142816485635088769661,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/168.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/168.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1606738557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1606738557' seed=92330749355755308657976149536207215156264848542094654241142816485635088769661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92330749355755308657976149536207215156264848542094654241142816485635088769661 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/168.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"169.edn_alert.41559902433133963230692881617721939687503104132358783490739245623351864727436","seed":41559902433133963230692881617721939687503104132358783490739245623351864727436,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/169.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/169.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331435404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1331435404' seed=41559902433133963230692881617721939687503104132358783490739245623351864727436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41559902433133963230692881617721939687503104132358783490739245623351864727436 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/169.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"170.edn_alert.109055663582801085453128824016758893996359256357019185049590437027850258397516","seed":109055663582801085453128824016758893996359256357019185049590437027850258397516,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/170.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/170.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3786586444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3786586444' seed=109055663582801085453128824016758893996359256357019185049590437027850258397516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109055663582801085453128824016758893996359256357019185049590437027850258397516 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/170.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"171.edn_alert.23958481357064235471075332965494030180786207976908235896012613129447132444100","seed":23958481357064235471075332965494030180786207976908235896012613129447132444100,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/171.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/171.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237216196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2237216196' seed=23958481357064235471075332965494030180786207976908235896012613129447132444100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23958481357064235471075332965494030180786207976908235896012613129447132444100 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/171.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"172.edn_alert.50464149787080059539820912851963256878509465772103471651427721182257435982168","seed":50464149787080059539820912851963256878509465772103471651427721182257435982168,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/172.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/172.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=343226712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.343226712' seed=50464149787080059539820912851963256878509465772103471651427721182257435982168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50464149787080059539820912851963256878509465772103471651427721182257435982168 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/172.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"173.edn_alert.10222541641864018083055506071566454933116947857374807464168119471077133001406","seed":10222541641864018083055506071566454933116947857374807464168119471077133001406,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/173.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/173.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3692176062 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3692176062' seed=10222541641864018083055506071566454933116947857374807464168119471077133001406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10222541641864018083055506071566454933116947857374807464168119471077133001406 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/173.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"174.edn_alert.46107806390556232872589248865749930637174317861808027608521118004850859819661","seed":46107806390556232872589248865749930637174317861808027608521118004850859819661,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/174.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/174.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1120518797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1120518797' seed=46107806390556232872589248865749930637174317861808027608521118004850859819661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46107806390556232872589248865749930637174317861808027608521118004850859819661 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/174.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"175.edn_alert.19382162493471494052245614014592495029657046423279501224458005688304525505741","seed":19382162493471494052245614014592495029657046423279501224458005688304525505741,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/175.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/175.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2357589197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2357589197' seed=19382162493471494052245614014592495029657046423279501224458005688304525505741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19382162493471494052245614014592495029657046423279501224458005688304525505741 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/175.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"176.edn_alert.79697444758141912033536344337461937794979160569490770014054791496813766942493","seed":79697444758141912033536344337461937794979160569490770014054791496813766942493,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/176.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/176.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2806423325 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2806423325' seed=79697444758141912033536344337461937794979160569490770014054791496813766942493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79697444758141912033536344337461937794979160569490770014054791496813766942493 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/176.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"177.edn_alert.26041683022921052510521512636896787561292202644588389699635022777664048760664","seed":26041683022921052510521512636896787561292202644588389699635022777664048760664,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/177.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/177.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3344729944 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3344729944' seed=26041683022921052510521512636896787561292202644588389699635022777664048760664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26041683022921052510521512636896787561292202644588389699635022777664048760664 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/177.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"178.edn_alert.3523338410821036709739790246205594450070162759049607905531545314038224443023","seed":3523338410821036709739790246205594450070162759049607905531545314038224443023,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/178.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/178.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725435023 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2725435023' seed=3523338410821036709739790246205594450070162759049607905531545314038224443023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3523338410821036709739790246205594450070162759049607905531545314038224443023 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/178.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"179.edn_alert.34039663236149846603324695586871286976427125263948578148353318530652630718380","seed":34039663236149846603324695586871286976427125263948578148353318530652630718380,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/179.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/179.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3347355564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3347355564' seed=34039663236149846603324695586871286976427125263948578148353318530652630718380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34039663236149846603324695586871286976427125263948578148353318530652630718380 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/179.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"180.edn_alert.99265109378912344636971593393528171929857262027854410072892823578564481499082","seed":99265109378912344636971593393528171929857262027854410072892823578564481499082,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/180.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/180.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2885402570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2885402570' seed=99265109378912344636971593393528171929857262027854410072892823578564481499082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99265109378912344636971593393528171929857262027854410072892823578564481499082 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/180.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"181.edn_alert.30722276256036308934684658447816154778544999929402745654544508030087098144257","seed":30722276256036308934684658447816154778544999929402745654544508030087098144257,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/181.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/181.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3069318657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3069318657' seed=30722276256036308934684658447816154778544999929402745654544508030087098144257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30722276256036308934684658447816154778544999929402745654544508030087098144257 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/181.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"182.edn_alert.82331408441207109687560829094972086932011295547028643890964295758420123807660","seed":82331408441207109687560829094972086932011295547028643890964295758420123807660,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/182.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/182.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=580874156 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.580874156' seed=82331408441207109687560829094972086932011295547028643890964295758420123807660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82331408441207109687560829094972086932011295547028643890964295758420123807660 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/182.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"183.edn_alert.27282105693694858919782244225456072794280871192971882199264426131989125376938","seed":27282105693694858919782244225456072794280871192971882199264426131989125376938,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/183.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/183.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2797579178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2797579178' seed=27282105693694858919782244225456072794280871192971882199264426131989125376938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27282105693694858919782244225456072794280871192971882199264426131989125376938 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/183.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"184.edn_alert.2205530149281931784017178602808121472890263434116001110690695919191694958893","seed":2205530149281931784017178602808121472890263434116001110690695919191694958893,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/184.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/184.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1789059373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1789059373' seed=2205530149281931784017178602808121472890263434116001110690695919191694958893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2205530149281931784017178602808121472890263434116001110690695919191694958893 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/184.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"185.edn_alert.99611486909565324355653151956147226220567640159210133566731907242258894307176","seed":99611486909565324355653151956147226220567640159210133566731907242258894307176,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/185.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/185.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4226432872 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4226432872' seed=99611486909565324355653151956147226220567640159210133566731907242258894307176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99611486909565324355653151956147226220567640159210133566731907242258894307176 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/185.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"186.edn_alert.19020133797274369716490342642795497806022227692810622186047816848959046146110","seed":19020133797274369716490342642795497806022227692810622186047816848959046146110,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/186.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/186.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2696140862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2696140862' seed=19020133797274369716490342642795497806022227692810622186047816848959046146110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19020133797274369716490342642795497806022227692810622186047816848959046146110 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/186.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"187.edn_alert.63845119848226135100694377211940019954371673973343988270683757056478085631102","seed":63845119848226135100694377211940019954371673973343988270683757056478085631102,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/187.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/187.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3955215486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3955215486' seed=63845119848226135100694377211940019954371673973343988270683757056478085631102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63845119848226135100694377211940019954371673973343988270683757056478085631102 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/187.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"188.edn_alert.42414696330607244605003377845943515102306362307483641972552129148433563381474","seed":42414696330607244605003377845943515102306362307483641972552129148433563381474,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/188.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/188.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3120033506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3120033506' seed=42414696330607244605003377845943515102306362307483641972552129148433563381474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42414696330607244605003377845943515102306362307483641972552129148433563381474 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/188.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"189.edn_alert.114169821955713686698327486580444192895675739712873425974183054448453584638616","seed":114169821955713686698327486580444192895675739712873425974183054448453584638616,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/189.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/189.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2629259928 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2629259928' seed=114169821955713686698327486580444192895675739712873425974183054448453584638616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114169821955713686698327486580444192895675739712873425974183054448453584638616 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/189.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"190.edn_alert.114731720873425824396612326090350600062178099082405937410838775491947549654382","seed":114731720873425824396612326090350600062178099082405937410838775491947549654382,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/190.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/190.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2591522158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2591522158' seed=114731720873425824396612326090350600062178099082405937410838775491947549654382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114731720873425824396612326090350600062178099082405937410838775491947549654382 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/190.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"191.edn_alert.42908361441193664995984292175734648344145731653883173818287111216885468821421","seed":42908361441193664995984292175734648344145731653883173818287111216885468821421,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/191.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/191.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1354823597 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1354823597' seed=42908361441193664995984292175734648344145731653883173818287111216885468821421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42908361441193664995984292175734648344145731653883173818287111216885468821421 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/191.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"192.edn_alert.25423977956737986163956860891418420560034489629447156018632424900523216590387","seed":25423977956737986163956860891418420560034489629447156018632424900523216590387,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/192.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/192.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2840843827 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2840843827' seed=25423977956737986163956860891418420560034489629447156018632424900523216590387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25423977956737986163956860891418420560034489629447156018632424900523216590387 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/192.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"193.edn_alert.115396423677389647267964220734831578412360743983794444326275710931607200818444","seed":115396423677389647267964220734831578412360743983794444326275710931607200818444,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/193.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/193.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2398709004 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2398709004' seed=115396423677389647267964220734831578412360743983794444326275710931607200818444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115396423677389647267964220734831578412360743983794444326275710931607200818444 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/193.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"194.edn_alert.44120340883426843347087595878348895158361304349813253103710036210784110488790","seed":44120340883426843347087595878348895158361304349813253103710036210784110488790,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/194.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/194.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=581545174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.581545174' seed=44120340883426843347087595878348895158361304349813253103710036210784110488790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44120340883426843347087595878348895158361304349813253103710036210784110488790 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/194.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"195.edn_alert.36643547581813112262948098571425853221598387294018358637618790665734377592155","seed":36643547581813112262948098571425853221598387294018358637618790665734377592155,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/195.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/195.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677246811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3677246811' seed=36643547581813112262948098571425853221598387294018358637618790665734377592155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36643547581813112262948098571425853221598387294018358637618790665734377592155 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/195.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"196.edn_alert.51548133689017134439153041855347431087107912104868351884202458487171916158887","seed":51548133689017134439153041855347431087107912104868351884202458487171916158887,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/196.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/196.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2357909415 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2357909415' seed=51548133689017134439153041855347431087107912104868351884202458487171916158887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51548133689017134439153041855347431087107912104868351884202458487171916158887 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/196.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"197.edn_alert.26564887319638625535202814045585570376933287669993968896070212894927130762334","seed":26564887319638625535202814045585570376933287669993968896070212894927130762334,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/197.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/197.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3480525918 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3480525918' seed=26564887319638625535202814045585570376933287669993968896070212894927130762334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26564887319638625535202814045585570376933287669993968896070212894927130762334 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/197.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"198.edn_alert.108722560464887005508772158126214538445603647844576023258445893031198129206006","seed":108722560464887005508772158126214538445603647844576023258445893031198129206006,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/198.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/198.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1994994422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1994994422' seed=108722560464887005508772158126214538445603647844576023258445893031198129206006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108722560464887005508772158126214538445603647844576023258445893031198129206006 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/198.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"edn_alert","qual_name":"199.edn_alert.9951101411248131967085182318830201478606599963037671674747830584449783591195","seed":9951101411248131967085182318830201478606599963037671674747830584449783591195,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/199.edn_alert/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/199.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3864817947 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3864817947' seed=9951101411248131967085182318830201478606599963037671674747830584449783591195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9951101411248131967085182318830201478606599963037671674747830584449783591195 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/199.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job returned a non-zero exit code: *":[{"name":"edn","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=urg cov_merge_opts='-lca -full64 -noreport +urg+lic+wait -merge_across_libs -show tests -flex_merge union -dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -dbname /nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_merge/merged.vdb'\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126\n"]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"edn","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":30,"total":688,"percent":4.3604651162790695}