{"block":{"name":"prim_lfsr","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/prim/dv/data/prim_lfsr_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"prim_lfsr_gal_test":{"max_time":0.9240193981677294,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"prim_lfsr_fib_smoke":{"max_time":0.8493927037343383,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"prim_lfsr_fib_test":{"max_time":0.8621360212564468,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"prim_lfsr_gal_smoke":{"max_time":1.5361144673079252,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":4,"percent":0.0}},"passed":0,"total":4,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"prim_lfsr_gal_test","qual_name":"0.prim_lfsr_gal_test.50441203155217391417965348684596618978779580551307030908335236501683024937891","seed":50441203155217391417965348684596618978779580551307030908335236501683024937891,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2530722723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2530722723' seed=50441203155217391417965348684596618978779580551307030908335236501683024937891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50441203155217391417965348684596618978779580551307030908335236501683024937891 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_lfsr_fib_smoke","qual_name":"0.prim_lfsr_fib_smoke.91003624428416665413202665153887631937593393900244584810233321220958332604439","seed":91003624428416665413202665153887631937593393900244584810233321220958332604439,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752991255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2752991255' seed=91003624428416665413202665153887631937593393900244584810233321220958332604439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91003624428416665413202665153887631937593393900244584810233321220958332604439 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_lfsr_fib_test","qual_name":"0.prim_lfsr_fib_test.2313760343944071282976823417207071379977432858347527514220852279044916647677","seed":2313760343944071282976823417207071379977432858347527514220852279044916647677,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623098109 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3623098109' seed=2313760343944071282976823417207071379977432858347527514220852279044916647677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2313760343944071282976823417207071379977432858347527514220852279044916647677 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_lfsr_gal_smoke","qual_name":"0.prim_lfsr_gal_smoke.52328450844965490062983855721819351653157860323355323168199369566078557542586","seed":52328450844965490062983855721819351653157860323355323168199369566078557542586,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3291535546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3291535546' seed=52328450844965490062983855721819351653157860323355323168199369566078557542586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52328450844965490062983855721819351653157860323355323168199369566078557542586 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"prim_lfsr","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"prim_lfsr","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":4,"percent":0.0}