{"block":{"name":"prim_present","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/prim/dv/data/prim_present_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"prim_present_test":{"max_time":0.8324560718610883,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/prim_present-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"prim_present_test","qual_name":"0.prim_present_test.44724331238313348461258715079347334657498787992135706498197524088593196030188","seed":44724331238313348461258715079347334657498787992135706498197524088593196030188,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_present-sim-vcs/0.prim_present_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_present-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_present-sim-vcs/0.prim_present_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3111950572 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_present-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3111950572' seed=44724331238313348461258715079347334657498787992135706498197524088593196030188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44724331238313348461258715079347334657498787992135706498197524088593196030188 --run-dir=/nightly/current_run/scratch/master/prim_present-sim-vcs/0.prim_present_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"prim_present","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_present-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"prim_present","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_present-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":1,"percent":0.0}