{"block":{"name":"prim_prince","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/prim/dv/data/prim_prince_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"prim_prince_test":{"max_time":0.8608049601316452,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"prim_prince_test","qual_name":"0.prim_prince_test.15231573386652458815026935024758295259148300701635250280211421879178873500755","seed":15231573386652458815026935024758295259148300701635250280211421879178873500755,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/0.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/0.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726627411 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.726627411' seed=15231573386652458815026935024758295259148300701635250280211421879178873500755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15231573386652458815026935024758295259148300701635250280211421879178873500755 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/0.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"1.prim_prince_test.50380697662767856027533923214490238581818850841484358314782899502387031586354","seed":50380697662767856027533923214490238581818850841484358314782899502387031586354,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/1.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/1.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660223538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.660223538' seed=50380697662767856027533923214490238581818850841484358314782899502387031586354 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50380697662767856027533923214490238581818850841484358314782899502387031586354 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/1.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"2.prim_prince_test.110370721900244997009513102730980952292444592636754242143346655255970128329470","seed":110370721900244997009513102730980952292444592636754242143346655255970128329470,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/2.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/2.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660680958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.1660680958' seed=110370721900244997009513102730980952292444592636754242143346655255970128329470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110370721900244997009513102730980952292444592636754242143346655255970128329470 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/2.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"3.prim_prince_test.11688395977842925585993731290036915644104325899270008191317371342710215326630","seed":11688395977842925585993731290036915644104325899270008191317371342710215326630,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/3.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/3.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344243110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.344243110' seed=11688395977842925585993731290036915644104325899270008191317371342710215326630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11688395977842925585993731290036915644104325899270008191317371342710215326630 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/3.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"4.prim_prince_test.13067945688635067429823472934429282157324161487061439802358873814959939782028","seed":13067945688635067429823472934429282157324161487061439802358873814959939782028,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/4.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/4.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=884606348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.884606348' seed=13067945688635067429823472934429282157324161487061439802358873814959939782028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13067945688635067429823472934429282157324161487061439802358873814959939782028 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/4.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"5.prim_prince_test.18973240702348216045206856287511966281238972550246183705375596790166210576478","seed":18973240702348216045206856287511966281238972550246183705375596790166210576478,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/5.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/5.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1468629086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.1468629086' seed=18973240702348216045206856287511966281238972550246183705375596790166210576478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18973240702348216045206856287511966281238972550246183705375596790166210576478 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/5.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"6.prim_prince_test.60710122857598354614907583293896474992062095638554831563585660587029643827661","seed":60710122857598354614907583293896474992062095638554831563585660587029643827661,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/6.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/6.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2575997389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.2575997389' seed=60710122857598354614907583293896474992062095638554831563585660587029643827661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60710122857598354614907583293896474992062095638554831563585660587029643827661 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/6.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"7.prim_prince_test.56751152764714501257060262555256070142893237900456291319745949242095787851144","seed":56751152764714501257060262555256070142893237900456291319745949242095787851144,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/7.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/7.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4088151432 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.4088151432' seed=56751152764714501257060262555256070142893237900456291319745949242095787851144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56751152764714501257060262555256070142893237900456291319745949242095787851144 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/7.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"8.prim_prince_test.14813737436380616593529222378562278714736494495173650058504419615758033098021","seed":14813737436380616593529222378562278714736494495173650058504419615758033098021,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/8.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/8.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1457001765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.1457001765' seed=14813737436380616593529222378562278714736494495173650058504419615758033098021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14813737436380616593529222378562278714736494495173650058504419615758033098021 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/8.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"prim_prince_test","qual_name":"9.prim_prince_test.110807401434252911965480529693303103633248323137282041389835383721471869914572","seed":110807401434252911965480529693303103633248323137282041389835383721471869914572,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/9.prim_prince_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/9.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617287116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.617287116' seed=110807401434252911965480529693303103633248323137282041389835383721471869914572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110807401434252911965480529693303103633248323137282041389835383721471869914572 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/9.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"prim_prince","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"prim_prince","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/prim_prince-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":10,"percent":0.0}