{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":1.550029925070703,"sim_time":0.0,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"rstmgr_cnsty_chk_test","qual_name":"0.rstmgr_cnsty_chk_test.87002220680016519304335402143387895658696161506133204157513199708473546591223","seed":87002220680016519304335402143387895658696161506133204157513199708473546591223,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/0.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/0.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3152366583 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.3152366583' seed=87002220680016519304335402143387895658696161506133204157513199708473546591223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87002220680016519304335402143387895658696161506133204157513199708473546591223 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/0.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"1.rstmgr_cnsty_chk_test.79768897443213699915630363715815873840454429665303207426703300471887926115651","seed":79768897443213699915630363715815873840454429665303207426703300471887926115651,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/1.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/1.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=967818563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.967818563' seed=79768897443213699915630363715815873840454429665303207426703300471887926115651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79768897443213699915630363715815873840454429665303207426703300471887926115651 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/1.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"2.rstmgr_cnsty_chk_test.101335400197665867040741941836387687771964893079953129895976509395859780886557","seed":101335400197665867040741941836387687771964893079953129895976509395859780886557,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/2.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/2.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4025180189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.4025180189' seed=101335400197665867040741941836387687771964893079953129895976509395859780886557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101335400197665867040741941836387687771964893079953129895976509395859780886557 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/2.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"3.rstmgr_cnsty_chk_test.3753312391865165641242356506054433350119034198177351782820853596736598963495","seed":3753312391865165641242356506054433350119034198177351782820853596736598963495,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/3.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/3.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054812967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.2054812967' seed=3753312391865165641242356506054433350119034198177351782820853596736598963495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3753312391865165641242356506054433350119034198177351782820853596736598963495 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/3.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"4.rstmgr_cnsty_chk_test.84041159977120686543046287376748603726721990230917522367116447611997612684343","seed":84041159977120686543046287376748603726721990230917522367116447611997612684343,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/4.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/4.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1436038199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.1436038199' seed=84041159977120686543046287376748603726721990230917522367116447611997612684343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84041159977120686543046287376748603726721990230917522367116447611997612684343 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/4.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"5.rstmgr_cnsty_chk_test.74936002926122468277230926711211923413049169661850128484152050197718238780335","seed":74936002926122468277230926711211923413049169661850128484152050197718238780335,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/5.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/5.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1711823791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1711823791' seed=74936002926122468277230926711211923413049169661850128484152050197718238780335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74936002926122468277230926711211923413049169661850128484152050197718238780335 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/5.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"6.rstmgr_cnsty_chk_test.41776916182301547705603121819239339946654591150472431269244301316264428187748","seed":41776916182301547705603121819239339946654591150472431269244301316264428187748,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/6.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/6.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2461675620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.2461675620' seed=41776916182301547705603121819239339946654591150472431269244301316264428187748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41776916182301547705603121819239339946654591150472431269244301316264428187748 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/6.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"7.rstmgr_cnsty_chk_test.84163447747501071049898437293146555330039621736150993847450606802057447485052","seed":84163447747501071049898437293146555330039621736150993847450606802057447485052,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/7.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/7.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3712626300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.3712626300' seed=84163447747501071049898437293146555330039621736150993847450606802057447485052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84163447747501071049898437293146555330039621736150993847450606802057447485052 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/7.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"8.rstmgr_cnsty_chk_test.34638726101820448481815057572208690065683552391647072471993245700931070627599","seed":34638726101820448481815057572208690065683552391647072471993245700931070627599,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/8.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/8.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817270543 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.817270543' seed=34638726101820448481815057572208690065683552391647072471993245700931070627599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34638726101820448481815057572208690065683552391647072471993245700931070627599 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/8.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"9.rstmgr_cnsty_chk_test.12971040274996305698157034106152408486265952422583168175517181957177680829105","seed":12971040274996305698157034106152408486265952422583168175517181957177680829105,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2287180465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.2287180465' seed=12971040274996305698157034106152408486265952422583168175517181957177680829105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12971040274996305698157034106152408486265952422583168175517181957177680829105 --run-dir=/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"rstmgr_cnsty_chk","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"rstmgr_cnsty_chk","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":10,"percent":0.0}