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tb +SVSEED=4098199966 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_tap_fsm.4098199966 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_tap_fsm.4098199966 -covoverwrite' seed=43678163745004093937860088453128804004583517799496913267019863224516946006430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43678163745004093937860088453128804004583517799496913267019863224516946006430 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_tap_fsm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_hw_reset","qual_name":"0.rv_dm_jtag_dtm_csr_hw_reset.2935496760055761753637371022000775689509807058641931492524166111729253845466","seed":2935496760055761753637371022000775689509807058641931492524166111729253845466,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1046710746 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1046710746 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_hw_reset.1046710746 -covoverwrite' seed=2935496760055761753637371022000775689509807058641931492524166111729253845466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2935496760055761753637371022000775689509807058641931492524166111729253845466 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"0.rv_dm_jtag_dtm_csr_rw.13562403687229824451634777228402506612085312066842728978513066640658147425301","seed":13562403687229824451634777228402506612085312066842728978513066640658147425301,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2870852629 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2870852629 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_rw.2870852629 -covoverwrite' seed=13562403687229824451634777228402506612085312066842728978513066640658147425301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13562403687229824451634777228402506612085312066842728978513066640658147425301 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_bit_bash","qual_name":"0.rv_dm_jtag_dtm_csr_bit_bash.100172231198237987126315632782480719966406223745334962800634661805917611535394","seed":100172231198237987126315632782480719966406223745334962800634661805917611535394,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4179930146 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4179930146 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_bit_bash.4179930146 -covoverwrite' seed=100172231198237987126315632782480719966406223745334962800634661805917611535394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100172231198237987126315632782480719966406223745334962800634661805917611535394 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_aliasing","qual_name":"0.rv_dm_jtag_dtm_csr_aliasing.109408384305177799996859289447860758368956743872733230494792634603807631372867","seed":109408384305177799996859289447860758368956743872733230494792634603807631372867,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1662677571 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1662677571 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_aliasing.1662677571 -covoverwrite' seed=109408384305177799996859289447860758368956743872733230494792634603807631372867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109408384305177799996859289447860758368956743872733230494792634603807631372867 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_hw_reset","qual_name":"0.rv_dm_jtag_dmi_csr_hw_reset.14818129070322768956370203155526171752204489069220681541074618650998461842783","seed":14818129070322768956370203155526171752204489069220681541074618650998461842783,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4014622047 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4014622047 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_hw_reset.4014622047 -covoverwrite' seed=14818129070322768956370203155526171752204489069220681541074618650998461842783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14818129070322768956370203155526171752204489069220681541074618650998461842783 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"0.rv_dm_jtag_dmi_csr_rw.23433163186225842731198646653550653547973863446638869651945219780308203955076","seed":23433163186225842731198646653550653547973863446638869651945219780308203955076,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3710083972 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3710083972 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_rw.3710083972 -covoverwrite' seed=23433163186225842731198646653550653547973863446638869651945219780308203955076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23433163186225842731198646653550653547973863446638869651945219780308203955076 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"0.rv_dm_jtag_dmi_csr_bit_bash.55977877042368459914077739396979460269243962620118140384600414793761870910371","seed":55977877042368459914077739396979460269243962620118140384600414793761870910371,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3451720611 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3451720611 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_bit_bash.3451720611 -covoverwrite' seed=55977877042368459914077739396979460269243962620118140384600414793761870910371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55977877042368459914077739396979460269243962620118140384600414793761870910371 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_aliasing","qual_name":"0.rv_dm_jtag_dmi_csr_aliasing.76835480321072788057825069683113626811391098483094521139535719740281114764768","seed":76835480321072788057825069683113626811391098483094521139535719740281114764768,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=910075360 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.910075360 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_aliasing.910075360 -covoverwrite' seed=76835480321072788057825069683113626811391098483094521139535719740281114764768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76835480321072788057825069683113626811391098483094521139535719740281114764768 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"0.rv_dm_sba_tl_access.110040478614476365939391859636701374092700037196362671853120156789189530088185","seed":110040478614476365939391859636701374092700037196362671853120156789189530088185,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=999289593 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sba_tl_access.999289593 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sba_tl_access.999289593 -covoverwrite' seed=110040478614476365939391859636701374092700037196362671853120156789189530088185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110040478614476365939391859636701374092700037196362671853120156789189530088185 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"0.rv_dm_delayed_resp_sba_tl_access.2162125529611344131716661238163460641595335208721419524248588892044488579524","seed":2162125529611344131716661238163460641595335208721419524248588892044488579524,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2251004356 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2251004356 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_delayed_resp_sba_tl_access.2251004356 -covoverwrite' seed=2162125529611344131716661238163460641595335208721419524248588892044488579524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2162125529611344131716661238163460641595335208721419524248588892044488579524 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"0.rv_dm_bad_sba_tl_access.25128622909085098625444480889523950281418639233075032999434942834628990451388","seed":25128622909085098625444480889523950281418639233075032999434942834628990451388,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1758576316 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_bad_sba_tl_access.1758576316 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_bad_sba_tl_access.1758576316 -covoverwrite' seed=25128622909085098625444480889523950281418639233075032999434942834628990451388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25128622909085098625444480889523950281418639233075032999434942834628990451388 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"0.rv_dm_autoincr_sba_tl_access.108851442235874526930625924238117963119546305134562909091198043823635044700740","seed":108851442235874526930625924238117963119546305134562909091198043823635044700740,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1054020164 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_autoincr_sba_tl_access.1054020164 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_autoincr_sba_tl_access.1054020164 -covoverwrite' seed=108851442235874526930625924238117963119546305134562909091198043823635044700740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108851442235874526930625924238117963119546305134562909091198043823635044700740 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"0.rv_dm_tap_fsm_rand_reset.5600314857910583076481030619359718525803378395940022713705842482865216765855","seed":5600314857910583076481030619359718525803378395940022713705842482865216765855,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1117601695 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1117601695 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_tap_fsm_rand_reset.1117601695 -covoverwrite' seed=5600314857910583076481030619359718525803378395940022713705842482865216765855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5600314857910583076481030619359718525803378395940022713705842482865216765855 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_busy","qual_name":"0.rv_dm_cmderr_busy.28938314962285900743120911343588127258334959195829388090266332995120796828569","seed":28938314962285900743120911343588127258334959195829388090266332995120796828569,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_busy/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_busy/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2368766873 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_busy.2368766873 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_busy.2368766873 -covoverwrite' seed=28938314962285900743120911343588127258334959195829388090266332995120796828569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28938314962285900743120911343588127258334959195829388090266332995120796828569 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_busy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_busy_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_not_supported","qual_name":"0.rv_dm_cmderr_not_supported.62145028535011319006378507087108017503457541331682053176745701104428352410601","seed":62145028535011319006378507087108017503457541331682053176745701104428352410601,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_not_supported/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_not_supported/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2808746985 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_not_supported.2808746985 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_not_supported.2808746985 -covoverwrite' seed=62145028535011319006378507087108017503457541331682053176745701104428352410601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62145028535011319006378507087108017503457541331682053176745701104428352410601 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_not_supported/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_not_supported_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_exception","qual_name":"0.rv_dm_cmderr_exception.50446413704309246918716582396601784726923152186812173942030279060983704737234","seed":50446413704309246918716582396601784726923152186812173942030279060983704737234,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_exception/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_exception/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1876710866 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_exception.1876710866 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_exception.1876710866 -covoverwrite' seed=50446413704309246918716582396601784726923152186812173942030279060983704737234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50446413704309246918716582396601784726923152186812173942030279060983704737234 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_exception/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_exception_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_mem_tl_access_halted","qual_name":"0.rv_dm_mem_tl_access_halted.53268811777129531051625354316760781905991938730464846659710902012130611600362","seed":53268811777129531051625354316760781905991938730464846659710902012130611600362,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_halted/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_halted/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1466604522 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_mem_tl_access_halted.1466604522 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_mem_tl_access_halted.1466604522 -covoverwrite' seed=53268811777129531051625354316760781905991938730464846659710902012130611600362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53268811777129531051625354316760781905991938730464846659710902012130611600362 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_halted/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_mem_tl_access_halted_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_mem_tl_access_resuming","qual_name":"0.rv_dm_mem_tl_access_resuming.80604120596213122576364148641965496702145056829225913464028180869404630325745","seed":80604120596213122576364148641965496702145056829225913464028180869404630325745,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_resuming/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=262806001 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_mem_tl_access_resuming.262806001 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_mem_tl_access_resuming.262806001 -covoverwrite' seed=80604120596213122576364148641965496702145056829225913464028180869404630325745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80604120596213122576364148641965496702145056829225913464028180869404630325745 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_resuming/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_mem_tl_access_resuming_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_hart_unavail","qual_name":"0.rv_dm_hart_unavail.2393893441059039628241062090848182033344017093909608191038620001222965278369","seed":2393893441059039628241062090848182033344017093909608191038620001222965278369,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hart_unavail/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hart_unavail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=694105761 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_hart_unavail.694105761 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_hart_unavail.694105761 -covoverwrite' seed=2393893441059039628241062090848182033344017093909608191038620001222965278369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2393893441059039628241062090848182033344017093909608191038620001222965278369 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hart_unavail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hart_unavail_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_halt_resume","qual_name":"0.rv_dm_cmderr_halt_resume.4356480580597368573666644760857209111898272452472741914787146893117772043043","seed":4356480580597368573666644760857209111898272452472741914787146893117772043043,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_halt_resume/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_halt_resume/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1567396643 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_halt_resume.1567396643 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_halt_resume.1567396643 -covoverwrite' seed=4356480580597368573666644760857209111898272452472741914787146893117772043043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4356480580597368573666644760857209111898272452472741914787146893117772043043 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_halt_resume/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_halt_resume_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_dataaddr_rw_access","qual_name":"0.rv_dm_dataaddr_rw_access.65320972746811724052751726634928940015096095462396707607747307483116147997154","seed":65320972746811724052751726634928940015096095462396707607747307483116147997154,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dataaddr_rw_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dataaddr_rw_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=697989602 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_dataaddr_rw_access.697989602 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_dataaddr_rw_access.697989602 -covoverwrite' seed=65320972746811724052751726634928940015096095462396707607747307483116147997154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65320972746811724052751726634928940015096095462396707607747307483116147997154 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dataaddr_rw_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_dataaddr_rw_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"0.rv_dm_halt_resume_whereto.95838196194224806589520242608833328592493777841036884285000094415957876988994","seed":95838196194224806589520242608833328592493777841036884285000094415957876988994,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3934444610 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_halt_resume_whereto.3934444610 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_halt_resume_whereto.3934444610 -covoverwrite' seed=95838196194224806589520242608833328592493777841036884285000094415957876988994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95838196194224806589520242608833328592493777841036884285000094415957876988994 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_debug_disabled","qual_name":"0.rv_dm_sba_debug_disabled.18071373785554851175194026601718984634473290365006851737192452589554957531280","seed":18071373785554851175194026601718984634473290365006851737192452589554957531280,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_debug_disabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3169564816 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sba_debug_disabled.3169564816 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sba_debug_disabled.3169564816 -covoverwrite' seed=18071373785554851175194026601718984634473290365006851737192452589554957531280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18071373785554851175194026601718984634473290365006851737192452589554957531280 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_debug_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_ndmreset_req","qual_name":"0.rv_dm_ndmreset_req.44887875625970874806801668804026660786766003379561358144877367412505419080276","seed":44887875625970874806801668804026660786766003379561358144877367412505419080276,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_ndmreset_req/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_ndmreset_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=421421652 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_ndmreset_req.421421652 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_ndmreset_req.421421652 -covoverwrite' seed=44887875625970874806801668804026660786766003379561358144877367412505419080276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44887875625970874806801668804026660786766003379561358144877367412505419080276 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_ndmreset_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_ndmreset_req_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_idle_hint","qual_name":"0.rv_dm_jtag_dtm_idle_hint.87997714428859155603969929938937249160257396694324245892972938342505017023996","seed":87997714428859155603969929938937249160257396694324245892972938342505017023996,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_idle_hint/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_idle_hint/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3814759932 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3814759932 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dtm_idle_hint.3814759932 -covoverwrite' seed=87997714428859155603969929938937249160257396694324245892972938342505017023996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87997714428859155603969929938937249160257396694324245892972938342505017023996 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_idle_hint/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_idle_hint_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_dm_inactive","qual_name":"0.rv_dm_jtag_dmi_dm_inactive.7867286515717415157757760357046252018460314343937047267755361534065419201186","seed":7867286515717415157757760357046252018460314343937047267755361534065419201186,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_dm_inactive/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_dm_inactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2068818594 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2068818594 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dmi_dm_inactive.2068818594 -covoverwrite' seed=7867286515717415157757760357046252018460314343937047267755361534065419201186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7867286515717415157757760357046252018460314343937047267755361534065419201186 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_dm_inactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_dm_inactive_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"0.rv_dm_jtag_dmi_debug_disabled.14396016713429673900620029901041477974103046535535255791068527891466359203902","seed":14396016713429673900620029901041477974103046535535255791068527891466359203902,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=842852414 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.842852414 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dmi_debug_disabled.842852414 -covoverwrite' seed=14396016713429673900620029901041477974103046535535255791068527891466359203902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14396016713429673900620029901041477974103046535535255791068527891466359203902 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_debug_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_hard_reset","qual_name":"0.rv_dm_jtag_dtm_hard_reset.806257941022536882854238099720756736531968919961248136524618959550835704129","seed":806257941022536882854238099720756736531968919961248136524618959550835704129,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_hard_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_hard_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=597016897 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dtm_hard_reset.597016897 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dtm_hard_reset.597016897 -covoverwrite' seed=806257941022536882854238099720756736531968919961248136524618959550835704129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=806257941022536882854238099720756736531968919961248136524618959550835704129 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_hard_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_hard_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_abstractcmd_status","qual_name":"0.rv_dm_abstractcmd_status.9219808754384739610028068044057717244736521581635688571667559387593989482414","seed":9219808754384739610028068044057717244736521581635688571667559387593989482414,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_abstractcmd_status/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_abstractcmd_status/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2817320878 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_abstractcmd_status.2817320878 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_abstractcmd_status.2817320878 -covoverwrite' seed=9219808754384739610028068044057717244736521581635688571667559387593989482414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9219808754384739610028068044057717244736521581635688571667559387593989482414 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_abstractcmd_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_abstractcmd_status_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.43634308883098042133545061399584099273153177221978087130688496377486253460147","seed":43634308883098042133545061399584099273153177221978087130688496377486253460147,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3483601587 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_rom_read_access.3483601587 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_rom_read_access.3483601587 -covoverwrite' seed=43634308883098042133545061399584099273153177221978087130688496377486253460147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43634308883098042133545061399584099273153177221978087130688496377486253460147 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_rom_read_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_progbuf_read_write_execute","qual_name":"0.rv_dm_progbuf_read_write_execute.69326484050364525360845091791100743144692370513580405680577417690559066007985","seed":69326484050364525360845091791100743144692370513580405680577417690559066007985,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_progbuf_read_write_execute/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_progbuf_read_write_execute/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3985500593 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_progbuf_read_write_execute.3985500593 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_progbuf_read_write_execute.3985500593 -covoverwrite' seed=69326484050364525360845091791100743144692370513580405680577417690559066007985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69326484050364525360845091791100743144692370513580405680577417690559066007985 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_progbuf_read_write_execute/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_progbuf_read_write_execute_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_debug_disabled","qual_name":"0.rv_dm_debug_disabled.62347550787187915089632325250156274900383476436804007648420894448572362735786","seed":62347550787187915089632325250156274900383476436804007648420894448572362735786,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4254679210 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_debug_disabled.4254679210 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_debug_disabled.4254679210 -covoverwrite' seed=62347550787187915089632325250156274900383476436804007648420894448572362735786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62347550787187915089632325250156274900383476436804007648420894448572362735786 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_debug_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_dmi_failed_op","qual_name":"0.rv_dm_dmi_failed_op.86443000477291975173120240974395470440143090338561170855721772500239516121185","seed":86443000477291975173120240974395470440143090338561170855721772500239516121185,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dmi_failed_op/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dmi_failed_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3360110689 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_dmi_failed_op.3360110689 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_dmi_failed_op.3360110689 -covoverwrite' seed=86443000477291975173120240974395470440143090338561170855721772500239516121185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86443000477291975173120240974395470440143090338561170855721772500239516121185 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dmi_failed_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_dmi_failed_op_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_hartsel_warl","qual_name":"0.rv_dm_hartsel_warl.67514027591896222294610745421545324311686648607997090805940086532872564081282","seed":67514027591896222294610745421545324311686648607997090805940086532872564081282,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hartsel_warl/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hartsel_warl/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4242768514 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_hartsel_warl.4242768514 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_hartsel_warl.4242768514 -covoverwrite' seed=67514027591896222294610745421545324311686648607997090805940086532872564081282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67514027591896222294610745421545324311686648607997090805940086532872564081282 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hartsel_warl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hartsel_warl_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"0.rv_dm_buffered_enable.106384818791000223639253356937489688559581112749641358242856137276573383344487","seed":106384818791000223639253356937489688559581112749641358242856137276573383344487,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1746878823 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_buffered_enable.1746878823 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_buffered_enable.1746878823 -covoverwrite' seed=106384818791000223639253356937489688559581112749641358242856137276573383344487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106384818791000223639253356937489688559581112749641358242856137276573383344487 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sparse_lc_gate_fsm","qual_name":"0.rv_dm_sparse_lc_gate_fsm.48510933441186654772182484276024770834690245923847971775708848488487010732260","seed":48510933441186654772182484276024770834690245923847971775708848488487010732260,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sparse_lc_gate_fsm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sparse_lc_gate_fsm/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2050525412 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sparse_lc_gate_fsm.2050525412 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sparse_lc_gate_fsm.2050525412 -covoverwrite' seed=48510933441186654772182484276024770834690245923847971775708848488487010732260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48510933441186654772182484276024770834690245923847971775708848488487010732260 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sparse_lc_gate_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sparse_lc_gate_fsm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.37709107356435934054826716519963913697948167741955077441116071220093506584894","seed":37709107356435934054826716519963913697948167741955077441116071220093506584894,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3057942846 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_scanmode.3057942846 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_scanmode.3057942846 -covoverwrite' seed=37709107356435934054826716519963913697948167741955077441116071220093506584894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37709107356435934054826716519963913697948167741955077441116071220093506584894 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_scanmode_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.33034739383469910292305594915269452924874985820366144424243403970972451171251","seed":33034739383469910292305594915269452924874985820366144424243403970972451171251,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1701931955 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_stress_all_with_rand_reset.1701931955 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_stress_all_with_rand_reset.1701931955 -covoverwrite' seed=33034739383469910292305594915269452924874985820366144424243403970972451171251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33034739383469910292305594915269452924874985820366144424243403970972451171251 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sec_cm","qual_name":"0.rv_dm_sec_cm.94279092504261889453831579200405129794835378927585834745924566450003673110631","seed":94279092504261889453831579200405129794835378927585834745924566450003673110631,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1787058279 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sec_cm.1787058279 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sec_cm.1787058279 -covoverwrite' seed=94279092504261889453831579200405129794835378927585834745924566450003673110631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94279092504261889453831579200405129794835378927585834745924566450003673110631 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"0.rv_dm_tl_errors.47763842881623317448360301418361976056198877363445201597530411930926872101403","seed":47763842881623317448360301418361976056198877363445201597530411930926872101403,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=22905371 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_tl_errors.22905371 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_tl_errors.22905371 -covoverwrite' seed=47763842881623317448360301418361976056198877363445201597530411930926872101403 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47763842881623317448360301418361976056198877363445201597530411930926872101403 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"0.rv_dm_tl_intg_err.71989083355048923957800432709138192912416524460921448335760791279841789598491","seed":71989083355048923957800432709138192912416524460921448335760791279841789598491,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2349587227 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2349587227 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_tl_intg_err.2349587227 -covoverwrite' seed=71989083355048923957800432709138192912416524460921448335760791279841789598491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71989083355048923957800432709138192912416524460921448335760791279841789598491 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"0.rv_dm_alert_test.83251584736200377150923422072709057508098334564107755751707888409770700453821","seed":83251584736200377150923422072709057508098334564107755751707888409770700453821,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3911333821 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_alert_test.3911333821 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_alert_test.3911333821 -covoverwrite' seed=83251584736200377150923422072709057508098334564107755751707888409770700453821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83251584736200377150923422072709057508098334564107755751707888409770700453821 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_mem_walk","qual_name":"0.rv_dm_mem_walk.114129519036273848465084095316378961486348555569568476188643275479309074018379","seed":114129519036273848465084095316378961486348555569568476188643275479309074018379,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_walk/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=570404939 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_mem_walk.570404939 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_mem_walk.570404939 -covoverwrite' seed=114129519036273848465084095316378961486348555569568476188643275479309074018379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114129519036273848465084095316378961486348555569568476188643275479309074018379 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_mem_partial_access","qual_name":"0.rv_dm_mem_partial_access.8809190802839520613254324676605863498034578036754981941322950563985640434057","seed":8809190802839520613254324676605863498034578036754981941322950563985640434057,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_partial_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3209210249 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3209210249 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_mem_partial_access.3209210249 -covoverwrite' seed=8809190802839520613254324676605863498034578036754981941322950563985640434057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8809190802839520613254324676605863498034578036754981941322950563985640434057 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_hw_reset","qual_name":"0.rv_dm_csr_hw_reset.115220032646427783872002607767117269136440559217018917047386595742270586105998","seed":115220032646427783872002607767117269136440559217018917047386595742270586105998,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3642765454 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3642765454 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_csr_hw_reset.3642765454 -covoverwrite' seed=115220032646427783872002607767117269136440559217018917047386595742270586105998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115220032646427783872002607767117269136440559217018917047386595742270586105998 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_rw","qual_name":"0.rv_dm_csr_rw.110852856229346660482462572799403021331671525747902604536292590904664815814387","seed":110852856229346660482462572799403021331671525747902604536292590904664815814387,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2340931315 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_csr_rw.2340931315 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_csr_rw.2340931315 -covoverwrite' seed=110852856229346660482462572799403021331671525747902604536292590904664815814387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110852856229346660482462572799403021331671525747902604536292590904664815814387 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_bit_bash","qual_name":"0.rv_dm_csr_bit_bash.51639493845282246744323745651189777958745500827701283506546621397728783774507","seed":51639493845282246744323745651189777958745500827701283506546621397728783774507,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=921449259 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.921449259 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_csr_bit_bash.921449259 -covoverwrite' seed=51639493845282246744323745651189777958745500827701283506546621397728783774507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51639493845282246744323745651189777958745500827701283506546621397728783774507 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_same_csr_outstanding","qual_name":"0.rv_dm_same_csr_outstanding.54150962869945662900765839474499895714584520725337735331906139004343308437940","seed":54150962869945662900765839474499895714584520725337735331906139004343308437940,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3773483444 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3773483444 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_same_csr_outstanding.3773483444 -covoverwrite' seed=54150962869945662900765839474499895714584520725337735331906139004343308437940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54150962869945662900765839474499895714584520725337735331906139004343308437940 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"0.rv_dm_csr_mem_rw_with_rand_reset.89819361596643823341337137813188056980072462381770190705794451121788104891042","seed":89819361596643823341337137813188056980072462381770190705794451121788104891042,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=456546978 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.456546978 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_csr_mem_rw_with_rand_reset.456546978 -covoverwrite' seed=89819361596643823341337137813188056980072462381770190705794451121788104891042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89819361596643823341337137813188056980072462381770190705794451121788104891042 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_smoke","qual_name":"1.rv_dm_smoke.82222581162838306124158837161341536907931491687750162554048173508717910229767","seed":82222581162838306124158837161341536907931491687750162554048173508717910229767,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4084794119 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_smoke.4084794119 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_smoke.4084794119 -covoverwrite' seed=82222581162838306124158837161341536907931491687750162554048173508717910229767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82222581162838306124158837161341536907931491687750162554048173508717910229767 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_hw_reset","qual_name":"1.rv_dm_jtag_dtm_csr_hw_reset.1082068269594808472614791331429984728502370066595163957420364459228291294454","seed":1082068269594808472614791331429984728502370066595163957420364459228291294454,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3432670454 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3432670454 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dtm_csr_hw_reset.3432670454 -covoverwrite' seed=1082068269594808472614791331429984728502370066595163957420364459228291294454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1082068269594808472614791331429984728502370066595163957420364459228291294454 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"1.rv_dm_jtag_dtm_csr_rw.98602488759201436148350977246153747559596826995270375703839948862101536112480","seed":98602488759201436148350977246153747559596826995270375703839948862101536112480,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=268435296 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.268435296 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dtm_csr_rw.268435296 -covoverwrite' seed=98602488759201436148350977246153747559596826995270375703839948862101536112480 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98602488759201436148350977246153747559596826995270375703839948862101536112480 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_bit_bash","qual_name":"1.rv_dm_jtag_dtm_csr_bit_bash.20854915221375567216206481862888851712117652459500918586429045543443086488972","seed":20854915221375567216206481862888851712117652459500918586429045543443086488972,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2111354252 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2111354252 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dtm_csr_bit_bash.2111354252 -covoverwrite' seed=20854915221375567216206481862888851712117652459500918586429045543443086488972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20854915221375567216206481862888851712117652459500918586429045543443086488972 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_aliasing","qual_name":"1.rv_dm_jtag_dtm_csr_aliasing.20741402186472064973487585831575209052974296235429822274262357567257926221588","seed":20741402186472064973487585831575209052974296235429822274262357567257926221588,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3851992852 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3851992852 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dtm_csr_aliasing.3851992852 -covoverwrite' seed=20741402186472064973487585831575209052974296235429822274262357567257926221588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20741402186472064973487585831575209052974296235429822274262357567257926221588 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_hw_reset","qual_name":"1.rv_dm_jtag_dmi_csr_hw_reset.3092718466180608502638020878496308934774274987441989886658759494057903851690","seed":3092718466180608502638020878496308934774274987441989886658759494057903851690,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2083063978 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2083063978 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dmi_csr_hw_reset.2083063978 -covoverwrite' seed=3092718466180608502638020878496308934774274987441989886658759494057903851690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3092718466180608502638020878496308934774274987441989886658759494057903851690 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"1.rv_dm_jtag_dmi_csr_rw.20074714249083234382553417859263142354009314948121687172926814919697534032204","seed":20074714249083234382553417859263142354009314948121687172926814919697534032204,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2050234700 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2050234700 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dmi_csr_rw.2050234700 -covoverwrite' seed=20074714249083234382553417859263142354009314948121687172926814919697534032204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20074714249083234382553417859263142354009314948121687172926814919697534032204 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"1.rv_dm_jtag_dmi_csr_bit_bash.59416744613099193433235434969738509125160796466008625099940059602785778000533","seed":59416744613099193433235434969738509125160796466008625099940059602785778000533,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2247877269 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2247877269 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dmi_csr_bit_bash.2247877269 -covoverwrite' seed=59416744613099193433235434969738509125160796466008625099940059602785778000533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59416744613099193433235434969738509125160796466008625099940059602785778000533 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_aliasing","qual_name":"1.rv_dm_jtag_dmi_csr_aliasing.37718022988189649101440821483464444608091393260548559907392071529228392740347","seed":37718022988189649101440821483464444608091393260548559907392071529228392740347,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2322085371 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2322085371 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_jtag_dmi_csr_aliasing.2322085371 -covoverwrite' seed=37718022988189649101440821483464444608091393260548559907392071529228392740347 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37718022988189649101440821483464444608091393260548559907392071529228392740347 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"1.rv_dm_sba_tl_access.56473785937106328744131497793051813414042392197611033596041847800445369056867","seed":56473785937106328744131497793051813414042392197611033596041847800445369056867,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=925367907 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_sba_tl_access.925367907 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_sba_tl_access.925367907 -covoverwrite' seed=56473785937106328744131497793051813414042392197611033596041847800445369056867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56473785937106328744131497793051813414042392197611033596041847800445369056867 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"1.rv_dm_delayed_resp_sba_tl_access.28146034804805915334775540760782510263493864179465116120892443451758732265401","seed":28146034804805915334775540760782510263493864179465116120892443451758732265401,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=565331897 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.565331897 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_delayed_resp_sba_tl_access.565331897 -covoverwrite' seed=28146034804805915334775540760782510263493864179465116120892443451758732265401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28146034804805915334775540760782510263493864179465116120892443451758732265401 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"1.rv_dm_bad_sba_tl_access.69178647994159875615152403585927284257722653138737688769116415618826981541175","seed":69178647994159875615152403585927284257722653138737688769116415618826981541175,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2955085111 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_bad_sba_tl_access.2955085111 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_bad_sba_tl_access.2955085111 -covoverwrite' seed=69178647994159875615152403585927284257722653138737688769116415618826981541175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69178647994159875615152403585927284257722653138737688769116415618826981541175 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"1.rv_dm_autoincr_sba_tl_access.104012347231332387661950627077810514448808519447478758414609536054005224630108","seed":104012347231332387661950627077810514448808519447478758414609536054005224630108,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4084918108 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_autoincr_sba_tl_access.4084918108 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_autoincr_sba_tl_access.4084918108 -covoverwrite' seed=104012347231332387661950627077810514448808519447478758414609536054005224630108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104012347231332387661950627077810514448808519447478758414609536054005224630108 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"1.rv_dm_tap_fsm_rand_reset.63607630730623993519481641278987169999987088138522784292335400839410205211026","seed":63607630730623993519481641278987169999987088138522784292335400839410205211026,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2073966994 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2073966994 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_tap_fsm_rand_reset.2073966994 -covoverwrite' seed=63607630730623993519481641278987169999987088138522784292335400839410205211026 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63607630730623993519481641278987169999987088138522784292335400839410205211026 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_busy","qual_name":"1.rv_dm_cmderr_busy.9950330698654593178653043201587066540743241722274379773142342962189138504123","seed":9950330698654593178653043201587066540743241722274379773142342962189138504123,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_busy/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_busy/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2090183099 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_cmderr_busy.2090183099 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_cmderr_busy.2090183099 -covoverwrite' seed=9950330698654593178653043201587066540743241722274379773142342962189138504123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9950330698654593178653043201587066540743241722274379773142342962189138504123 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_busy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_busy_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_not_supported","qual_name":"1.rv_dm_cmderr_not_supported.7911552843323373961774049632625874113270231776336440015503450906230649434832","seed":7911552843323373961774049632625874113270231776336440015503450906230649434832,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_not_supported/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_not_supported/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=297448144 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_cmderr_not_supported.297448144 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_cmderr_not_supported.297448144 -covoverwrite' seed=7911552843323373961774049632625874113270231776336440015503450906230649434832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7911552843323373961774049632625874113270231776336440015503450906230649434832 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_not_supported/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_not_supported_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_exception","qual_name":"1.rv_dm_cmderr_exception.4696777026215092126523260116955913234377054863884905243533259676243994125016","seed":4696777026215092126523260116955913234377054863884905243533259676243994125016,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_exception/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_exception/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3858014936 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_cmderr_exception.3858014936 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_cmderr_exception.3858014936 -covoverwrite' seed=4696777026215092126523260116955913234377054863884905243533259676243994125016 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4696777026215092126523260116955913234377054863884905243533259676243994125016 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_exception/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_exception_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_mem_tl_access_halted","qual_name":"1.rv_dm_mem_tl_access_halted.21510823585626666872664500657521355770262818470496619866888777968330760625152","seed":21510823585626666872664500657521355770262818470496619866888777968330760625152,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_mem_tl_access_halted/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_mem_tl_access_halted/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=949853184 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_mem_tl_access_halted.949853184 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_mem_tl_access_halted.949853184 -covoverwrite' seed=21510823585626666872664500657521355770262818470496619866888777968330760625152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21510823585626666872664500657521355770262818470496619866888777968330760625152 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_mem_tl_access_halted/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_mem_tl_access_halted_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_mem_tl_access_resuming","qual_name":"1.rv_dm_mem_tl_access_resuming.41012492607463466595812299559461776992141521119290112548187832517524440469132","seed":41012492607463466595812299559461776992141521119290112548187832517524440469132,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_mem_tl_access_resuming/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3860582028 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_mem_tl_access_resuming.3860582028 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_mem_tl_access_resuming.3860582028 -covoverwrite' seed=41012492607463466595812299559461776992141521119290112548187832517524440469132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41012492607463466595812299559461776992141521119290112548187832517524440469132 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_mem_tl_access_resuming/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_mem_tl_access_resuming_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_hart_unavail","qual_name":"1.rv_dm_hart_unavail.2060456579194778297709140257956503117371087056193478837849435806578585257226","seed":2060456579194778297709140257956503117371087056193478837849435806578585257226,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_hart_unavail/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_hart_unavail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3172877578 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_hart_unavail.3172877578 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_hart_unavail.3172877578 -covoverwrite' seed=2060456579194778297709140257956503117371087056193478837849435806578585257226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2060456579194778297709140257956503117371087056193478837849435806578585257226 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_hart_unavail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hart_unavail_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_cmderr_halt_resume","qual_name":"1.rv_dm_cmderr_halt_resume.83396925849712322127871033081755545748560349980227726097995549184121787558376","seed":83396925849712322127871033081755545748560349980227726097995549184121787558376,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_halt_resume/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_halt_resume/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3518671336 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_cmderr_halt_resume.3518671336 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_cmderr_halt_resume.3518671336 -covoverwrite' seed=83396925849712322127871033081755545748560349980227726097995549184121787558376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83396925849712322127871033081755545748560349980227726097995549184121787558376 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_cmderr_halt_resume/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_halt_resume_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_dataaddr_rw_access","qual_name":"1.rv_dm_dataaddr_rw_access.20833381848601872731710272759478973119952128574734193485252812842562421483557","seed":20833381848601872731710272759478973119952128574734193485252812842562421483557,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_dataaddr_rw_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_dataaddr_rw_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2617468965 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_dataaddr_rw_access.2617468965 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_dataaddr_rw_access.2617468965 -covoverwrite' seed=20833381848601872731710272759478973119952128574734193485252812842562421483557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20833381848601872731710272759478973119952128574734193485252812842562421483557 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_dataaddr_rw_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_dataaddr_rw_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"1.rv_dm_halt_resume_whereto.81107025722944110175820953761621470514327781574276421942866309922933931141047","seed":81107025722944110175820953761621470514327781574276421942866309922933931141047,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=113141687 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_halt_resume_whereto.113141687 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_halt_resume_whereto.113141687 -covoverwrite' seed=81107025722944110175820953761621470514327781574276421942866309922933931141047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81107025722944110175820953761621470514327781574276421942866309922933931141047 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_debug_disabled","qual_name":"1.rv_dm_sba_debug_disabled.29877632180453048969433112547244798155572762063956432521281023918613569381629","seed":29877632180453048969433112547244798155572762063956432521281023918613569381629,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sba_debug_disabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sba_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3518407933 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_sba_debug_disabled.3518407933 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_sba_debug_disabled.3518407933 -covoverwrite' seed=29877632180453048969433112547244798155572762063956432521281023918613569381629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29877632180453048969433112547244798155572762063956432521281023918613569381629 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sba_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_debug_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_ndmreset_req","qual_name":"1.rv_dm_ndmreset_req.112801553974700206539188820783216503042335272499079197389927448204843941202633","seed":112801553974700206539188820783216503042335272499079197389927448204843941202633,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_ndmreset_req/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_ndmreset_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4143286985 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_ndmreset_req.4143286985 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_ndmreset_req.4143286985 -covoverwrite' seed=112801553974700206539188820783216503042335272499079197389927448204843941202633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112801553974700206539188820783216503042335272499079197389927448204843941202633 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_ndmreset_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_ndmreset_req_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_idle_hint","qual_name":"1.rv_dm_jtag_dtm_idle_hint.82978746338966339175625399343130882591776821558331369783071645113380685194882","seed":82978746338966339175625399343130882591776821558331369783071645113380685194882,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_idle_hint/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_idle_hint/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2293474946 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2293474946 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_jtag_dtm_idle_hint.2293474946 -covoverwrite' seed=82978746338966339175625399343130882591776821558331369783071645113380685194882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82978746338966339175625399343130882591776821558331369783071645113380685194882 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_idle_hint/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_idle_hint_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_dm_inactive","qual_name":"1.rv_dm_jtag_dmi_dm_inactive.113030991688156798537733256525433955180066464467895757728838682447605294822510","seed":113030991688156798537733256525433955180066464467895757728838682447605294822510,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_dm_inactive/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_dm_inactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=683799662 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.683799662 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_jtag_dmi_dm_inactive.683799662 -covoverwrite' seed=113030991688156798537733256525433955180066464467895757728838682447605294822510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113030991688156798537733256525433955180066464467895757728838682447605294822510 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_dm_inactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_dm_inactive_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"1.rv_dm_jtag_dmi_debug_disabled.1764057866928769912957240770207504516209979241819260757245815441955591323907","seed":1764057866928769912957240770207504516209979241819260757245815441955591323907,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3754721539 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3754721539 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_jtag_dmi_debug_disabled.3754721539 -covoverwrite' seed=1764057866928769912957240770207504516209979241819260757245815441955591323907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1764057866928769912957240770207504516209979241819260757245815441955591323907 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dmi_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_debug_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_hard_reset","qual_name":"1.rv_dm_jtag_dtm_hard_reset.103293603897264678362038477664764942074234249227328869318077593616285547561715","seed":103293603897264678362038477664764942074234249227328869318077593616285547561715,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_hard_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_hard_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1103561459 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1103561459 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_jtag_dtm_hard_reset.1103561459 -covoverwrite' seed=103293603897264678362038477664764942074234249227328869318077593616285547561715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103293603897264678362038477664764942074234249227328869318077593616285547561715 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_hard_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_hard_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_abstractcmd_status","qual_name":"1.rv_dm_abstractcmd_status.13782764390361407936550831087096182689013556972951094452782674374000300254440","seed":13782764390361407936550831087096182689013556972951094452782674374000300254440,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_abstractcmd_status/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_abstractcmd_status/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3919570152 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_abstractcmd_status.3919570152 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_abstractcmd_status.3919570152 -covoverwrite' seed=13782764390361407936550831087096182689013556972951094452782674374000300254440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13782764390361407936550831087096182689013556972951094452782674374000300254440 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_abstractcmd_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_abstractcmd_status_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_rom_read_access","qual_name":"1.rv_dm_rom_read_access.2511922457458013834013466238354651786139050391314644496029180618061929205","seed":2511922457458013834013466238354651786139050391314644496029180618061929205,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_rom_read_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_rom_read_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3290979061 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_rom_read_access.3290979061 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_rom_read_access.3290979061 -covoverwrite' seed=2511922457458013834013466238354651786139050391314644496029180618061929205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2511922457458013834013466238354651786139050391314644496029180618061929205 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_rom_read_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_rom_read_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_progbuf_read_write_execute","qual_name":"1.rv_dm_progbuf_read_write_execute.72479501154122196891377892792799401409781790590063870952358196537771636426051","seed":72479501154122196891377892792799401409781790590063870952358196537771636426051,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_progbuf_read_write_execute/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_progbuf_read_write_execute/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2519598403 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_progbuf_read_write_execute.2519598403 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_progbuf_read_write_execute.2519598403 -covoverwrite' seed=72479501154122196891377892792799401409781790590063870952358196537771636426051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72479501154122196891377892792799401409781790590063870952358196537771636426051 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_progbuf_read_write_execute/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_progbuf_read_write_execute_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_debug_disabled","qual_name":"1.rv_dm_debug_disabled.76134566612271029270348968248378892956586751413041627454675754371190853329181","seed":76134566612271029270348968248378892956586751413041627454675754371190853329181,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_debug_disabled/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3540377885 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_debug_disabled.3540377885 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_debug_disabled.3540377885 -covoverwrite' seed=76134566612271029270348968248378892956586751413041627454675754371190853329181 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76134566612271029270348968248378892956586751413041627454675754371190853329181 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_debug_disabled_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_dmi_failed_op","qual_name":"1.rv_dm_dmi_failed_op.52083714466624265909623085322365752760841015703905542441153242628285533684562","seed":52083714466624265909623085322365752760841015703905542441153242628285533684562,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_dmi_failed_op/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_dmi_failed_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=907445074 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_dmi_failed_op.907445074 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_dmi_failed_op.907445074 -covoverwrite' seed=52083714466624265909623085322365752760841015703905542441153242628285533684562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52083714466624265909623085322365752760841015703905542441153242628285533684562 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_dmi_failed_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_dmi_failed_op_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"1.rv_dm_buffered_enable.24987815152891532858315072287720930876874922391907155731185993120574167517288","seed":24987815152891532858315072287720930876874922391907155731185993120574167517288,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1602685032 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_buffered_enable.1602685032 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_buffered_enable.1602685032 -covoverwrite' seed=24987815152891532858315072287720930876874922391907155731185993120574167517288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24987815152891532858315072287720930876874922391907155731185993120574167517288 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sparse_lc_gate_fsm","qual_name":"1.rv_dm_sparse_lc_gate_fsm.66353212723188594376389778500267604992126224907969118975977620490483310379560","seed":66353212723188594376389778500267604992126224907969118975977620490483310379560,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sparse_lc_gate_fsm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sparse_lc_gate_fsm/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1916650024 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1916650024 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_sparse_lc_gate_fsm.1916650024 -covoverwrite' seed=66353212723188594376389778500267604992126224907969118975977620490483310379560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66353212723188594376389778500267604992126224907969118975977620490483310379560 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sparse_lc_gate_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sparse_lc_gate_fsm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"1.rv_dm_stress_all_with_rand_reset.35555724819257723914544140637011454156627062428345842455193889621827970273949","seed":35555724819257723914544140637011454156627062428345842455193889621827970273949,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3814593181 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_stress_all_with_rand_reset.3814593181 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_stress_all_with_rand_reset.3814593181 -covoverwrite' seed=35555724819257723914544140637011454156627062428345842455193889621827970273949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35555724819257723914544140637011454156627062428345842455193889621827970273949 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sec_cm","qual_name":"1.rv_dm_sec_cm.37545891097480916958901872278653544731697964622101627621649961853258758297577","seed":37545891097480916958901872278653544731697964622101627621649961853258758297577,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=402331625 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_sec_cm.402331625 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_sec_cm.402331625 -covoverwrite' seed=37545891097480916958901872278653544731697964622101627621649961853258758297577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37545891097480916958901872278653544731697964622101627621649961853258758297577 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"1.rv_dm_tl_errors.61549042525199080306902910599468769785696715160286783726654676875521474879512","seed":61549042525199080306902910599468769785696715160286783726654676875521474879512,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4041400344 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_tl_errors.4041400344 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_tl_errors.4041400344 -covoverwrite' seed=61549042525199080306902910599468769785696715160286783726654676875521474879512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61549042525199080306902910599468769785696715160286783726654676875521474879512 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"1.rv_dm_tl_intg_err.84919545249679261180899930890201220170507639354712179095751902347506175582613","seed":84919545249679261180899930890201220170507639354712179095751902347506175582613,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2823430549 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2823430549 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_tl_intg_err.2823430549 -covoverwrite' seed=84919545249679261180899930890201220170507639354712179095751902347506175582613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84919545249679261180899930890201220170507639354712179095751902347506175582613 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"1.rv_dm_alert_test.104399634929801097371821637653465203746248336099557286467838505107428168785581","seed":104399634929801097371821637653465203746248336099557286467838505107428168785581,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=312565421 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/1.rv_dm_alert_test.312565421 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 1.rv_dm_alert_test.312565421 -covoverwrite' seed=104399634929801097371821637653465203746248336099557286467838505107428168785581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104399634929801097371821637653465203746248336099557286467838505107428168785581 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_rw","qual_name":"1.rv_dm_csr_rw.11622724934710668955221734386253681975720900410539649304589034067723913867512","seed":11622724934710668955221734386253681975720900410539649304589034067723913867512,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3057987832 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_csr_rw.3057987832 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_csr_rw.3057987832 -covoverwrite' seed=11622724934710668955221734386253681975720900410539649304589034067723913867512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11622724934710668955221734386253681975720900410539649304589034067723913867512 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_same_csr_outstanding","qual_name":"1.rv_dm_same_csr_outstanding.49005361903243845864776546878144831713194509442860893445871030982684676705050","seed":49005361903243845864776546878144831713194509442860893445871030982684676705050,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1756613402 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1756613402 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_same_csr_outstanding.1756613402 -covoverwrite' seed=49005361903243845864776546878144831713194509442860893445871030982684676705050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49005361903243845864776546878144831713194509442860893445871030982684676705050 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"1.rv_dm_csr_mem_rw_with_rand_reset.12675236962283453120016722027496858406677833536195393893847657660809423884626","seed":12675236962283453120016722027496858406677833536195393893847657660809423884626,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3647213906 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3647213906 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_dm_csr_mem_rw_with_rand_reset.3647213906 -covoverwrite' seed=12675236962283453120016722027496858406677833536195393893847657660809423884626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12675236962283453120016722027496858406677833536195393893847657660809423884626 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_hw_reset","qual_name":"2.rv_dm_jtag_dtm_csr_hw_reset.62262234445144442458688125113231535122370921384509666359776488603351116378319","seed":62262234445144442458688125113231535122370921384509666359776488603351116378319,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1994092751 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1994092751 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dtm_csr_hw_reset.1994092751 -covoverwrite' seed=62262234445144442458688125113231535122370921384509666359776488603351116378319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62262234445144442458688125113231535122370921384509666359776488603351116378319 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"2.rv_dm_jtag_dtm_csr_rw.53649694159875300527689571691934686170814279249415759746181886262027620927964","seed":53649694159875300527689571691934686170814279249415759746181886262027620927964,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=490162652 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.490162652 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dtm_csr_rw.490162652 -covoverwrite' seed=53649694159875300527689571691934686170814279249415759746181886262027620927964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53649694159875300527689571691934686170814279249415759746181886262027620927964 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_bit_bash","qual_name":"2.rv_dm_jtag_dtm_csr_bit_bash.103385777964739289989423217829276029305997142958215862084189187353666185805176","seed":103385777964739289989423217829276029305997142958215862084189187353666185805176,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3350412664 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3350412664 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dtm_csr_bit_bash.3350412664 -covoverwrite' seed=103385777964739289989423217829276029305997142958215862084189187353666185805176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103385777964739289989423217829276029305997142958215862084189187353666185805176 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_aliasing","qual_name":"2.rv_dm_jtag_dtm_csr_aliasing.1870084058408461176625024159986671477156953988489804454441759602547903966590","seed":1870084058408461176625024159986671477156953988489804454441759602547903966590,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=491793790 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.491793790 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dtm_csr_aliasing.491793790 -covoverwrite' seed=1870084058408461176625024159986671477156953988489804454441759602547903966590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1870084058408461176625024159986671477156953988489804454441759602547903966590 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dtm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_hw_reset","qual_name":"2.rv_dm_jtag_dmi_csr_hw_reset.11918538367404660214606211986140857975880679629645576285147915919500782321381","seed":11918538367404660214606211986140857975880679629645576285147915919500782321381,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3850878693 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3850878693 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dmi_csr_hw_reset.3850878693 -covoverwrite' seed=11918538367404660214606211986140857975880679629645576285147915919500782321381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11918538367404660214606211986140857975880679629645576285147915919500782321381 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"2.rv_dm_jtag_dmi_csr_rw.13134108934770431342135171353588117315182245608627628961357973719250494789437","seed":13134108934770431342135171353588117315182245608627628961357973719250494789437,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=633837373 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.633837373 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dmi_csr_rw.633837373 -covoverwrite' seed=13134108934770431342135171353588117315182245608627628961357973719250494789437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13134108934770431342135171353588117315182245608627628961357973719250494789437 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"2.rv_dm_jtag_dmi_csr_bit_bash.20635873818561831076372869000733118862878163841176521170620377207916478508130","seed":20635873818561831076372869000733118862878163841176521170620377207916478508130,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2711268450 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2711268450 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dmi_csr_bit_bash.2711268450 -covoverwrite' seed=20635873818561831076372869000733118862878163841176521170620377207916478508130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20635873818561831076372869000733118862878163841176521170620377207916478508130 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_aliasing","qual_name":"2.rv_dm_jtag_dmi_csr_aliasing.114760871920532804596143336000479241693370059088812561346351513378766471507787","seed":114760871920532804596143336000479241693370059088812561346351513378766471507787,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3122605899 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3122605899 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_jtag_dmi_csr_aliasing.3122605899 -covoverwrite' seed=114760871920532804596143336000479241693370059088812561346351513378766471507787 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114760871920532804596143336000479241693370059088812561346351513378766471507787 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_jtag_dmi_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"2.rv_dm_sba_tl_access.19372917843049020965856869190337556516164692050109533782294084933875407173088","seed":19372917843049020965856869190337556516164692050109533782294084933875407173088,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2812458464 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_sba_tl_access.2812458464 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_sba_tl_access.2812458464 -covoverwrite' seed=19372917843049020965856869190337556516164692050109533782294084933875407173088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19372917843049020965856869190337556516164692050109533782294084933875407173088 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"2.rv_dm_delayed_resp_sba_tl_access.108782202673333018739743492475021585725642722485949808528918149067909266414060","seed":108782202673333018739743492475021585725642722485949808528918149067909266414060,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=500439532 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.500439532 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_delayed_resp_sba_tl_access.500439532 -covoverwrite' seed=108782202673333018739743492475021585725642722485949808528918149067909266414060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108782202673333018739743492475021585725642722485949808528918149067909266414060 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"2.rv_dm_bad_sba_tl_access.101229173934463748683417323037184684179181409662867346564101510114846134286091","seed":101229173934463748683417323037184684179181409662867346564101510114846134286091,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1265678091 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_bad_sba_tl_access.1265678091 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_bad_sba_tl_access.1265678091 -covoverwrite' seed=101229173934463748683417323037184684179181409662867346564101510114846134286091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101229173934463748683417323037184684179181409662867346564101510114846134286091 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"2.rv_dm_autoincr_sba_tl_access.23574321442046064952503871480048788682868741219940553946666801825496585060142","seed":23574321442046064952503871480048788682868741219940553946666801825496585060142,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=104185646 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_autoincr_sba_tl_access.104185646 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_autoincr_sba_tl_access.104185646 -covoverwrite' seed=23574321442046064952503871480048788682868741219940553946666801825496585060142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23574321442046064952503871480048788682868741219940553946666801825496585060142 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"2.rv_dm_tap_fsm_rand_reset.52098509106890804820330259971076006442073314027951903509654505571505992160921","seed":52098509106890804820330259971076006442073314027951903509654505571505992160921,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3956332185 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3956332185 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_tap_fsm_rand_reset.3956332185 -covoverwrite' seed=52098509106890804820330259971076006442073314027951903509654505571505992160921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52098509106890804820330259971076006442073314027951903509654505571505992160921 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_hart_unavail","qual_name":"2.rv_dm_hart_unavail.70847216244533462263079046237075424267157691239624854692567285030775761259043","seed":70847216244533462263079046237075424267157691239624854692567285030775761259043,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_hart_unavail/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_hart_unavail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3628714531 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_hart_unavail.3628714531 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_hart_unavail.3628714531 -covoverwrite' seed=70847216244533462263079046237075424267157691239624854692567285030775761259043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70847216244533462263079046237075424267157691239624854692567285030775761259043 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_hart_unavail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hart_unavail_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"2.rv_dm_halt_resume_whereto.36239319882187409177239144480962992512874374098080376543952928364191451726361","seed":36239319882187409177239144480962992512874374098080376543952928364191451726361,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1726759449 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_halt_resume_whereto.1726759449 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_halt_resume_whereto.1726759449 -covoverwrite' seed=36239319882187409177239144480962992512874374098080376543952928364191451726361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36239319882187409177239144480962992512874374098080376543952928364191451726361 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"2.rv_dm_buffered_enable.6238490888835688084051039787256938807614631645799208994243829129531708573144","seed":6238490888835688084051039787256938807614631645799208994243829129531708573144,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4285695448 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_buffered_enable.4285695448 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_buffered_enable.4285695448 -covoverwrite' seed=6238490888835688084051039787256938807614631645799208994243829129531708573144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6238490888835688084051039787256938807614631645799208994243829129531708573144 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sparse_lc_gate_fsm","qual_name":"2.rv_dm_sparse_lc_gate_fsm.30123753948500939728914278237737072108890117590342593781526258276141912838935","seed":30123753948500939728914278237737072108890117590342593781526258276141912838935,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sparse_lc_gate_fsm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sparse_lc_gate_fsm/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3678688023 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3678688023 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_sparse_lc_gate_fsm.3678688023 -covoverwrite' seed=30123753948500939728914278237737072108890117590342593781526258276141912838935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30123753948500939728914278237737072108890117590342593781526258276141912838935 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sparse_lc_gate_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sparse_lc_gate_fsm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"2.rv_dm_stress_all_with_rand_reset.40192808714353374496480284219835098198516528718869012743759784680718566203736","seed":40192808714353374496480284219835098198516528718869012743759784680718566203736,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3289948504 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_stress_all_with_rand_reset.3289948504 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_stress_all_with_rand_reset.3289948504 -covoverwrite' seed=40192808714353374496480284219835098198516528718869012743759784680718566203736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40192808714353374496480284219835098198516528718869012743759784680718566203736 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sec_cm","qual_name":"2.rv_dm_sec_cm.89645192101070493283044508168728461021871292432108167284744345947065207434078","seed":89645192101070493283044508168728461021871292432108167284744345947065207434078,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=937896798 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_sec_cm.937896798 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_sec_cm.937896798 -covoverwrite' seed=89645192101070493283044508168728461021871292432108167284744345947065207434078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89645192101070493283044508168728461021871292432108167284744345947065207434078 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"2.rv_dm_tl_errors.6331104900054105625078479181628534501569593436293176857041686723086492489616","seed":6331104900054105625078479181628534501569593436293176857041686723086492489616,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2316687248 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_tl_errors.2316687248 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_tl_errors.2316687248 -covoverwrite' seed=6331104900054105625078479181628534501569593436293176857041686723086492489616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6331104900054105625078479181628534501569593436293176857041686723086492489616 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"2.rv_dm_tl_intg_err.56499557094320203879590874267526395929688162898665571735760506375818683477761","seed":56499557094320203879590874267526395929688162898665571735760506375818683477761,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=750382849 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_tl_intg_err.750382849 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_tl_intg_err.750382849 -covoverwrite' seed=56499557094320203879590874267526395929688162898665571735760506375818683477761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56499557094320203879590874267526395929688162898665571735760506375818683477761 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"2.rv_dm_alert_test.94790916497087326647959025219957185285505782689670835285233155754672701548960","seed":94790916497087326647959025219957185285505782689670835285233155754672701548960,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2006952352 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/2.rv_dm_alert_test.2006952352 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 2.rv_dm_alert_test.2006952352 -covoverwrite' seed=94790916497087326647959025219957185285505782689670835285233155754672701548960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94790916497087326647959025219957185285505782689670835285233155754672701548960 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_rw","qual_name":"2.rv_dm_csr_rw.57842052279387090698397190420278900750391399097574296242898162989442873513007","seed":57842052279387090698397190420278900750391399097574296242898162989442873513007,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=480597039 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_csr_rw.480597039 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_csr_rw.480597039 -covoverwrite' seed=57842052279387090698397190420278900750391399097574296242898162989442873513007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57842052279387090698397190420278900750391399097574296242898162989442873513007 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_same_csr_outstanding","qual_name":"2.rv_dm_same_csr_outstanding.53585236941569929758539527409672932128344770123953926898076653785382338170253","seed":53585236941569929758539527409672932128344770123953926898076653785382338170253,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3331067277 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3331067277 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_same_csr_outstanding.3331067277 -covoverwrite' seed=53585236941569929758539527409672932128344770123953926898076653785382338170253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53585236941569929758539527409672932128344770123953926898076653785382338170253 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"2.rv_dm_csr_mem_rw_with_rand_reset.66877975107323616143493391178796014810330272264188947885094282780553637861540","seed":66877975107323616143493391178796014810330272264188947885094282780553637861540,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1506875556 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1506875556 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_dm_csr_mem_rw_with_rand_reset.1506875556 -covoverwrite' seed=66877975107323616143493391178796014810330272264188947885094282780553637861540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66877975107323616143493391178796014810330272264188947885094282780553637861540 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_hw_reset","qual_name":"3.rv_dm_jtag_dtm_csr_hw_reset.80567652319584297633436061173413280249169437067210836676156837308478685229598","seed":80567652319584297633436061173413280249169437067210836676156837308478685229598,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3135549982 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3135549982 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dtm_csr_hw_reset.3135549982 -covoverwrite' seed=80567652319584297633436061173413280249169437067210836676156837308478685229598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80567652319584297633436061173413280249169437067210836676156837308478685229598 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"3.rv_dm_jtag_dtm_csr_rw.26122456136989275816596840981102052020239533390186023868206393368362900012681","seed":26122456136989275816596840981102052020239533390186023868206393368362900012681,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=813710985 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.813710985 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dtm_csr_rw.813710985 -covoverwrite' seed=26122456136989275816596840981102052020239533390186023868206393368362900012681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26122456136989275816596840981102052020239533390186023868206393368362900012681 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_bit_bash","qual_name":"3.rv_dm_jtag_dtm_csr_bit_bash.22087169962232464083231254273442804827231338232330280151249335045285832495467","seed":22087169962232464083231254273442804827231338232330280151249335045285832495467,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3596292459 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3596292459 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dtm_csr_bit_bash.3596292459 -covoverwrite' seed=22087169962232464083231254273442804827231338232330280151249335045285832495467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22087169962232464083231254273442804827231338232330280151249335045285832495467 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_aliasing","qual_name":"3.rv_dm_jtag_dtm_csr_aliasing.89376491860565425241140549981367289504207813637103497234175033138996036127014","seed":89376491860565425241140549981367289504207813637103497234175033138996036127014,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3683535142 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3683535142 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dtm_csr_aliasing.3683535142 -covoverwrite' seed=89376491860565425241140549981367289504207813637103497234175033138996036127014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89376491860565425241140549981367289504207813637103497234175033138996036127014 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dtm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_hw_reset","qual_name":"3.rv_dm_jtag_dmi_csr_hw_reset.72133623268993529277350834779407119269759269707248944493375987100009803788445","seed":72133623268993529277350834779407119269759269707248944493375987100009803788445,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3217010845 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3217010845 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dmi_csr_hw_reset.3217010845 -covoverwrite' seed=72133623268993529277350834779407119269759269707248944493375987100009803788445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72133623268993529277350834779407119269759269707248944493375987100009803788445 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"3.rv_dm_jtag_dmi_csr_rw.70207964398700630011729796313032650634328565605466168054203688700697724586992","seed":70207964398700630011729796313032650634328565605466168054203688700697724586992,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2793147376 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2793147376 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dmi_csr_rw.2793147376 -covoverwrite' seed=70207964398700630011729796313032650634328565605466168054203688700697724586992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70207964398700630011729796313032650634328565605466168054203688700697724586992 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"3.rv_dm_jtag_dmi_csr_bit_bash.6182699381237397025544487708560913203288958500440036101803672723725031135826","seed":6182699381237397025544487708560913203288958500440036101803672723725031135826,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=776034898 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.776034898 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dmi_csr_bit_bash.776034898 -covoverwrite' seed=6182699381237397025544487708560913203288958500440036101803672723725031135826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6182699381237397025544487708560913203288958500440036101803672723725031135826 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_aliasing","qual_name":"3.rv_dm_jtag_dmi_csr_aliasing.62169450476486042165548621370680209373891666534672091252512322206912648333938","seed":62169450476486042165548621370680209373891666534672091252512322206912648333938,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2232699506 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2232699506 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_jtag_dmi_csr_aliasing.2232699506 -covoverwrite' seed=62169450476486042165548621370680209373891666534672091252512322206912648333938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62169450476486042165548621370680209373891666534672091252512322206912648333938 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_jtag_dmi_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"3.rv_dm_sba_tl_access.4377657498113067278431375000239267644313014539417971240404212117363705953977","seed":4377657498113067278431375000239267644313014539417971240404212117363705953977,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2234695353 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_sba_tl_access.2234695353 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_sba_tl_access.2234695353 -covoverwrite' seed=4377657498113067278431375000239267644313014539417971240404212117363705953977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4377657498113067278431375000239267644313014539417971240404212117363705953977 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"3.rv_dm_delayed_resp_sba_tl_access.12209583487352220212319769712913481964408209648718883460191282190377510616807","seed":12209583487352220212319769712913481964408209648718883460191282190377510616807,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=682213095 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.682213095 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_delayed_resp_sba_tl_access.682213095 -covoverwrite' seed=12209583487352220212319769712913481964408209648718883460191282190377510616807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12209583487352220212319769712913481964408209648718883460191282190377510616807 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"3.rv_dm_bad_sba_tl_access.32279451750541741253335885968544839384135019646667783305705557657867654779082","seed":32279451750541741253335885968544839384135019646667783305705557657867654779082,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3787968714 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_bad_sba_tl_access.3787968714 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_bad_sba_tl_access.3787968714 -covoverwrite' seed=32279451750541741253335885968544839384135019646667783305705557657867654779082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32279451750541741253335885968544839384135019646667783305705557657867654779082 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"3.rv_dm_autoincr_sba_tl_access.24184657880973074944930858620784126697555712476074324727295729423637028777501","seed":24184657880973074944930858620784126697555712476074324727295729423637028777501,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3631984157 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_autoincr_sba_tl_access.3631984157 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_autoincr_sba_tl_access.3631984157 -covoverwrite' seed=24184657880973074944930858620784126697555712476074324727295729423637028777501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24184657880973074944930858620784126697555712476074324727295729423637028777501 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"3.rv_dm_tap_fsm_rand_reset.113482466597236799111131298915485647476054390658069694226021523209692990893287","seed":113482466597236799111131298915485647476054390658069694226021523209692990893287,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1480027367 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1480027367 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_tap_fsm_rand_reset.1480027367 -covoverwrite' seed=113482466597236799111131298915485647476054390658069694226021523209692990893287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113482466597236799111131298915485647476054390658069694226021523209692990893287 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_hart_unavail","qual_name":"3.rv_dm_hart_unavail.51192502276248458116098023413248797112518072493255488956122828270957386288498","seed":51192502276248458116098023413248797112518072493255488956122828270957386288498,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_hart_unavail/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_hart_unavail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2213563762 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_hart_unavail.2213563762 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_hart_unavail.2213563762 -covoverwrite' seed=51192502276248458116098023413248797112518072493255488956122828270957386288498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51192502276248458116098023413248797112518072493255488956122828270957386288498 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_hart_unavail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hart_unavail_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"3.rv_dm_halt_resume_whereto.50443103725568355617463899523674332743468100189081735274487032717379624572066","seed":50443103725568355617463899523674332743468100189081735274487032717379624572066,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=738006178 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_halt_resume_whereto.738006178 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_halt_resume_whereto.738006178 -covoverwrite' seed=50443103725568355617463899523674332743468100189081735274487032717379624572066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50443103725568355617463899523674332743468100189081735274487032717379624572066 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"3.rv_dm_buffered_enable.74303307218360797868148126604130156830248244947854668055389004881806722650392","seed":74303307218360797868148126604130156830248244947854668055389004881806722650392,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=786747672 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_buffered_enable.786747672 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_buffered_enable.786747672 -covoverwrite' seed=74303307218360797868148126604130156830248244947854668055389004881806722650392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74303307218360797868148126604130156830248244947854668055389004881806722650392 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sparse_lc_gate_fsm","qual_name":"3.rv_dm_sparse_lc_gate_fsm.93253636703036078615964212803720430072644127843418387934769534955468489992583","seed":93253636703036078615964212803720430072644127843418387934769534955468489992583,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sparse_lc_gate_fsm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sparse_lc_gate_fsm/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=270772615 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_sparse_lc_gate_fsm.270772615 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_sparse_lc_gate_fsm.270772615 -covoverwrite' seed=93253636703036078615964212803720430072644127843418387934769534955468489992583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93253636703036078615964212803720430072644127843418387934769534955468489992583 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sparse_lc_gate_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sparse_lc_gate_fsm_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"3.rv_dm_stress_all_with_rand_reset.9714942137675116885235461545278608863290862278085688348328097478912013981761","seed":9714942137675116885235461545278608863290862278085688348328097478912013981761,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=625956929 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_stress_all_with_rand_reset.625956929 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_stress_all_with_rand_reset.625956929 -covoverwrite' seed=9714942137675116885235461545278608863290862278085688348328097478912013981761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9714942137675116885235461545278608863290862278085688348328097478912013981761 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sec_cm","qual_name":"3.rv_dm_sec_cm.65504039440098541996758363208408905348105096284433112522796179033150771561202","seed":65504039440098541996758363208408905348105096284433112522796179033150771561202,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4294050546 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_sec_cm.4294050546 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_sec_cm.4294050546 -covoverwrite' seed=65504039440098541996758363208408905348105096284433112522796179033150771561202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65504039440098541996758363208408905348105096284433112522796179033150771561202 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"3.rv_dm_tl_errors.114316975852295612368512742915276200862444331790402077257037145406607089727779","seed":114316975852295612368512742915276200862444331790402077257037145406607089727779,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3634886947 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_tl_errors.3634886947 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_tl_errors.3634886947 -covoverwrite' seed=114316975852295612368512742915276200862444331790402077257037145406607089727779 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114316975852295612368512742915276200862444331790402077257037145406607089727779 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"3.rv_dm_tl_intg_err.33488166547074781247449339760824880751486744713387329370112958017038820749206","seed":33488166547074781247449339760824880751486744713387329370112958017038820749206,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2813243286 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2813243286 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_tl_intg_err.2813243286 -covoverwrite' seed=33488166547074781247449339760824880751486744713387329370112958017038820749206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33488166547074781247449339760824880751486744713387329370112958017038820749206 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"3.rv_dm_alert_test.32667252149704456344568445304616331157229118676762786468316201653491905179489","seed":32667252149704456344568445304616331157229118676762786468316201653491905179489,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3467226977 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/3.rv_dm_alert_test.3467226977 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 3.rv_dm_alert_test.3467226977 -covoverwrite' seed=32667252149704456344568445304616331157229118676762786468316201653491905179489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32667252149704456344568445304616331157229118676762786468316201653491905179489 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_rw","qual_name":"3.rv_dm_csr_rw.37527910099075995919787638465778194936075040941891860148560503629256479036969","seed":37527910099075995919787638465778194936075040941891860148560503629256479036969,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1714247209 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_csr_rw.1714247209 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_csr_rw.1714247209 -covoverwrite' seed=37527910099075995919787638465778194936075040941891860148560503629256479036969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37527910099075995919787638465778194936075040941891860148560503629256479036969 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_same_csr_outstanding","qual_name":"3.rv_dm_same_csr_outstanding.79003565927786152295438667858021062921609559353759986416923099016993401577077","seed":79003565927786152295438667858021062921609559353759986416923099016993401577077,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3388579445 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3388579445 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_same_csr_outstanding.3388579445 -covoverwrite' seed=79003565927786152295438667858021062921609559353759986416923099016993401577077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79003565927786152295438667858021062921609559353759986416923099016993401577077 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"3.rv_dm_csr_mem_rw_with_rand_reset.22288422863639462746686666727369187211693863753662139773556603219329954438886","seed":22288422863639462746686666727369187211693863753662139773556603219329954438886,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1021664998 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1021664998 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_dm_csr_mem_rw_with_rand_reset.1021664998 -covoverwrite' seed=22288422863639462746686666727369187211693863753662139773556603219329954438886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22288422863639462746686666727369187211693863753662139773556603219329954438886 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_hw_reset","qual_name":"4.rv_dm_jtag_dtm_csr_hw_reset.65859516421565510752847619876941235094499448325905321269348975452051785576460","seed":65859516421565510752847619876941235094499448325905321269348975452051785576460,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3576360972 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3576360972 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dtm_csr_hw_reset.3576360972 -covoverwrite' seed=65859516421565510752847619876941235094499448325905321269348975452051785576460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65859516421565510752847619876941235094499448325905321269348975452051785576460 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"4.rv_dm_jtag_dtm_csr_rw.79034957115428520718596581221390183792713438087643022177935098306125789291919","seed":79034957115428520718596581221390183792713438087643022177935098306125789291919,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=600204687 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.600204687 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dtm_csr_rw.600204687 -covoverwrite' seed=79034957115428520718596581221390183792713438087643022177935098306125789291919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79034957115428520718596581221390183792713438087643022177935098306125789291919 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_bit_bash","qual_name":"4.rv_dm_jtag_dtm_csr_bit_bash.84078426101415266539018954596794322437236237173666465046570840326745072608228","seed":84078426101415266539018954596794322437236237173666465046570840326745072608228,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3854050276 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3854050276 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dtm_csr_bit_bash.3854050276 -covoverwrite' seed=84078426101415266539018954596794322437236237173666465046570840326745072608228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84078426101415266539018954596794322437236237173666465046570840326745072608228 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_aliasing","qual_name":"4.rv_dm_jtag_dtm_csr_aliasing.20405991371552844118852860188049222351229722963928554013629602591711549112897","seed":20405991371552844118852860188049222351229722963928554013629602591711549112897,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3494822465 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3494822465 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dtm_csr_aliasing.3494822465 -covoverwrite' seed=20405991371552844118852860188049222351229722963928554013629602591711549112897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20405991371552844118852860188049222351229722963928554013629602591711549112897 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dtm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_hw_reset","qual_name":"4.rv_dm_jtag_dmi_csr_hw_reset.94045307412536402122162902538112103727357849392447753725625816230385192042794","seed":94045307412536402122162902538112103727357849392447753725625816230385192042794,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_hw_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3280240938 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3280240938 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dmi_csr_hw_reset.3280240938 -covoverwrite' seed=94045307412536402122162902538112103727357849392447753725625816230385192042794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94045307412536402122162902538112103727357849392447753725625816230385192042794 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"4.rv_dm_jtag_dmi_csr_rw.99836758873977957553852610467165360691381925600870150412880006676588925483420","seed":99836758873977957553852610467165360691381925600870150412880006676588925483420,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4134992284 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4134992284 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dmi_csr_rw.4134992284 -covoverwrite' seed=99836758873977957553852610467165360691381925600870150412880006676588925483420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99836758873977957553852610467165360691381925600870150412880006676588925483420 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"4.rv_dm_jtag_dmi_csr_bit_bash.22943413047561599132765252818652447566844754131937245737316344540606458666353","seed":22943413047561599132765252818652447566844754131937245737316344540606458666353,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2981797233 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2981797233 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dmi_csr_bit_bash.2981797233 -covoverwrite' seed=22943413047561599132765252818652447566844754131937245737316344540606458666353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22943413047561599132765252818652447566844754131937245737316344540606458666353 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_aliasing","qual_name":"4.rv_dm_jtag_dmi_csr_aliasing.60655114547135141131893693819791663194611700834342954969883467474334953676733","seed":60655114547135141131893693819791663194611700834342954969883467474334953676733,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_aliasing/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3222446013 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3222446013 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_jtag_dmi_csr_aliasing.3222446013 -covoverwrite' seed=60655114547135141131893693819791663194611700834342954969883467474334953676733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60655114547135141131893693819791663194611700834342954969883467474334953676733 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_jtag_dmi_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"4.rv_dm_sba_tl_access.108969106441839140997838887058707435002685058538825341999021181588941355143227","seed":108969106441839140997838887058707435002685058538825341999021181588941355143227,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=858837051 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_sba_tl_access.858837051 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_sba_tl_access.858837051 -covoverwrite' seed=108969106441839140997838887058707435002685058538825341999021181588941355143227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108969106441839140997838887058707435002685058538825341999021181588941355143227 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"4.rv_dm_delayed_resp_sba_tl_access.52561935446993718250246746658117621141564217260188216456143726005752302150028","seed":52561935446993718250246746658117621141564217260188216456143726005752302150028,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3770163596 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3770163596 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_delayed_resp_sba_tl_access.3770163596 -covoverwrite' seed=52561935446993718250246746658117621141564217260188216456143726005752302150028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52561935446993718250246746658117621141564217260188216456143726005752302150028 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"4.rv_dm_bad_sba_tl_access.90448484611259263110454294271712363475852863129248863745381904881458029240364","seed":90448484611259263110454294271712363475852863129248863745381904881458029240364,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=203399212 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_bad_sba_tl_access.203399212 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_bad_sba_tl_access.203399212 -covoverwrite' seed=90448484611259263110454294271712363475852863129248863745381904881458029240364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90448484611259263110454294271712363475852863129248863745381904881458029240364 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"4.rv_dm_autoincr_sba_tl_access.107616905579990319723034015168930593749092020981788308990957188795923639004440","seed":107616905579990319723034015168930593749092020981788308990957188795923639004440,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=790588696 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_autoincr_sba_tl_access.790588696 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_autoincr_sba_tl_access.790588696 -covoverwrite' seed=107616905579990319723034015168930593749092020981788308990957188795923639004440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107616905579990319723034015168930593749092020981788308990957188795923639004440 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"4.rv_dm_tap_fsm_rand_reset.58479017657194917165226269269690702336931507232907958587130866462228584575933","seed":58479017657194917165226269269690702336931507232907958587130866462228584575933,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1371255741 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1371255741 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_tap_fsm_rand_reset.1371255741 -covoverwrite' seed=58479017657194917165226269269690702336931507232907958587130866462228584575933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58479017657194917165226269269690702336931507232907958587130866462228584575933 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_hart_unavail","qual_name":"4.rv_dm_hart_unavail.7070056900684000734998210719437892982657935259239062301770024660301892435137","seed":7070056900684000734998210719437892982657935259239062301770024660301892435137,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_hart_unavail/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_hart_unavail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2302819521 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_hart_unavail.2302819521 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_hart_unavail.2302819521 -covoverwrite' seed=7070056900684000734998210719437892982657935259239062301770024660301892435137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7070056900684000734998210719437892982657935259239062301770024660301892435137 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_hart_unavail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hart_unavail_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"4.rv_dm_halt_resume_whereto.6900642285708199538439187802826957952151343864527382205877982765183457454817","seed":6900642285708199538439187802826957952151343864527382205877982765183457454817,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3343805153 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_halt_resume_whereto.3343805153 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_halt_resume_whereto.3343805153 -covoverwrite' seed=6900642285708199538439187802826957952151343864527382205877982765183457454817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6900642285708199538439187802826957952151343864527382205877982765183457454817 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"4.rv_dm_buffered_enable.34825889526723339715610933462314621449758139772058166568578926448301871111279","seed":34825889526723339715610933462314621449758139772058166568578926448301871111279,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1217567855 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_buffered_enable.1217567855 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_buffered_enable.1217567855 -covoverwrite' seed=34825889526723339715610933462314621449758139772058166568578926448301871111279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34825889526723339715610933462314621449758139772058166568578926448301871111279 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"4.rv_dm_stress_all_with_rand_reset.16742855394483592109873028871181200075037213437121075986017468329188365295684","seed":16742855394483592109873028871181200075037213437121075986017468329188365295684,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=56221764 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_stress_all_with_rand_reset.56221764 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_stress_all_with_rand_reset.56221764 -covoverwrite' seed=16742855394483592109873028871181200075037213437121075986017468329188365295684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16742855394483592109873028871181200075037213437121075986017468329188365295684 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sec_cm","qual_name":"4.rv_dm_sec_cm.86991982872394365247601976989718883270458310816048514046696960592623034112626","seed":86991982872394365247601976989718883270458310816048514046696960592623034112626,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_sec_cm/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2423200370 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_sec_cm.2423200370 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_sec_cm.2423200370 -covoverwrite' seed=86991982872394365247601976989718883270458310816048514046696960592623034112626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86991982872394365247601976989718883270458310816048514046696960592623034112626 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"4.rv_dm_tl_errors.93919523814399166981939651451214768961414726235851723990446743631830068132534","seed":93919523814399166981939651451214768961414726235851723990446743631830068132534,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3705305782 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_tl_errors.3705305782 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_tl_errors.3705305782 -covoverwrite' seed=93919523814399166981939651451214768961414726235851723990446743631830068132534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93919523814399166981939651451214768961414726235851723990446743631830068132534 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"4.rv_dm_tl_intg_err.43709013262148297909233076726068311887348546070963843980633894238951891843670","seed":43709013262148297909233076726068311887348546070963843980633894238951891843670,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1167637078 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1167637078 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_tl_intg_err.1167637078 -covoverwrite' seed=43709013262148297909233076726068311887348546070963843980633894238951891843670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43709013262148297909233076726068311887348546070963843980633894238951891843670 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"4.rv_dm_alert_test.27712775071889080963337690879650696387517335435604527114704142202594986515876","seed":27712775071889080963337690879650696387517335435604527114704142202594986515876,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3180289444 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/4.rv_dm_alert_test.3180289444 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 4.rv_dm_alert_test.3180289444 -covoverwrite' seed=27712775071889080963337690879650696387517335435604527114704142202594986515876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27712775071889080963337690879650696387517335435604527114704142202594986515876 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_rw","qual_name":"4.rv_dm_csr_rw.95649196713966778736222229889348291123649815141513936725431915640613178364656","seed":95649196713966778736222229889348291123649815141513936725431915640613178364656,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1860621040 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_csr_rw.1860621040 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_csr_rw.1860621040 -covoverwrite' seed=95649196713966778736222229889348291123649815141513936725431915640613178364656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95649196713966778736222229889348291123649815141513936725431915640613178364656 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_same_csr_outstanding","qual_name":"4.rv_dm_same_csr_outstanding.109176218139495256957644540738444452659861957701975440419953479429534058706127","seed":109176218139495256957644540738444452659861957701975440419953479429534058706127,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_same_csr_outstanding/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=327840975 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.327840975 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_same_csr_outstanding.327840975 -covoverwrite' seed=109176218139495256957644540738444452659861957701975440419953479429534058706127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109176218139495256957644540738444452659861957701975440419953479429534058706127 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"4.rv_dm_csr_mem_rw_with_rand_reset.110029711919877376355258263385314456577451368244345721464195622278277489126367","seed":110029711919877376355258263385314456577451368244345721464195622278277489126367,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4250561503 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4250561503 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_dm_csr_mem_rw_with_rand_reset.4250561503 -covoverwrite' seed=110029711919877376355258263385314456577451368244345721464195622278277489126367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110029711919877376355258263385314456577451368244345721464195622278277489126367 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"5.rv_dm_jtag_dtm_csr_rw.67268328783620124720084826200657548734763194592499245078620624717705967458775","seed":67268328783620124720084826200657548734763194592499245078620624717705967458775,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=486955479 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.486955479 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_dm_jtag_dtm_csr_rw.486955479 -covoverwrite' seed=67268328783620124720084826200657548734763194592499245078620624717705967458775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67268328783620124720084826200657548734763194592499245078620624717705967458775 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"5.rv_dm_jtag_dmi_csr_rw.112083371070653633895760168667369271237435454099677331846406005884923737999160","seed":112083371070653633895760168667369271237435454099677331846406005884923737999160,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=893847352 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.893847352 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_dm_jtag_dmi_csr_rw.893847352 -covoverwrite' seed=112083371070653633895760168667369271237435454099677331846406005884923737999160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112083371070653633895760168667369271237435454099677331846406005884923737999160 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"5.rv_dm_jtag_dmi_csr_bit_bash.19665978213223678321573374707983236765146743322188973125110872297976999295145","seed":19665978213223678321573374707983236765146743322188973125110872297976999295145,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3748509865 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3748509865 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_dm_jtag_dmi_csr_bit_bash.3748509865 -covoverwrite' seed=19665978213223678321573374707983236765146743322188973125110872297976999295145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19665978213223678321573374707983236765146743322188973125110872297976999295145 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"5.rv_dm_sba_tl_access.77575332155743812459098340335780550019002278041271095927716161373943924138055","seed":77575332155743812459098340335780550019002278041271095927716161373943924138055,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=598351943 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_sba_tl_access.598351943 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_sba_tl_access.598351943 -covoverwrite' seed=77575332155743812459098340335780550019002278041271095927716161373943924138055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77575332155743812459098340335780550019002278041271095927716161373943924138055 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"5.rv_dm_delayed_resp_sba_tl_access.44632124377852673285444453613133058532778347427151981342470230350729832819793","seed":44632124377852673285444453613133058532778347427151981342470230350729832819793,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4190628945 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.4190628945 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_delayed_resp_sba_tl_access.4190628945 -covoverwrite' seed=44632124377852673285444453613133058532778347427151981342470230350729832819793 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44632124377852673285444453613133058532778347427151981342470230350729832819793 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"5.rv_dm_bad_sba_tl_access.6492107162097396816825249337442560857758214494549163515867702723926521111293","seed":6492107162097396816825249337442560857758214494549163515867702723926521111293,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1845584637 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_bad_sba_tl_access.1845584637 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_bad_sba_tl_access.1845584637 -covoverwrite' seed=6492107162097396816825249337442560857758214494549163515867702723926521111293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6492107162097396816825249337442560857758214494549163515867702723926521111293 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"5.rv_dm_autoincr_sba_tl_access.84381744482415384937118920863557543159126056362110397228062670845292664322517","seed":84381744482415384937118920863557543159126056362110397228062670845292664322517,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4130863573 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_autoincr_sba_tl_access.4130863573 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_autoincr_sba_tl_access.4130863573 -covoverwrite' seed=84381744482415384937118920863557543159126056362110397228062670845292664322517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84381744482415384937118920863557543159126056362110397228062670845292664322517 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"5.rv_dm_tap_fsm_rand_reset.49710683066818901944138327376604092997079534016740812010446607633341512571937","seed":49710683066818901944138327376604092997079534016740812010446607633341512571937,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2701286433 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2701286433 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_dm_tap_fsm_rand_reset.2701286433 -covoverwrite' seed=49710683066818901944138327376604092997079534016740812010446607633341512571937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49710683066818901944138327376604092997079534016740812010446607633341512571937 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"5.rv_dm_halt_resume_whereto.43712576654391803307080264866847936481987458837347191510250836452544995261923","seed":43712576654391803307080264866847936481987458837347191510250836452544995261923,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1095892451 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_halt_resume_whereto.1095892451 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_halt_resume_whereto.1095892451 -covoverwrite' seed=43712576654391803307080264866847936481987458837347191510250836452544995261923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43712576654391803307080264866847936481987458837347191510250836452544995261923 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"5.rv_dm_buffered_enable.29852397262505224482281032601442673203458708917379269578296495071869408505748","seed":29852397262505224482281032601442673203458708917379269578296495071869408505748,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=406974356 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_buffered_enable.406974356 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_buffered_enable.406974356 -covoverwrite' seed=29852397262505224482281032601442673203458708917379269578296495071869408505748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29852397262505224482281032601442673203458708917379269578296495071869408505748 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"5.rv_dm_stress_all_with_rand_reset.106010556150760362126101113350625834342241173475717437617470056007681380763099","seed":106010556150760362126101113350625834342241173475717437617470056007681380763099,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3214722523 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_stress_all_with_rand_reset.3214722523 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_stress_all_with_rand_reset.3214722523 -covoverwrite' seed=106010556150760362126101113350625834342241173475717437617470056007681380763099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106010556150760362126101113350625834342241173475717437617470056007681380763099 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"5.rv_dm_tl_errors.53959357622381789963853586426396725712401707720982529961064854762529519744929","seed":53959357622381789963853586426396725712401707720982529961064854762529519744929,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=469153697 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/5.rv_dm_tl_errors.469153697 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_dm_tl_errors.469153697 -covoverwrite' seed=53959357622381789963853586426396725712401707720982529961064854762529519744929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53959357622381789963853586426396725712401707720982529961064854762529519744929 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"5.rv_dm_tl_intg_err.109809016160852215670479682250411663616586321965742729676756105275319046391501","seed":109809016160852215670479682250411663616586321965742729676756105275319046391501,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2788181709 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2788181709 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_dm_tl_intg_err.2788181709 -covoverwrite' seed=109809016160852215670479682250411663616586321965742729676756105275319046391501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109809016160852215670479682250411663616586321965742729676756105275319046391501 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"5.rv_dm_alert_test.102056526722338363587318866561409691914180922914423102743878031521015173657808","seed":102056526722338363587318866561409691914180922914423102743878031521015173657808,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2042279120 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/5.rv_dm_alert_test.2042279120 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 5.rv_dm_alert_test.2042279120 -covoverwrite' seed=102056526722338363587318866561409691914180922914423102743878031521015173657808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102056526722338363587318866561409691914180922914423102743878031521015173657808 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"6.rv_dm_jtag_dtm_csr_rw.31589138495478693969328956314291033792012852540101727304932251623391712245960","seed":31589138495478693969328956314291033792012852540101727304932251623391712245960,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3309304008 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3309304008 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_dm_jtag_dtm_csr_rw.3309304008 -covoverwrite' seed=31589138495478693969328956314291033792012852540101727304932251623391712245960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31589138495478693969328956314291033792012852540101727304932251623391712245960 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"6.rv_dm_jtag_dmi_csr_rw.35851571451064177128821371810675060707994957316029599244492572406613999625565","seed":35851571451064177128821371810675060707994957316029599244492572406613999625565,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1110975837 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1110975837 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_dm_jtag_dmi_csr_rw.1110975837 -covoverwrite' seed=35851571451064177128821371810675060707994957316029599244492572406613999625565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35851571451064177128821371810675060707994957316029599244492572406613999625565 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"6.rv_dm_jtag_dmi_csr_bit_bash.61210450890690902974628371877329707827668295500867167649640227218894205327951","seed":61210450890690902974628371877329707827668295500867167649640227218894205327951,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4294810191 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4294810191 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_dm_jtag_dmi_csr_bit_bash.4294810191 -covoverwrite' seed=61210450890690902974628371877329707827668295500867167649640227218894205327951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61210450890690902974628371877329707827668295500867167649640227218894205327951 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"6.rv_dm_sba_tl_access.49610374475812820021087222566041872474808202982245341307805686578870160888928","seed":49610374475812820021087222566041872474808202982245341307805686578870160888928,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2525926496 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_sba_tl_access.2525926496 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_sba_tl_access.2525926496 -covoverwrite' seed=49610374475812820021087222566041872474808202982245341307805686578870160888928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49610374475812820021087222566041872474808202982245341307805686578870160888928 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"6.rv_dm_delayed_resp_sba_tl_access.69845587575144025071175893650181490412033356600821239094247797135356219245756","seed":69845587575144025071175893650181490412033356600821239094247797135356219245756,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2828420284 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2828420284 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_delayed_resp_sba_tl_access.2828420284 -covoverwrite' seed=69845587575144025071175893650181490412033356600821239094247797135356219245756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69845587575144025071175893650181490412033356600821239094247797135356219245756 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"6.rv_dm_bad_sba_tl_access.40216725161887753218053742987479772821359784853143130134911391196406838739555","seed":40216725161887753218053742987479772821359784853143130134911391196406838739555,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=27542115 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_bad_sba_tl_access.27542115 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_bad_sba_tl_access.27542115 -covoverwrite' seed=40216725161887753218053742987479772821359784853143130134911391196406838739555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40216725161887753218053742987479772821359784853143130134911391196406838739555 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"6.rv_dm_autoincr_sba_tl_access.109074217760759790765043156332432449380145779801749900788711955962942309052051","seed":109074217760759790765043156332432449380145779801749900788711955962942309052051,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1644211859 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_autoincr_sba_tl_access.1644211859 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_autoincr_sba_tl_access.1644211859 -covoverwrite' seed=109074217760759790765043156332432449380145779801749900788711955962942309052051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109074217760759790765043156332432449380145779801749900788711955962942309052051 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"6.rv_dm_tap_fsm_rand_reset.79466030953139227015238270774424146358996444590812969971873452404678716962709","seed":79466030953139227015238270774424146358996444590812969971873452404678716962709,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2408200085 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2408200085 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_dm_tap_fsm_rand_reset.2408200085 -covoverwrite' seed=79466030953139227015238270774424146358996444590812969971873452404678716962709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79466030953139227015238270774424146358996444590812969971873452404678716962709 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"6.rv_dm_halt_resume_whereto.70489483164946999205637008794737241283702882973743699307078480254464462161407","seed":70489483164946999205637008794737241283702882973743699307078480254464462161407,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1097336319 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_halt_resume_whereto.1097336319 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_halt_resume_whereto.1097336319 -covoverwrite' seed=70489483164946999205637008794737241283702882973743699307078480254464462161407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70489483164946999205637008794737241283702882973743699307078480254464462161407 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"6.rv_dm_buffered_enable.79658036655797039288250600207030921698876373630838532785093725056837222303501","seed":79658036655797039288250600207030921698876373630838532785093725056837222303501,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=344885005 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_buffered_enable.344885005 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_buffered_enable.344885005 -covoverwrite' seed=79658036655797039288250600207030921698876373630838532785093725056837222303501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79658036655797039288250600207030921698876373630838532785093725056837222303501 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"6.rv_dm_stress_all_with_rand_reset.48075842682074333327313269574529882662211796800772168157598859465693820134170","seed":48075842682074333327313269574529882662211796800772168157598859465693820134170,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2223022874 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_stress_all_with_rand_reset.2223022874 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_stress_all_with_rand_reset.2223022874 -covoverwrite' seed=48075842682074333327313269574529882662211796800772168157598859465693820134170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48075842682074333327313269574529882662211796800772168157598859465693820134170 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"6.rv_dm_tl_errors.21346489039218801084397221473776190822884386869856771071815062098679803422467","seed":21346489039218801084397221473776190822884386869856771071815062098679803422467,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=527443715 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/6.rv_dm_tl_errors.527443715 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_dm_tl_errors.527443715 -covoverwrite' seed=21346489039218801084397221473776190822884386869856771071815062098679803422467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21346489039218801084397221473776190822884386869856771071815062098679803422467 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"6.rv_dm_tl_intg_err.57042520198599192284778706362452812627738868212498623482438993758742443014610","seed":57042520198599192284778706362452812627738868212498623482438993758742443014610,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1360607698 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1360607698 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_dm_tl_intg_err.1360607698 -covoverwrite' seed=57042520198599192284778706362452812627738868212498623482438993758742443014610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57042520198599192284778706362452812627738868212498623482438993758742443014610 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"6.rv_dm_alert_test.4377577888708575907659073883707556474648954418388165893575327429180210517154","seed":4377577888708575907659073883707556474648954418388165893575327429180210517154,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=977769634 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/6.rv_dm_alert_test.977769634 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 6.rv_dm_alert_test.977769634 -covoverwrite' seed=4377577888708575907659073883707556474648954418388165893575327429180210517154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4377577888708575907659073883707556474648954418388165893575327429180210517154 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"7.rv_dm_jtag_dtm_csr_rw.68079241260193237234417064766367923364695528268941427750347280036080044466670","seed":68079241260193237234417064766367923364695528268941427750347280036080044466670,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=866378222 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.866378222 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_dm_jtag_dtm_csr_rw.866378222 -covoverwrite' seed=68079241260193237234417064766367923364695528268941427750347280036080044466670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68079241260193237234417064766367923364695528268941427750347280036080044466670 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"7.rv_dm_jtag_dmi_csr_rw.64413839976657021654931803009230484974529388299112150742754640167968149640309","seed":64413839976657021654931803009230484974529388299112150742754640167968149640309,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4033647733 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4033647733 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_dm_jtag_dmi_csr_rw.4033647733 -covoverwrite' seed=64413839976657021654931803009230484974529388299112150742754640167968149640309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64413839976657021654931803009230484974529388299112150742754640167968149640309 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"7.rv_dm_jtag_dmi_csr_bit_bash.78688741333176507302560478376917081987321470146035724581974662742653688009545","seed":78688741333176507302560478376917081987321470146035724581974662742653688009545,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1311429449 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1311429449 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_dm_jtag_dmi_csr_bit_bash.1311429449 -covoverwrite' seed=78688741333176507302560478376917081987321470146035724581974662742653688009545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78688741333176507302560478376917081987321470146035724581974662742653688009545 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"7.rv_dm_sba_tl_access.72148428346942174702832133312316289830908959114463616227088747390266361640669","seed":72148428346942174702832133312316289830908959114463616227088747390266361640669,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=961672925 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_sba_tl_access.961672925 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_sba_tl_access.961672925 -covoverwrite' seed=72148428346942174702832133312316289830908959114463616227088747390266361640669 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72148428346942174702832133312316289830908959114463616227088747390266361640669 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"7.rv_dm_delayed_resp_sba_tl_access.98441740329178774511010271674169666889363179497477230687968538831130065201826","seed":98441740329178774511010271674169666889363179497477230687968538831130065201826,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1693805218 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1693805218 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_delayed_resp_sba_tl_access.1693805218 -covoverwrite' seed=98441740329178774511010271674169666889363179497477230687968538831130065201826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98441740329178774511010271674169666889363179497477230687968538831130065201826 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"7.rv_dm_bad_sba_tl_access.93998208720010905462402879347555805658318207699169954865688763953941952066609","seed":93998208720010905462402879347555805658318207699169954865688763953941952066609,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3142705 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_bad_sba_tl_access.3142705 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_bad_sba_tl_access.3142705 -covoverwrite' seed=93998208720010905462402879347555805658318207699169954865688763953941952066609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93998208720010905462402879347555805658318207699169954865688763953941952066609 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"7.rv_dm_autoincr_sba_tl_access.39240448541394255141748001168322926574674605661131097694366665591682209918643","seed":39240448541394255141748001168322926574674605661131097694366665591682209918643,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2538319539 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_autoincr_sba_tl_access.2538319539 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_autoincr_sba_tl_access.2538319539 -covoverwrite' seed=39240448541394255141748001168322926574674605661131097694366665591682209918643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39240448541394255141748001168322926574674605661131097694366665591682209918643 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"7.rv_dm_tap_fsm_rand_reset.39035635645089405323711845381626014414291718418264583889213441089900412246419","seed":39035635645089405323711845381626014414291718418264583889213441089900412246419,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=854170003 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.854170003 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_dm_tap_fsm_rand_reset.854170003 -covoverwrite' seed=39035635645089405323711845381626014414291718418264583889213441089900412246419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39035635645089405323711845381626014414291718418264583889213441089900412246419 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_halt_resume_whereto","qual_name":"7.rv_dm_halt_resume_whereto.14820104292007250818068235797129207287988095681655301114851161910988742969263","seed":14820104292007250818068235797129207287988095681655301114851161910988742969263,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_halt_resume_whereto/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1928185775 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_halt_resume_whereto.1928185775 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_halt_resume_whereto.1928185775 -covoverwrite' seed=14820104292007250818068235797129207287988095681655301114851161910988742969263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14820104292007250818068235797129207287988095681655301114851161910988742969263 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"7.rv_dm_buffered_enable.13541090085972932104206966233308942891245879608986896532772460880931224123618","seed":13541090085972932104206966233308942891245879608986896532772460880931224123618,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1533901026 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_buffered_enable.1533901026 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_buffered_enable.1533901026 -covoverwrite' seed=13541090085972932104206966233308942891245879608986896532772460880931224123618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13541090085972932104206966233308942891245879608986896532772460880931224123618 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"7.rv_dm_stress_all_with_rand_reset.53953792767276560120047816415077153458818775657135274940245409678819592716097","seed":53953792767276560120047816415077153458818775657135274940245409678819592716097,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3523690305 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_stress_all_with_rand_reset.3523690305 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_stress_all_with_rand_reset.3523690305 -covoverwrite' seed=53953792767276560120047816415077153458818775657135274940245409678819592716097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53953792767276560120047816415077153458818775657135274940245409678819592716097 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"7.rv_dm_tl_errors.53132801631777255465249057778370129605030759486094508019738429121770626229252","seed":53132801631777255465249057778370129605030759486094508019738429121770626229252,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1337467908 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/7.rv_dm_tl_errors.1337467908 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_dm_tl_errors.1337467908 -covoverwrite' seed=53132801631777255465249057778370129605030759486094508019738429121770626229252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53132801631777255465249057778370129605030759486094508019738429121770626229252 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"7.rv_dm_tl_intg_err.37016340721924810974912208981931033253795368249940682906715010670071077390891","seed":37016340721924810974912208981931033253795368249940682906715010670071077390891,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4107782699 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4107782699 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_dm_tl_intg_err.4107782699 -covoverwrite' seed=37016340721924810974912208981931033253795368249940682906715010670071077390891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37016340721924810974912208981931033253795368249940682906715010670071077390891 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"7.rv_dm_alert_test.115168730581380425246679338003037659657268779469267399809114724638328915057629","seed":115168730581380425246679338003037659657268779469267399809114724638328915057629,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3267714013 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/7.rv_dm_alert_test.3267714013 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 7.rv_dm_alert_test.3267714013 -covoverwrite' seed=115168730581380425246679338003037659657268779469267399809114724638328915057629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115168730581380425246679338003037659657268779469267399809114724638328915057629 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"8.rv_dm_jtag_dtm_csr_rw.5868991058735095043304571149834589736821825856254352137136693587575992575156","seed":5868991058735095043304571149834589736821825856254352137136693587575992575156,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1617519796 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1617519796 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_dm_jtag_dtm_csr_rw.1617519796 -covoverwrite' seed=5868991058735095043304571149834589736821825856254352137136693587575992575156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5868991058735095043304571149834589736821825856254352137136693587575992575156 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"8.rv_dm_jtag_dmi_csr_rw.67610398016234542076046505165682812365444581210413902172511076063534458090091","seed":67610398016234542076046505165682812365444581210413902172511076063534458090091,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1909994091 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1909994091 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_dm_jtag_dmi_csr_rw.1909994091 -covoverwrite' seed=67610398016234542076046505165682812365444581210413902172511076063534458090091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67610398016234542076046505165682812365444581210413902172511076063534458090091 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"8.rv_dm_jtag_dmi_csr_bit_bash.13975291930816617712430628976020912917154691135029537392920932768059042297447","seed":13975291930816617712430628976020912917154691135029537392920932768059042297447,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3328964199 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3328964199 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_dm_jtag_dmi_csr_bit_bash.3328964199 -covoverwrite' seed=13975291930816617712430628976020912917154691135029537392920932768059042297447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13975291930816617712430628976020912917154691135029537392920932768059042297447 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"8.rv_dm_sba_tl_access.27932810817962770983815623839425395143001854940869687094144603733729688761112","seed":27932810817962770983815623839425395143001854940869687094144603733729688761112,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1594176280 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_sba_tl_access.1594176280 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_sba_tl_access.1594176280 -covoverwrite' seed=27932810817962770983815623839425395143001854940869687094144603733729688761112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27932810817962770983815623839425395143001854940869687094144603733729688761112 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"8.rv_dm_delayed_resp_sba_tl_access.35669157958048612764010343447150087116816020413823590173579565981670149704136","seed":35669157958048612764010343447150087116816020413823590173579565981670149704136,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3186870728 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3186870728 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_delayed_resp_sba_tl_access.3186870728 -covoverwrite' seed=35669157958048612764010343447150087116816020413823590173579565981670149704136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35669157958048612764010343447150087116816020413823590173579565981670149704136 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"8.rv_dm_bad_sba_tl_access.95087065296345932832819893496479843048176291237754251989632805621098421010778","seed":95087065296345932832819893496479843048176291237754251989632805621098421010778,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2633089370 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_bad_sba_tl_access.2633089370 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_bad_sba_tl_access.2633089370 -covoverwrite' seed=95087065296345932832819893496479843048176291237754251989632805621098421010778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95087065296345932832819893496479843048176291237754251989632805621098421010778 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"8.rv_dm_autoincr_sba_tl_access.44535834201031590291536721972812988924839617477320164844885000985582269459429","seed":44535834201031590291536721972812988924839617477320164844885000985582269459429,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3376770021 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_autoincr_sba_tl_access.3376770021 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_autoincr_sba_tl_access.3376770021 -covoverwrite' seed=44535834201031590291536721972812988924839617477320164844885000985582269459429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44535834201031590291536721972812988924839617477320164844885000985582269459429 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"8.rv_dm_tap_fsm_rand_reset.79240145357911788645593514642955102495378336566578450142056750706570664171718","seed":79240145357911788645593514642955102495378336566578450142056750706570664171718,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2006800582 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2006800582 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_dm_tap_fsm_rand_reset.2006800582 -covoverwrite' seed=79240145357911788645593514642955102495378336566578450142056750706570664171718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79240145357911788645593514642955102495378336566578450142056750706570664171718 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"8.rv_dm_buffered_enable.1348888090900683119871412782257703987538596966960032048012495133847113942612","seed":1348888090900683119871412782257703987538596966960032048012495133847113942612,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2284832340 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_buffered_enable.2284832340 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_buffered_enable.2284832340 -covoverwrite' seed=1348888090900683119871412782257703987538596966960032048012495133847113942612 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1348888090900683119871412782257703987538596966960032048012495133847113942612 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"8.rv_dm_stress_all_with_rand_reset.30532127793339447612320425641573602707008352982011953576012872058825136681328","seed":30532127793339447612320425641573602707008352982011953576012872058825136681328,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=557068656 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_stress_all_with_rand_reset.557068656 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_stress_all_with_rand_reset.557068656 -covoverwrite' seed=30532127793339447612320425641573602707008352982011953576012872058825136681328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30532127793339447612320425641573602707008352982011953576012872058825136681328 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"8.rv_dm_tl_errors.60065624323396942075082236990882738673370919446688987252149445759536347814855","seed":60065624323396942075082236990882738673370919446688987252149445759536347814855,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=284498887 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/8.rv_dm_tl_errors.284498887 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_dm_tl_errors.284498887 -covoverwrite' seed=60065624323396942075082236990882738673370919446688987252149445759536347814855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60065624323396942075082236990882738673370919446688987252149445759536347814855 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"8.rv_dm_tl_intg_err.22345001041533511123648236552715221645822941037475775261720687046497503453477","seed":22345001041533511123648236552715221645822941037475775261720687046497503453477,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=490643749 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/8.rv_dm_tl_intg_err.490643749 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_dm_tl_intg_err.490643749 -covoverwrite' seed=22345001041533511123648236552715221645822941037475775261720687046497503453477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22345001041533511123648236552715221645822941037475775261720687046497503453477 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"8.rv_dm_alert_test.21699199157203842092149450347780887899901442716664861914191667175865059005405","seed":21699199157203842092149450347780887899901442716664861914191667175865059005405,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=258626525 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/8.rv_dm_alert_test.258626525 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 8.rv_dm_alert_test.258626525 -covoverwrite' seed=21699199157203842092149450347780887899901442716664861914191667175865059005405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21699199157203842092149450347780887899901442716664861914191667175865059005405 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"9.rv_dm_jtag_dtm_csr_rw.86892225817222789914297706746696162692993735924339722111417823716932147838984","seed":86892225817222789914297706746696162692993735924339722111417823716932147838984,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4217995272 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4217995272 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_dm_jtag_dtm_csr_rw.4217995272 -covoverwrite' seed=86892225817222789914297706746696162692993735924339722111417823716932147838984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86892225817222789914297706746696162692993735924339722111417823716932147838984 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"9.rv_dm_jtag_dmi_csr_rw.80755381974988456062674487024290964688201257850591926645689148158390683837129","seed":80755381974988456062674487024290964688201257850591926645689148158390683837129,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1517822665 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1517822665 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_dm_jtag_dmi_csr_rw.1517822665 -covoverwrite' seed=80755381974988456062674487024290964688201257850591926645689148158390683837129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80755381974988456062674487024290964688201257850591926645689148158390683837129 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"9.rv_dm_jtag_dmi_csr_bit_bash.28517664046659461048248470242223425204451070239341716435822120363249684840948","seed":28517664046659461048248470242223425204451070239341716435822120363249684840948,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3195142644 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3195142644 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_dm_jtag_dmi_csr_bit_bash.3195142644 -covoverwrite' seed=28517664046659461048248470242223425204451070239341716435822120363249684840948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28517664046659461048248470242223425204451070239341716435822120363249684840948 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"9.rv_dm_sba_tl_access.61892676955061193113124775503984966610804465408703896846654657057800951066996","seed":61892676955061193113124775503984966610804465408703896846654657057800951066996,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2764992884 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_sba_tl_access.2764992884 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_sba_tl_access.2764992884 -covoverwrite' seed=61892676955061193113124775503984966610804465408703896846654657057800951066996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61892676955061193113124775503984966610804465408703896846654657057800951066996 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"9.rv_dm_delayed_resp_sba_tl_access.60932455588671094409038884428424818326740406024003659563400928646164734813392","seed":60932455588671094409038884428424818326740406024003659563400928646164734813392,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2485920976 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2485920976 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_delayed_resp_sba_tl_access.2485920976 -covoverwrite' seed=60932455588671094409038884428424818326740406024003659563400928646164734813392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60932455588671094409038884428424818326740406024003659563400928646164734813392 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"9.rv_dm_bad_sba_tl_access.41964595222818406208026608005738158671637083270714503262354940069093811012505","seed":41964595222818406208026608005738158671637083270714503262354940069093811012505,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1744159641 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_bad_sba_tl_access.1744159641 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_bad_sba_tl_access.1744159641 -covoverwrite' seed=41964595222818406208026608005738158671637083270714503262354940069093811012505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41964595222818406208026608005738158671637083270714503262354940069093811012505 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"9.rv_dm_autoincr_sba_tl_access.1394510898195890171396242109981382009912670652025095003008813772531254974745","seed":1394510898195890171396242109981382009912670652025095003008813772531254974745,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2070698265 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_autoincr_sba_tl_access.2070698265 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_autoincr_sba_tl_access.2070698265 -covoverwrite' seed=1394510898195890171396242109981382009912670652025095003008813772531254974745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1394510898195890171396242109981382009912670652025095003008813772531254974745 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tap_fsm_rand_reset","qual_name":"9.rv_dm_tap_fsm_rand_reset.54171098230152166352263289030787145531559792566867178964814955816641204712835","seed":54171098230152166352263289030787145531559792566867178964814955816641204712835,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tap_fsm_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2246178179 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2246178179 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_dm_tap_fsm_rand_reset.2246178179 -covoverwrite' seed=54171098230152166352263289030787145531559792566867178964814955816641204712835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54171098230152166352263289030787145531559792566867178964814955816641204712835 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_buffered_enable","qual_name":"9.rv_dm_buffered_enable.88251841447975333334678019779160624631474683178836457997549223946744379069462","seed":88251841447975333334678019779160624631474683178836457997549223946744379069462,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_buffered_enable/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=719705110 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_buffered_enable.719705110 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_buffered_enable.719705110 -covoverwrite' seed=88251841447975333334678019779160624631474683178836457997549223946744379069462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88251841447975333334678019779160624631474683178836457997549223946744379069462 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"9.rv_dm_stress_all_with_rand_reset.64510116424265542353550370060898698959231614067914746457247329279053980587826","seed":64510116424265542353550370060898698959231614067914746457247329279053980587826,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=999905074 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_stress_all_with_rand_reset.999905074 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_stress_all_with_rand_reset.999905074 -covoverwrite' seed=64510116424265542353550370060898698959231614067914746457247329279053980587826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64510116424265542353550370060898698959231614067914746457247329279053980587826 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"9.rv_dm_tl_errors.111515251430885475078130297566070091339388176348042019482161871248177350055888","seed":111515251430885475078130297566070091339388176348042019482161871248177350055888,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1548490704 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/9.rv_dm_tl_errors.1548490704 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_dm_tl_errors.1548490704 -covoverwrite' seed=111515251430885475078130297566070091339388176348042019482161871248177350055888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111515251430885475078130297566070091339388176348042019482161871248177350055888 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"9.rv_dm_tl_intg_err.111794032915687986248557343261680831625746350649494385770404055638554832424875","seed":111794032915687986248557343261680831625746350649494385770404055638554832424875,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1621774251 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1621774251 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_dm_tl_intg_err.1621774251 -covoverwrite' seed=111794032915687986248557343261680831625746350649494385770404055638554832424875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111794032915687986248557343261680831625746350649494385770404055638554832424875 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_alert_test","qual_name":"9.rv_dm_alert_test.45624298994305292083436861615369043933175533241515339518488306820302051127579","seed":45624298994305292083436861615369043933175533241515339518488306820302051127579,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_alert_test/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=587378971 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/9.rv_dm_alert_test.587378971 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 9.rv_dm_alert_test.587378971 -covoverwrite' seed=45624298994305292083436861615369043933175533241515339518488306820302051127579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45624298994305292083436861615369043933175533241515339518488306820302051127579 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"10.rv_dm_jtag_dtm_csr_rw.108409267601250064030588814007792547255608055493235460380003520554850665511687","seed":108409267601250064030588814007792547255608055493235460380003520554850665511687,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3752999687 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3752999687 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_dm_jtag_dtm_csr_rw.3752999687 -covoverwrite' seed=108409267601250064030588814007792547255608055493235460380003520554850665511687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108409267601250064030588814007792547255608055493235460380003520554850665511687 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"10.rv_dm_jtag_dmi_csr_rw.80784052493613858990053398563471701608097252148325934209289044048206255218530","seed":80784052493613858990053398563471701608097252148325934209289044048206255218530,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3713654626 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3713654626 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_dm_jtag_dmi_csr_rw.3713654626 -covoverwrite' seed=80784052493613858990053398563471701608097252148325934209289044048206255218530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80784052493613858990053398563471701608097252148325934209289044048206255218530 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"10.rv_dm_jtag_dmi_csr_bit_bash.30690386291164965304149667449256359711841607090372760672725005966253527997746","seed":30690386291164965304149667449256359711841607090372760672725005966253527997746,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2959154482 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2959154482 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_dm_jtag_dmi_csr_bit_bash.2959154482 -covoverwrite' seed=30690386291164965304149667449256359711841607090372760672725005966253527997746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30690386291164965304149667449256359711841607090372760672725005966253527997746 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"10.rv_dm_sba_tl_access.33599118193070161255162548339697396888346456231976973591093804769276748870156","seed":33599118193070161255162548339697396888346456231976973591093804769276748870156,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2725753356 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/10.rv_dm_sba_tl_access.2725753356 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 10.rv_dm_sba_tl_access.2725753356 -covoverwrite' seed=33599118193070161255162548339697396888346456231976973591093804769276748870156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33599118193070161255162548339697396888346456231976973591093804769276748870156 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"10.rv_dm_delayed_resp_sba_tl_access.105948416146984939071669136730917107571074213558295757652145688169388153162568","seed":105948416146984939071669136730917107571074213558295757652145688169388153162568,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1380895560 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1380895560 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 10.rv_dm_delayed_resp_sba_tl_access.1380895560 -covoverwrite' seed=105948416146984939071669136730917107571074213558295757652145688169388153162568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105948416146984939071669136730917107571074213558295757652145688169388153162568 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"10.rv_dm_bad_sba_tl_access.9548545099540823096156278021283577439318711635431961807882322385649901598839","seed":9548545099540823096156278021283577439318711635431961807882322385649901598839,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2566486135 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/10.rv_dm_bad_sba_tl_access.2566486135 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 10.rv_dm_bad_sba_tl_access.2566486135 -covoverwrite' seed=9548545099540823096156278021283577439318711635431961807882322385649901598839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9548545099540823096156278021283577439318711635431961807882322385649901598839 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"10.rv_dm_autoincr_sba_tl_access.79091337451502509722711411535121758823604675914743529824888740029655270717302","seed":79091337451502509722711411535121758823604675914743529824888740029655270717302,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3028973430 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/10.rv_dm_autoincr_sba_tl_access.3028973430 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 10.rv_dm_autoincr_sba_tl_access.3028973430 -covoverwrite' seed=79091337451502509722711411535121758823604675914743529824888740029655270717302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79091337451502509722711411535121758823604675914743529824888740029655270717302 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"10.rv_dm_stress_all_with_rand_reset.102053799347468707023317873569859524243491595596238996752670089116741165386885","seed":102053799347468707023317873569859524243491595596238996752670089116741165386885,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1449921669 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/10.rv_dm_stress_all_with_rand_reset.1449921669 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 10.rv_dm_stress_all_with_rand_reset.1449921669 -covoverwrite' seed=102053799347468707023317873569859524243491595596238996752670089116741165386885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102053799347468707023317873569859524243491595596238996752670089116741165386885 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"10.rv_dm_tl_errors.5757738291446662738750438991306927052139380606994839601119804658206815220845","seed":5757738291446662738750438991306927052139380606994839601119804658206815220845,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2733569133 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/10.rv_dm_tl_errors.2733569133 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_dm_tl_errors.2733569133 -covoverwrite' seed=5757738291446662738750438991306927052139380606994839601119804658206815220845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5757738291446662738750438991306927052139380606994839601119804658206815220845 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"10.rv_dm_tl_intg_err.8296490689856608646283257209947010708856678476564563643913914572787597887692","seed":8296490689856608646283257209947010708856678476564563643913914572787597887692,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=679921868 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/10.rv_dm_tl_intg_err.679921868 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_dm_tl_intg_err.679921868 -covoverwrite' seed=8296490689856608646283257209947010708856678476564563643913914572787597887692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8296490689856608646283257209947010708856678476564563643913914572787597887692 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"11.rv_dm_jtag_dtm_csr_rw.102511305569863862973772909356817230226870551745198965079419552748551382918689","seed":102511305569863862973772909356817230226870551745198965079419552748551382918689,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1079404065 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1079404065 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_dm_jtag_dtm_csr_rw.1079404065 -covoverwrite' seed=102511305569863862973772909356817230226870551745198965079419552748551382918689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102511305569863862973772909356817230226870551745198965079419552748551382918689 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"11.rv_dm_jtag_dmi_csr_rw.91077362814423480149575320682105264959405520322995088000554948575822073740043","seed":91077362814423480149575320682105264959405520322995088000554948575822073740043,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=60996363 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.60996363 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_dm_jtag_dmi_csr_rw.60996363 -covoverwrite' seed=91077362814423480149575320682105264959405520322995088000554948575822073740043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91077362814423480149575320682105264959405520322995088000554948575822073740043 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"11.rv_dm_jtag_dmi_csr_bit_bash.37786809506788639695894807726426543843036140148566534272220420698633467226568","seed":37786809506788639695894807726426543843036140148566534272220420698633467226568,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3342756296 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3342756296 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_dm_jtag_dmi_csr_bit_bash.3342756296 -covoverwrite' seed=37786809506788639695894807726426543843036140148566534272220420698633467226568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37786809506788639695894807726426543843036140148566534272220420698633467226568 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"11.rv_dm_sba_tl_access.48540862029759633161485306466479580524407660527610935201393743628585733081469","seed":48540862029759633161485306466479580524407660527610935201393743628585733081469,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2627094909 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/11.rv_dm_sba_tl_access.2627094909 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 11.rv_dm_sba_tl_access.2627094909 -covoverwrite' seed=48540862029759633161485306466479580524407660527610935201393743628585733081469 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48540862029759633161485306466479580524407660527610935201393743628585733081469 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"11.rv_dm_delayed_resp_sba_tl_access.33591942015264177570117604352593872949894292451893155749447942267589876093684","seed":33591942015264177570117604352593872949894292451893155749447942267589876093684,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2527695604 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2527695604 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 11.rv_dm_delayed_resp_sba_tl_access.2527695604 -covoverwrite' seed=33591942015264177570117604352593872949894292451893155749447942267589876093684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33591942015264177570117604352593872949894292451893155749447942267589876093684 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"11.rv_dm_bad_sba_tl_access.3383477836861083595913422188397134682427856913895128464894685892897895782233","seed":3383477836861083595913422188397134682427856913895128464894685892897895782233,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3460470617 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/11.rv_dm_bad_sba_tl_access.3460470617 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 11.rv_dm_bad_sba_tl_access.3460470617 -covoverwrite' seed=3383477836861083595913422188397134682427856913895128464894685892897895782233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3383477836861083595913422188397134682427856913895128464894685892897895782233 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"11.rv_dm_autoincr_sba_tl_access.44813369374458964379147932233343247031133209992169814069656756493294487797306","seed":44813369374458964379147932233343247031133209992169814069656756493294487797306,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3024682554 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/11.rv_dm_autoincr_sba_tl_access.3024682554 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 11.rv_dm_autoincr_sba_tl_access.3024682554 -covoverwrite' seed=44813369374458964379147932233343247031133209992169814069656756493294487797306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44813369374458964379147932233343247031133209992169814069656756493294487797306 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"11.rv_dm_stress_all_with_rand_reset.62535975860016345987579130048772074378163251072970237479614627151540253970986","seed":62535975860016345987579130048772074378163251072970237479614627151540253970986,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3982840362 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/11.rv_dm_stress_all_with_rand_reset.3982840362 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 11.rv_dm_stress_all_with_rand_reset.3982840362 -covoverwrite' seed=62535975860016345987579130048772074378163251072970237479614627151540253970986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62535975860016345987579130048772074378163251072970237479614627151540253970986 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"11.rv_dm_tl_errors.20249058279806573756094837100755689045513951446432783160386695064225462989079","seed":20249058279806573756094837100755689045513951446432783160386695064225462989079,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4137005335 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/11.rv_dm_tl_errors.4137005335 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_dm_tl_errors.4137005335 -covoverwrite' seed=20249058279806573756094837100755689045513951446432783160386695064225462989079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20249058279806573756094837100755689045513951446432783160386695064225462989079 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"11.rv_dm_tl_intg_err.17968403549527454607975043651454197625645898401506200729170233086425189377248","seed":17968403549527454607975043651454197625645898401506200729170233086425189377248,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=493413600 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/11.rv_dm_tl_intg_err.493413600 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_dm_tl_intg_err.493413600 -covoverwrite' seed=17968403549527454607975043651454197625645898401506200729170233086425189377248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17968403549527454607975043651454197625645898401506200729170233086425189377248 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"12.rv_dm_jtag_dtm_csr_rw.58663857989711759972453694177327058875249706243595338678922307925685389805071","seed":58663857989711759972453694177327058875249706243595338678922307925685389805071,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2328413711 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2328413711 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_dm_jtag_dtm_csr_rw.2328413711 -covoverwrite' seed=58663857989711759972453694177327058875249706243595338678922307925685389805071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58663857989711759972453694177327058875249706243595338678922307925685389805071 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"12.rv_dm_jtag_dmi_csr_rw.24538113749083970398669230370890548038283288420572286903077952205992258933168","seed":24538113749083970398669230370890548038283288420572286903077952205992258933168,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4010512816 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4010512816 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_dm_jtag_dmi_csr_rw.4010512816 -covoverwrite' seed=24538113749083970398669230370890548038283288420572286903077952205992258933168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24538113749083970398669230370890548038283288420572286903077952205992258933168 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"12.rv_dm_jtag_dmi_csr_bit_bash.54459679918854383536700104125366147967660917626871924045703779096178767747591","seed":54459679918854383536700104125366147967660917626871924045703779096178767747591,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2265766407 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2265766407 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_dm_jtag_dmi_csr_bit_bash.2265766407 -covoverwrite' seed=54459679918854383536700104125366147967660917626871924045703779096178767747591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54459679918854383536700104125366147967660917626871924045703779096178767747591 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"12.rv_dm_sba_tl_access.88032072528461282305085063122338005516958498018347277515308485687195863908350","seed":88032072528461282305085063122338005516958498018347277515308485687195863908350,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3667689470 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/12.rv_dm_sba_tl_access.3667689470 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 12.rv_dm_sba_tl_access.3667689470 -covoverwrite' seed=88032072528461282305085063122338005516958498018347277515308485687195863908350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88032072528461282305085063122338005516958498018347277515308485687195863908350 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"12.rv_dm_delayed_resp_sba_tl_access.55000248519684177177828574531824856362032213470763293409832014068737111174842","seed":55000248519684177177828574531824856362032213470763293409832014068737111174842,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=227749562 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.227749562 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 12.rv_dm_delayed_resp_sba_tl_access.227749562 -covoverwrite' seed=55000248519684177177828574531824856362032213470763293409832014068737111174842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55000248519684177177828574531824856362032213470763293409832014068737111174842 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"12.rv_dm_bad_sba_tl_access.48666319326530727217731688055309204786230166655860527037100345640863398186115","seed":48666319326530727217731688055309204786230166655860527037100345640863398186115,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3521465475 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/12.rv_dm_bad_sba_tl_access.3521465475 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 12.rv_dm_bad_sba_tl_access.3521465475 -covoverwrite' seed=48666319326530727217731688055309204786230166655860527037100345640863398186115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48666319326530727217731688055309204786230166655860527037100345640863398186115 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"12.rv_dm_autoincr_sba_tl_access.73340424750204500418209866468181733803267585958790849462798653845119380288331","seed":73340424750204500418209866468181733803267585958790849462798653845119380288331,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3997233995 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/12.rv_dm_autoincr_sba_tl_access.3997233995 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 12.rv_dm_autoincr_sba_tl_access.3997233995 -covoverwrite' seed=73340424750204500418209866468181733803267585958790849462798653845119380288331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73340424750204500418209866468181733803267585958790849462798653845119380288331 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"12.rv_dm_stress_all_with_rand_reset.73801087400033640708808489771720260720297851559562992516743300099772168729578","seed":73801087400033640708808489771720260720297851559562992516743300099772168729578,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2600924138 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/12.rv_dm_stress_all_with_rand_reset.2600924138 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 12.rv_dm_stress_all_with_rand_reset.2600924138 -covoverwrite' seed=73801087400033640708808489771720260720297851559562992516743300099772168729578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73801087400033640708808489771720260720297851559562992516743300099772168729578 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"12.rv_dm_tl_errors.77565570216374034864684563433636004267559339841735661444636519138564617751334","seed":77565570216374034864684563433636004267559339841735661444636519138564617751334,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=741296934 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/12.rv_dm_tl_errors.741296934 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_dm_tl_errors.741296934 -covoverwrite' seed=77565570216374034864684563433636004267559339841735661444636519138564617751334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77565570216374034864684563433636004267559339841735661444636519138564617751334 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"12.rv_dm_tl_intg_err.31147096413674470209274035584829023332607292026009900067111079345194037232153","seed":31147096413674470209274035584829023332607292026009900067111079345194037232153,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=494223897 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/12.rv_dm_tl_intg_err.494223897 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_dm_tl_intg_err.494223897 -covoverwrite' seed=31147096413674470209274035584829023332607292026009900067111079345194037232153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31147096413674470209274035584829023332607292026009900067111079345194037232153 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"13.rv_dm_jtag_dtm_csr_rw.18284891140626024160734936909487082621492612429648049498548841412951146040359","seed":18284891140626024160734936909487082621492612429648049498548841412951146040359,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3033074727 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3033074727 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_dm_jtag_dtm_csr_rw.3033074727 -covoverwrite' seed=18284891140626024160734936909487082621492612429648049498548841412951146040359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18284891140626024160734936909487082621492612429648049498548841412951146040359 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"13.rv_dm_jtag_dmi_csr_rw.68956374749682241802366177846612459958170066049887165298928421597604926863445","seed":68956374749682241802366177846612459958170066049887165298928421597604926863445,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2240952405 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2240952405 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_dm_jtag_dmi_csr_rw.2240952405 -covoverwrite' seed=68956374749682241802366177846612459958170066049887165298928421597604926863445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68956374749682241802366177846612459958170066049887165298928421597604926863445 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"13.rv_dm_jtag_dmi_csr_bit_bash.47536348249626397690382690752624446651050324178597363652554803464304510008131","seed":47536348249626397690382690752624446651050324178597363652554803464304510008131,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1022262083 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1022262083 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_dm_jtag_dmi_csr_bit_bash.1022262083 -covoverwrite' seed=47536348249626397690382690752624446651050324178597363652554803464304510008131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47536348249626397690382690752624446651050324178597363652554803464304510008131 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"13.rv_dm_sba_tl_access.75707584620645888878555607270917171638570643964013827815629388309832188461648","seed":75707584620645888878555607270917171638570643964013827815629388309832188461648,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=360088144 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/13.rv_dm_sba_tl_access.360088144 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 13.rv_dm_sba_tl_access.360088144 -covoverwrite' seed=75707584620645888878555607270917171638570643964013827815629388309832188461648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75707584620645888878555607270917171638570643964013827815629388309832188461648 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"13.rv_dm_delayed_resp_sba_tl_access.33229749664583014022320093397217959321454393077130705255613090519294631643882","seed":33229749664583014022320093397217959321454393077130705255613090519294631643882,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2796194538 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2796194538 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 13.rv_dm_delayed_resp_sba_tl_access.2796194538 -covoverwrite' seed=33229749664583014022320093397217959321454393077130705255613090519294631643882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33229749664583014022320093397217959321454393077130705255613090519294631643882 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"13.rv_dm_bad_sba_tl_access.72148252604719781554122339324319723601996154611036767939187210951410841304990","seed":72148252604719781554122339324319723601996154611036767939187210951410841304990,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1576812446 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/13.rv_dm_bad_sba_tl_access.1576812446 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 13.rv_dm_bad_sba_tl_access.1576812446 -covoverwrite' seed=72148252604719781554122339324319723601996154611036767939187210951410841304990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72148252604719781554122339324319723601996154611036767939187210951410841304990 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"13.rv_dm_autoincr_sba_tl_access.2720670843001376455655401652093440251030039068463477861964205151965022694048","seed":2720670843001376455655401652093440251030039068463477861964205151965022694048,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3117853344 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/13.rv_dm_autoincr_sba_tl_access.3117853344 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 13.rv_dm_autoincr_sba_tl_access.3117853344 -covoverwrite' seed=2720670843001376455655401652093440251030039068463477861964205151965022694048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2720670843001376455655401652093440251030039068463477861964205151965022694048 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"13.rv_dm_stress_all_with_rand_reset.16684790002226439144850277656005466838191435379859310100839745993911431583639","seed":16684790002226439144850277656005466838191435379859310100839745993911431583639,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1287116695 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/13.rv_dm_stress_all_with_rand_reset.1287116695 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 13.rv_dm_stress_all_with_rand_reset.1287116695 -covoverwrite' seed=16684790002226439144850277656005466838191435379859310100839745993911431583639 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16684790002226439144850277656005466838191435379859310100839745993911431583639 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"13.rv_dm_tl_errors.21166662648355174493323868453956375915956000664554218339393189986613265115603","seed":21166662648355174493323868453956375915956000664554218339393189986613265115603,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1680026067 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/13.rv_dm_tl_errors.1680026067 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_dm_tl_errors.1680026067 -covoverwrite' seed=21166662648355174493323868453956375915956000664554218339393189986613265115603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21166662648355174493323868453956375915956000664554218339393189986613265115603 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"13.rv_dm_tl_intg_err.55114260437780683810200651685205508188194412175790024255487628307400710200261","seed":55114260437780683810200651685205508188194412175790024255487628307400710200261,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2108726213 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2108726213 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_dm_tl_intg_err.2108726213 -covoverwrite' seed=55114260437780683810200651685205508188194412175790024255487628307400710200261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55114260437780683810200651685205508188194412175790024255487628307400710200261 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"14.rv_dm_jtag_dtm_csr_rw.24251463937331103719163076444570420697907582474194696057197580007462228777491","seed":24251463937331103719163076444570420697907582474194696057197580007462228777491,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=718068243 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.718068243 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_dm_jtag_dtm_csr_rw.718068243 -covoverwrite' seed=24251463937331103719163076444570420697907582474194696057197580007462228777491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24251463937331103719163076444570420697907582474194696057197580007462228777491 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"14.rv_dm_jtag_dmi_csr_rw.32092722065863652679539653514866494647652880586661550595213763664014760628383","seed":32092722065863652679539653514866494647652880586661550595213763664014760628383,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=966938783 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.966938783 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_dm_jtag_dmi_csr_rw.966938783 -covoverwrite' seed=32092722065863652679539653514866494647652880586661550595213763664014760628383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32092722065863652679539653514866494647652880586661550595213763664014760628383 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"14.rv_dm_jtag_dmi_csr_bit_bash.53002895696566710675299441681689313357244087701615173002972964676405027558091","seed":53002895696566710675299441681689313357244087701615173002972964676405027558091,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4274934475 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4274934475 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_dm_jtag_dmi_csr_bit_bash.4274934475 -covoverwrite' seed=53002895696566710675299441681689313357244087701615173002972964676405027558091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53002895696566710675299441681689313357244087701615173002972964676405027558091 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"14.rv_dm_sba_tl_access.59702589083584525808735914705617875505357333794215479878747040459527943290774","seed":59702589083584525808735914705617875505357333794215479878747040459527943290774,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2137194390 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/14.rv_dm_sba_tl_access.2137194390 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 14.rv_dm_sba_tl_access.2137194390 -covoverwrite' seed=59702589083584525808735914705617875505357333794215479878747040459527943290774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59702589083584525808735914705617875505357333794215479878747040459527943290774 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"14.rv_dm_delayed_resp_sba_tl_access.19930687532597441852924822121376155380707447428842410960728230643772375302373","seed":19930687532597441852924822121376155380707447428842410960728230643772375302373,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3228958949 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3228958949 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 14.rv_dm_delayed_resp_sba_tl_access.3228958949 -covoverwrite' seed=19930687532597441852924822121376155380707447428842410960728230643772375302373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19930687532597441852924822121376155380707447428842410960728230643772375302373 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"14.rv_dm_bad_sba_tl_access.85760825011993863403623605473624837853446548827557148398457009374635067239588","seed":85760825011993863403623605473624837853446548827557148398457009374635067239588,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3680038052 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/14.rv_dm_bad_sba_tl_access.3680038052 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 14.rv_dm_bad_sba_tl_access.3680038052 -covoverwrite' seed=85760825011993863403623605473624837853446548827557148398457009374635067239588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85760825011993863403623605473624837853446548827557148398457009374635067239588 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"14.rv_dm_autoincr_sba_tl_access.15171624828594331119849377142267041716112607249108126124329871158520642071401","seed":15171624828594331119849377142267041716112607249108126124329871158520642071401,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1760619369 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/14.rv_dm_autoincr_sba_tl_access.1760619369 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 14.rv_dm_autoincr_sba_tl_access.1760619369 -covoverwrite' seed=15171624828594331119849377142267041716112607249108126124329871158520642071401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15171624828594331119849377142267041716112607249108126124329871158520642071401 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"14.rv_dm_stress_all_with_rand_reset.7581000177525476055022824434816800959440113428366317205140018962979375480179","seed":7581000177525476055022824434816800959440113428366317205140018962979375480179,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2405367155 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/14.rv_dm_stress_all_with_rand_reset.2405367155 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 14.rv_dm_stress_all_with_rand_reset.2405367155 -covoverwrite' seed=7581000177525476055022824434816800959440113428366317205140018962979375480179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7581000177525476055022824434816800959440113428366317205140018962979375480179 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"14.rv_dm_tl_errors.59028422272768446919756572229719382515380131507214342080048682242137118162474","seed":59028422272768446919756572229719382515380131507214342080048682242137118162474,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2759540266 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/14.rv_dm_tl_errors.2759540266 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_dm_tl_errors.2759540266 -covoverwrite' seed=59028422272768446919756572229719382515380131507214342080048682242137118162474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59028422272768446919756572229719382515380131507214342080048682242137118162474 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"14.rv_dm_tl_intg_err.46820476960648348384899187908952418667978101562127564498073593721919991860154","seed":46820476960648348384899187908952418667978101562127564498073593721919991860154,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3812510650 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3812510650 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_dm_tl_intg_err.3812510650 -covoverwrite' seed=46820476960648348384899187908952418667978101562127564498073593721919991860154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46820476960648348384899187908952418667978101562127564498073593721919991860154 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/14.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"15.rv_dm_jtag_dtm_csr_rw.36268699115932202991096628370076455841572235823890557204131343684419507999732","seed":36268699115932202991096628370076455841572235823890557204131343684419507999732,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1212699636 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1212699636 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_dm_jtag_dtm_csr_rw.1212699636 -covoverwrite' seed=36268699115932202991096628370076455841572235823890557204131343684419507999732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36268699115932202991096628370076455841572235823890557204131343684419507999732 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"15.rv_dm_jtag_dmi_csr_rw.90756209213420811820276559987312823222281837583429074535467117491981486057791","seed":90756209213420811820276559987312823222281837583429074535467117491981486057791,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1513810239 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1513810239 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_dm_jtag_dmi_csr_rw.1513810239 -covoverwrite' seed=90756209213420811820276559987312823222281837583429074535467117491981486057791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90756209213420811820276559987312823222281837583429074535467117491981486057791 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"15.rv_dm_jtag_dmi_csr_bit_bash.87051368703693748901910504849399020661851716458945425368826586223444413754013","seed":87051368703693748901910504849399020661851716458945425368826586223444413754013,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=854698653 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.854698653 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_dm_jtag_dmi_csr_bit_bash.854698653 -covoverwrite' seed=87051368703693748901910504849399020661851716458945425368826586223444413754013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87051368703693748901910504849399020661851716458945425368826586223444413754013 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"15.rv_dm_sba_tl_access.26443263299657393149583127912592269857701056135548248907341780763878614098807","seed":26443263299657393149583127912592269857701056135548248907341780763878614098807,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2001986423 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/15.rv_dm_sba_tl_access.2001986423 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 15.rv_dm_sba_tl_access.2001986423 -covoverwrite' seed=26443263299657393149583127912592269857701056135548248907341780763878614098807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26443263299657393149583127912592269857701056135548248907341780763878614098807 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"15.rv_dm_delayed_resp_sba_tl_access.27726955080810766678517237271936363661566689748334623937381503793547110096092","seed":27726955080810766678517237271936363661566689748334623937381503793547110096092,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1310039260 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1310039260 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 15.rv_dm_delayed_resp_sba_tl_access.1310039260 -covoverwrite' seed=27726955080810766678517237271936363661566689748334623937381503793547110096092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27726955080810766678517237271936363661566689748334623937381503793547110096092 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"15.rv_dm_bad_sba_tl_access.13930577309304667787034167304269118522810761484848659013956014518536070792617","seed":13930577309304667787034167304269118522810761484848659013956014518536070792617,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1941472681 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/15.rv_dm_bad_sba_tl_access.1941472681 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 15.rv_dm_bad_sba_tl_access.1941472681 -covoverwrite' seed=13930577309304667787034167304269118522810761484848659013956014518536070792617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13930577309304667787034167304269118522810761484848659013956014518536070792617 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"15.rv_dm_autoincr_sba_tl_access.99289546816892048534155589496802374874972274621727493201153249850593737200102","seed":99289546816892048534155589496802374874972274621727493201153249850593737200102,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2315538918 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/15.rv_dm_autoincr_sba_tl_access.2315538918 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 15.rv_dm_autoincr_sba_tl_access.2315538918 -covoverwrite' seed=99289546816892048534155589496802374874972274621727493201153249850593737200102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99289546816892048534155589496802374874972274621727493201153249850593737200102 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"15.rv_dm_stress_all_with_rand_reset.61908054248915067534526955359948255390688103233327630782060410985705442734709","seed":61908054248915067534526955359948255390688103233327630782060410985705442734709,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1792897653 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/15.rv_dm_stress_all_with_rand_reset.1792897653 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 15.rv_dm_stress_all_with_rand_reset.1792897653 -covoverwrite' seed=61908054248915067534526955359948255390688103233327630782060410985705442734709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61908054248915067534526955359948255390688103233327630782060410985705442734709 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"15.rv_dm_tl_errors.44788680759780660879161318230040600631197447312062563503325371674041013613692","seed":44788680759780660879161318230040600631197447312062563503325371674041013613692,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1680716924 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/15.rv_dm_tl_errors.1680716924 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_dm_tl_errors.1680716924 -covoverwrite' seed=44788680759780660879161318230040600631197447312062563503325371674041013613692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44788680759780660879161318230040600631197447312062563503325371674041013613692 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"15.rv_dm_tl_intg_err.27738979706457979571862427575254572797614910024046623397413082552279692614526","seed":27738979706457979571862427575254572797614910024046623397413082552279692614526,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=871242622 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/15.rv_dm_tl_intg_err.871242622 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_dm_tl_intg_err.871242622 -covoverwrite' seed=27738979706457979571862427575254572797614910024046623397413082552279692614526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27738979706457979571862427575254572797614910024046623397413082552279692614526 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"16.rv_dm_jtag_dtm_csr_rw.63130549574086167339080891184950199325139361246087565007325380902548155730832","seed":63130549574086167339080891184950199325139361246087565007325380902548155730832,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3123776400 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3123776400 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_dm_jtag_dtm_csr_rw.3123776400 -covoverwrite' seed=63130549574086167339080891184950199325139361246087565007325380902548155730832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63130549574086167339080891184950199325139361246087565007325380902548155730832 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"16.rv_dm_jtag_dmi_csr_rw.60738834557306384771604892757881640180301935589529197122964314663751116190956","seed":60738834557306384771604892757881640180301935589529197122964314663751116190956,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2932405484 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2932405484 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_dm_jtag_dmi_csr_rw.2932405484 -covoverwrite' seed=60738834557306384771604892757881640180301935589529197122964314663751116190956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60738834557306384771604892757881640180301935589529197122964314663751116190956 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"16.rv_dm_jtag_dmi_csr_bit_bash.48705703004878239978998093509305885704191094709786207080405170317062749869568","seed":48705703004878239978998093509305885704191094709786207080405170317062749869568,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2056836608 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2056836608 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_dm_jtag_dmi_csr_bit_bash.2056836608 -covoverwrite' seed=48705703004878239978998093509305885704191094709786207080405170317062749869568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48705703004878239978998093509305885704191094709786207080405170317062749869568 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"16.rv_dm_sba_tl_access.48493074908108528633015044769011677651225791112356561787846852128761673213478","seed":48493074908108528633015044769011677651225791112356561787846852128761673213478,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=298116646 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/16.rv_dm_sba_tl_access.298116646 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 16.rv_dm_sba_tl_access.298116646 -covoverwrite' seed=48493074908108528633015044769011677651225791112356561787846852128761673213478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48493074908108528633015044769011677651225791112356561787846852128761673213478 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"16.rv_dm_delayed_resp_sba_tl_access.73158811317193713640304832005647015385426581941974015207572148528961507863702","seed":73158811317193713640304832005647015385426581941974015207572148528961507863702,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=458796182 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.458796182 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 16.rv_dm_delayed_resp_sba_tl_access.458796182 -covoverwrite' seed=73158811317193713640304832005647015385426581941974015207572148528961507863702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73158811317193713640304832005647015385426581941974015207572148528961507863702 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"16.rv_dm_bad_sba_tl_access.60015697599257184439984940882294892309697659342724092250543218997220990957994","seed":60015697599257184439984940882294892309697659342724092250543218997220990957994,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3713186218 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/16.rv_dm_bad_sba_tl_access.3713186218 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 16.rv_dm_bad_sba_tl_access.3713186218 -covoverwrite' seed=60015697599257184439984940882294892309697659342724092250543218997220990957994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60015697599257184439984940882294892309697659342724092250543218997220990957994 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"16.rv_dm_autoincr_sba_tl_access.470875472502750839876368466759920868165954168249006321748148030753133579563","seed":470875472502750839876368466759920868165954168249006321748148030753133579563,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=892095787 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/16.rv_dm_autoincr_sba_tl_access.892095787 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 16.rv_dm_autoincr_sba_tl_access.892095787 -covoverwrite' seed=470875472502750839876368466759920868165954168249006321748148030753133579563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=470875472502750839876368466759920868165954168249006321748148030753133579563 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"16.rv_dm_stress_all_with_rand_reset.81395577449111192986274194096054267995390854826378469476778306670486783338279","seed":81395577449111192986274194096054267995390854826378469476778306670486783338279,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2151229223 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/16.rv_dm_stress_all_with_rand_reset.2151229223 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 16.rv_dm_stress_all_with_rand_reset.2151229223 -covoverwrite' seed=81395577449111192986274194096054267995390854826378469476778306670486783338279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81395577449111192986274194096054267995390854826378469476778306670486783338279 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"16.rv_dm_tl_errors.68098390316386054599682955469370069492566237091318017336856775346149270529273","seed":68098390316386054599682955469370069492566237091318017336856775346149270529273,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2258412793 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/16.rv_dm_tl_errors.2258412793 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_dm_tl_errors.2258412793 -covoverwrite' seed=68098390316386054599682955469370069492566237091318017336856775346149270529273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68098390316386054599682955469370069492566237091318017336856775346149270529273 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"16.rv_dm_tl_intg_err.19077318939339952292724682176932609381715375283162593595476478278171807986597","seed":19077318939339952292724682176932609381715375283162593595476478278171807986597,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3275764645 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3275764645 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_dm_tl_intg_err.3275764645 -covoverwrite' seed=19077318939339952292724682176932609381715375283162593595476478278171807986597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19077318939339952292724682176932609381715375283162593595476478278171807986597 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"17.rv_dm_jtag_dtm_csr_rw.68874194525296355275035509919186693121668258741611219034572903284710372194735","seed":68874194525296355275035509919186693121668258741611219034572903284710372194735,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3430332847 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3430332847 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_dm_jtag_dtm_csr_rw.3430332847 -covoverwrite' seed=68874194525296355275035509919186693121668258741611219034572903284710372194735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68874194525296355275035509919186693121668258741611219034572903284710372194735 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"17.rv_dm_jtag_dmi_csr_rw.50882803636698712381763162246339197964902908735187044539842235861934876940447","seed":50882803636698712381763162246339197964902908735187044539842235861934876940447,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1244158111 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1244158111 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_dm_jtag_dmi_csr_rw.1244158111 -covoverwrite' seed=50882803636698712381763162246339197964902908735187044539842235861934876940447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50882803636698712381763162246339197964902908735187044539842235861934876940447 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"17.rv_dm_jtag_dmi_csr_bit_bash.33523569678622404784399333502827281652134835627167787166203214771678710308579","seed":33523569678622404784399333502827281652134835627167787166203214771678710308579,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1415814883 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1415814883 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_dm_jtag_dmi_csr_bit_bash.1415814883 -covoverwrite' seed=33523569678622404784399333502827281652134835627167787166203214771678710308579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33523569678622404784399333502827281652134835627167787166203214771678710308579 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"17.rv_dm_sba_tl_access.60973251742908733624367983083191680578537689413604723835032274848581744510476","seed":60973251742908733624367983083191680578537689413604723835032274848581744510476,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2504443404 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/17.rv_dm_sba_tl_access.2504443404 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 17.rv_dm_sba_tl_access.2504443404 -covoverwrite' seed=60973251742908733624367983083191680578537689413604723835032274848581744510476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60973251742908733624367983083191680578537689413604723835032274848581744510476 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"17.rv_dm_delayed_resp_sba_tl_access.83513042381390125568986954052479820395082601009433966794044112018763849896712","seed":83513042381390125568986954052479820395082601009433966794044112018763849896712,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1390646024 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1390646024 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 17.rv_dm_delayed_resp_sba_tl_access.1390646024 -covoverwrite' seed=83513042381390125568986954052479820395082601009433966794044112018763849896712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83513042381390125568986954052479820395082601009433966794044112018763849896712 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"17.rv_dm_bad_sba_tl_access.52443608794699375784944221350098109005478444692916692927199903529531587091429","seed":52443608794699375784944221350098109005478444692916692927199903529531587091429,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4268678117 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/17.rv_dm_bad_sba_tl_access.4268678117 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 17.rv_dm_bad_sba_tl_access.4268678117 -covoverwrite' seed=52443608794699375784944221350098109005478444692916692927199903529531587091429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52443608794699375784944221350098109005478444692916692927199903529531587091429 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"17.rv_dm_autoincr_sba_tl_access.50276897365317697165938913637673325682334656801922140480271799463117534208243","seed":50276897365317697165938913637673325682334656801922140480271799463117534208243,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3062046963 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/17.rv_dm_autoincr_sba_tl_access.3062046963 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 17.rv_dm_autoincr_sba_tl_access.3062046963 -covoverwrite' seed=50276897365317697165938913637673325682334656801922140480271799463117534208243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50276897365317697165938913637673325682334656801922140480271799463117534208243 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"17.rv_dm_stress_all_with_rand_reset.18870431120509759069707678313325425575857629411354839653742346272483222545897","seed":18870431120509759069707678313325425575857629411354839653742346272483222545897,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1727063529 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/17.rv_dm_stress_all_with_rand_reset.1727063529 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 17.rv_dm_stress_all_with_rand_reset.1727063529 -covoverwrite' seed=18870431120509759069707678313325425575857629411354839653742346272483222545897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18870431120509759069707678313325425575857629411354839653742346272483222545897 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"17.rv_dm_tl_errors.77377849840648099284569130739850835904205353170054080727065468713843991032065","seed":77377849840648099284569130739850835904205353170054080727065468713843991032065,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1965601025 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/17.rv_dm_tl_errors.1965601025 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_dm_tl_errors.1965601025 -covoverwrite' seed=77377849840648099284569130739850835904205353170054080727065468713843991032065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77377849840648099284569130739850835904205353170054080727065468713843991032065 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"17.rv_dm_tl_intg_err.79808813917392355571073762084236008358908514745979721470023919496504154077288","seed":79808813917392355571073762084236008358908514745979721470023919496504154077288,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2467117160 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2467117160 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_dm_tl_intg_err.2467117160 -covoverwrite' seed=79808813917392355571073762084236008358908514745979721470023919496504154077288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79808813917392355571073762084236008358908514745979721470023919496504154077288 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"18.rv_dm_jtag_dtm_csr_rw.78761279707097130501172317007316065390863512088546714175748297180038167433003","seed":78761279707097130501172317007316065390863512088546714175748297180038167433003,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3000930091 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3000930091 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_dm_jtag_dtm_csr_rw.3000930091 -covoverwrite' seed=78761279707097130501172317007316065390863512088546714175748297180038167433003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78761279707097130501172317007316065390863512088546714175748297180038167433003 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"18.rv_dm_jtag_dmi_csr_rw.66265237112602729328138568844649921583528340121703551992062969290650837428480","seed":66265237112602729328138568844649921583528340121703551992062969290650837428480,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=880650496 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.880650496 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_dm_jtag_dmi_csr_rw.880650496 -covoverwrite' seed=66265237112602729328138568844649921583528340121703551992062969290650837428480 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66265237112602729328138568844649921583528340121703551992062969290650837428480 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"18.rv_dm_jtag_dmi_csr_bit_bash.55426069283585969840703803941246569866271897575814797151625799725921915949533","seed":55426069283585969840703803941246569866271897575814797151625799725921915949533,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3455898077 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3455898077 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_dm_jtag_dmi_csr_bit_bash.3455898077 -covoverwrite' seed=55426069283585969840703803941246569866271897575814797151625799725921915949533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55426069283585969840703803941246569866271897575814797151625799725921915949533 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"18.rv_dm_sba_tl_access.109948070566963157960866591719446659042956227479372976217554173774775493674689","seed":109948070566963157960866591719446659042956227479372976217554173774775493674689,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2017543873 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/18.rv_dm_sba_tl_access.2017543873 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 18.rv_dm_sba_tl_access.2017543873 -covoverwrite' seed=109948070566963157960866591719446659042956227479372976217554173774775493674689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109948070566963157960866591719446659042956227479372976217554173774775493674689 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"18.rv_dm_delayed_resp_sba_tl_access.23618240349034226094791150589798135546705044747046089411433474041406424207126","seed":23618240349034226094791150589798135546705044747046089411433474041406424207126,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3133263638 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3133263638 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 18.rv_dm_delayed_resp_sba_tl_access.3133263638 -covoverwrite' seed=23618240349034226094791150589798135546705044747046089411433474041406424207126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23618240349034226094791150589798135546705044747046089411433474041406424207126 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"18.rv_dm_bad_sba_tl_access.137558442371055445264345231458402365240934315343659953506716571183425746608","seed":137558442371055445264345231458402365240934315343659953506716571183425746608,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2225567408 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/18.rv_dm_bad_sba_tl_access.2225567408 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 18.rv_dm_bad_sba_tl_access.2225567408 -covoverwrite' seed=137558442371055445264345231458402365240934315343659953506716571183425746608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=137558442371055445264345231458402365240934315343659953506716571183425746608 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"18.rv_dm_autoincr_sba_tl_access.38510234591005402620076532019501783906055746215746887423071954200858734941326","seed":38510234591005402620076532019501783906055746215746887423071954200858734941326,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=190895246 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/18.rv_dm_autoincr_sba_tl_access.190895246 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 18.rv_dm_autoincr_sba_tl_access.190895246 -covoverwrite' seed=38510234591005402620076532019501783906055746215746887423071954200858734941326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38510234591005402620076532019501783906055746215746887423071954200858734941326 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"18.rv_dm_stress_all_with_rand_reset.54150878748693890876810342276753980692895290071692518720363047492894021239262","seed":54150878748693890876810342276753980692895290071692518720363047492894021239262,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=944357854 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/18.rv_dm_stress_all_with_rand_reset.944357854 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 18.rv_dm_stress_all_with_rand_reset.944357854 -covoverwrite' seed=54150878748693890876810342276753980692895290071692518720363047492894021239262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54150878748693890876810342276753980692895290071692518720363047492894021239262 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"18.rv_dm_tl_errors.14170322567165221801298598185371011399459223625576469067025077156039313973937","seed":14170322567165221801298598185371011399459223625576469067025077156039313973937,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=490332849 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/18.rv_dm_tl_errors.490332849 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_dm_tl_errors.490332849 -covoverwrite' seed=14170322567165221801298598185371011399459223625576469067025077156039313973937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14170322567165221801298598185371011399459223625576469067025077156039313973937 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"18.rv_dm_tl_intg_err.58516619266410264277498306298652359814280445497313936099208593051004553613601","seed":58516619266410264277498306298652359814280445497313936099208593051004553613601,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3308998945 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3308998945 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_dm_tl_intg_err.3308998945 -covoverwrite' seed=58516619266410264277498306298652359814280445497313936099208593051004553613601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58516619266410264277498306298652359814280445497313936099208593051004553613601 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dtm_csr_rw","qual_name":"19.rv_dm_jtag_dtm_csr_rw.90659598703156712591355548135855008451289220352484485587643710055416039357245","seed":90659598703156712591355548135855008451289220352484485587643710055416039357245,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dtm_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=434780989 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.434780989 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_dm_jtag_dtm_csr_rw.434780989 -covoverwrite' seed=90659598703156712591355548135855008451289220352484485587643710055416039357245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90659598703156712591355548135855008451289220352484485587643710055416039357245 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_rw","qual_name":"19.rv_dm_jtag_dmi_csr_rw.37752270246680913763653019975020974801248591352584344582929877754524998161792","seed":37752270246680913763653019975020974801248591352584344582929877754524998161792,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dmi_csr_rw/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=807785856 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.807785856 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_dm_jtag_dmi_csr_rw.807785856 -covoverwrite' seed=37752270246680913763653019975020974801248591352584344582929877754524998161792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37752270246680913763653019975020974801248591352584344582929877754524998161792 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_jtag_dmi_csr_bit_bash","qual_name":"19.rv_dm_jtag_dmi_csr_bit_bash.105065861693474417311509321312695361449568231991743660646738111297813826593098","seed":105065861693474417311509321312695361449568231991743660646738111297813826593098,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=594633034 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.594633034 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_dm_jtag_dmi_csr_bit_bash.594633034 -covoverwrite' seed=105065861693474417311509321312695361449568231991743660646738111297813826593098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105065861693474417311509321312695361449568231991743660646738111297813826593098 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"19.rv_dm_sba_tl_access.73014852210106539810759547980399869339358748258576279704678310835552079129933","seed":73014852210106539810759547980399869339358748258576279704678310835552079129933,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=722808141 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/19.rv_dm_sba_tl_access.722808141 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 19.rv_dm_sba_tl_access.722808141 -covoverwrite' seed=73014852210106539810759547980399869339358748258576279704678310835552079129933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73014852210106539810759547980399869339358748258576279704678310835552079129933 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"19.rv_dm_delayed_resp_sba_tl_access.82571175135144782672842859271058719176825812755605506107784914782664813746499","seed":82571175135144782672842859271058719176825812755605506107784914782664813746499,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2550700355 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2550700355 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 19.rv_dm_delayed_resp_sba_tl_access.2550700355 -covoverwrite' seed=82571175135144782672842859271058719176825812755605506107784914782664813746499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82571175135144782672842859271058719176825812755605506107784914782664813746499 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"19.rv_dm_bad_sba_tl_access.110349966571268573299651990741541437382882466566432020622853213478916467031389","seed":110349966571268573299651990741541437382882466566432020622853213478916467031389,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3288431965 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/19.rv_dm_bad_sba_tl_access.3288431965 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 19.rv_dm_bad_sba_tl_access.3288431965 -covoverwrite' seed=110349966571268573299651990741541437382882466566432020622853213478916467031389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110349966571268573299651990741541437382882466566432020622853213478916467031389 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"19.rv_dm_autoincr_sba_tl_access.81138218244402940019189983338268484441889068524375107337375511867944882177088","seed":81138218244402940019189983338268484441889068524375107337375511867944882177088,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2042135616 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/19.rv_dm_autoincr_sba_tl_access.2042135616 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 19.rv_dm_autoincr_sba_tl_access.2042135616 -covoverwrite' seed=81138218244402940019189983338268484441889068524375107337375511867944882177088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81138218244402940019189983338268484441889068524375107337375511867944882177088 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"19.rv_dm_stress_all_with_rand_reset.111829731293574365088743378997331824202691530001557282560204583673682729058645","seed":111829731293574365088743378997331824202691530001557282560204583673682729058645,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4286529877 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/19.rv_dm_stress_all_with_rand_reset.4286529877 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 19.rv_dm_stress_all_with_rand_reset.4286529877 -covoverwrite' seed=111829731293574365088743378997331824202691530001557282560204583673682729058645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111829731293574365088743378997331824202691530001557282560204583673682729058645 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"19.rv_dm_tl_errors.44482019377359533041869758565785502340227507111199659498511689454206217905855","seed":44482019377359533041869758565785502340227507111199659498511689454206217905855,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1499489983 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/19.rv_dm_tl_errors.1499489983 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_dm_tl_errors.1499489983 -covoverwrite' seed=44482019377359533041869758565785502340227507111199659498511689454206217905855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44482019377359533041869758565785502340227507111199659498511689454206217905855 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"19.rv_dm_tl_intg_err.49228020711425128976297614752743902663173884201801063980313083420207744803716","seed":49228020711425128976297614752743902663173884201801063980313083420207744803716,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1450959748 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1450959748 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_dm_tl_intg_err.1450959748 -covoverwrite' seed=49228020711425128976297614752743902663173884201801063980313083420207744803716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49228020711425128976297614752743902663173884201801063980313083420207744803716 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"20.rv_dm_tl_errors.59800903968071837838705136915475359790170704561180389133209606404991868648240","seed":59800903968071837838705136915475359790170704561180389133209606404991868648240,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/20.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/20.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3911105328 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/20.rv_dm_tl_errors.3911105328 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rv_dm_tl_errors.3911105328 -covoverwrite' seed=59800903968071837838705136915475359790170704561180389133209606404991868648240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59800903968071837838705136915475359790170704561180389133209606404991868648240 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/20.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"20.rv_dm_tl_intg_err.115566049801002096807303227046136096218928274291348748183426162401424679310134","seed":115566049801002096807303227046136096218928274291348748183426162401424679310134,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/20.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/20.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2043614006 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/20.rv_dm_tl_intg_err.2043614006 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rv_dm_tl_intg_err.2043614006 -covoverwrite' seed=115566049801002096807303227046136096218928274291348748183426162401424679310134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115566049801002096807303227046136096218928274291348748183426162401424679310134 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/20.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"21.rv_dm_tl_errors.107717847365051338148845025231010553870544024269986479013678737162595167640083","seed":107717847365051338148845025231010553870544024269986479013678737162595167640083,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/21.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/21.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=849615379 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/21.rv_dm_tl_errors.849615379 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rv_dm_tl_errors.849615379 -covoverwrite' seed=107717847365051338148845025231010553870544024269986479013678737162595167640083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107717847365051338148845025231010553870544024269986479013678737162595167640083 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/21.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"21.rv_dm_tl_intg_err.21484064038929739419578012925366113652951067730413269547639086912655650397659","seed":21484064038929739419578012925366113652951067730413269547639086912655650397659,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/21.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/21.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=100867547 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/21.rv_dm_tl_intg_err.100867547 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rv_dm_tl_intg_err.100867547 -covoverwrite' seed=21484064038929739419578012925366113652951067730413269547639086912655650397659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21484064038929739419578012925366113652951067730413269547639086912655650397659 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/21.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"22.rv_dm_tl_errors.21624456325528614609288501080501076579726830840275707648574685895039521696353","seed":21624456325528614609288501080501076579726830840275707648574685895039521696353,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/22.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/22.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=974957153 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/22.rv_dm_tl_errors.974957153 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rv_dm_tl_errors.974957153 -covoverwrite' seed=21624456325528614609288501080501076579726830840275707648574685895039521696353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21624456325528614609288501080501076579726830840275707648574685895039521696353 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/22.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"22.rv_dm_tl_intg_err.111277395602713394317646004297622618809224587673697862844292683171748876863672","seed":111277395602713394317646004297622618809224587673697862844292683171748876863672,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/22.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/22.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4025698488 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/22.rv_dm_tl_intg_err.4025698488 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rv_dm_tl_intg_err.4025698488 -covoverwrite' seed=111277395602713394317646004297622618809224587673697862844292683171748876863672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111277395602713394317646004297622618809224587673697862844292683171748876863672 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/22.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"23.rv_dm_tl_errors.97579643587013141885366335280577300681342097171290484828038448704815259371335","seed":97579643587013141885366335280577300681342097171290484828038448704815259371335,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/23.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/23.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3437414215 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/23.rv_dm_tl_errors.3437414215 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rv_dm_tl_errors.3437414215 -covoverwrite' seed=97579643587013141885366335280577300681342097171290484828038448704815259371335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97579643587013141885366335280577300681342097171290484828038448704815259371335 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/23.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"23.rv_dm_tl_intg_err.59058193080121814188185645513325907957948080378490445000585030789494097242078","seed":59058193080121814188185645513325907957948080378490445000585030789494097242078,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/23.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/23.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2868832222 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/23.rv_dm_tl_intg_err.2868832222 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rv_dm_tl_intg_err.2868832222 -covoverwrite' seed=59058193080121814188185645513325907957948080378490445000585030789494097242078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59058193080121814188185645513325907957948080378490445000585030789494097242078 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/23.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_errors","qual_name":"24.rv_dm_tl_errors.50484282870089631489281455007363944137759391375488540443242121716154792792858","seed":50484282870089631489281455007363944137759391375488540443242121716154792792858,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/24.rv_dm_tl_errors/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/24.rv_dm_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3242316570 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/24.rv_dm_tl_errors.3242316570 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rv_dm_tl_errors.3242316570 -covoverwrite' seed=50484282870089631489281455007363944137759391375488540443242121716154792792858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50484282870089631489281455007363944137759391375488540443242121716154792792858 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/24.rv_dm_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"rv_dm_tl_intg_err","qual_name":"24.rv_dm_tl_intg_err.88189783345652225934614930960880410494981670370843638214071667465213853344166","seed":88189783345652225934614930960880410494981670370843638214071667465213853344166,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/24.rv_dm_tl_intg_err/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/24.rv_dm_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2552537510 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/24.rv_dm_tl_intg_err.2552537510 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rv_dm_tl_intg_err.2552537510 -covoverwrite' seed=88189783345652225934614930960880410494981670370843638214071667465213853344166 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88189783345652225934614930960880410494981670370843638214071667465213853344166 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/24.rv_dm_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*])":[{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.35908395683369358247711894504348712489650930128095330977624565229787722653243","seed":35908395683369358247711894504348712489650930128095330977624565229787722653243,"line":89,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 1244920374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"1.rv_dm_stress_all.37773807195401412495530499165155555038848608155583507799799576025623193937628","seed":37773807195401412495530499165155555038848608155583507799799576025623193937628,"line":111,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 5998178481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"2.rv_dm_stress_all.2637375689563253791301164274332120890326510731446620440671220737842410873218","seed":2637375689563253791301164274332120890326510731446620440671220737842410873218,"line":91,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 4267476619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"5.rv_dm_stress_all.15497544185498300322134824287982647612064269760723768148277601115967798484817","seed":15497544185498300322134824287982647612064269760723768148277601115967798484817,"line":91,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/5.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 1646984154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"10.rv_dm_stress_all.28968376261522165194772937944440698016630353624545428541648908851560404885980","seed":28968376261522165194772937944440698016630353624545428541648908851560404885980,"line":89,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/10.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 431932222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"16.rv_dm_stress_all.43739762984662765440445957478989458835697290305105118775048705511313446228260","seed":43739762984662765440445957478989458835697290305105118775048705511313446228260,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/16.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @  86807605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"17.rv_dm_stress_all.33489999923231171848067130158149543016036660642148379167800544927691559006165","seed":33489999923231171848067130158149543016036660642148379167800544927691559006165,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/17.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 274726407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*])":[{"name":"rv_dm_stress_all","qual_name":"3.rv_dm_stress_all.27706798161838824041046910859843085491486060993340976871914770293234698625613","seed":27706798161838824041046910859843085491486060993340976871914770293234698625613,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/3.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @  59722253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"7.rv_dm_stress_all.105942574113592280252693588983390763839660191774873758476526017740546794906810","seed":105942574113592280252693588983390763839660191774873758476526017740546794906810,"line":89,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/7.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 893198955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"9.rv_dm_stress_all.21198821232646462721236029976448710804188447784201302533414268041300880017531","seed":21198821232646462721236029976448710804188447784201302533414268041300880017531,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 978950846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])":[{"name":"rv_dm_stress_all","qual_name":"4.rv_dm_stress_all.52216510902884716708723126836303156316385600432444077508800582538082493076513","seed":52216510902884716708723126836303156316385600432444077508800582538082493076513,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/4.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 268243412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"6.rv_dm_stress_all.23170791706582010883872582661844408303330671162176744990815240012026865641959","seed":23170791706582010883872582661844408303330671162176744990815240012026865641959,"line":93,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/6.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 7555208311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"15.rv_dm_stress_all.22132413459347964257282754072702521387112253740522289898737061771624776289368","seed":22132413459347964257282754072702521387112253740522289898737061771624776289368,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/15.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 123542780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"rv_dm_stress_all","qual_name":"11.rv_dm_stress_all.79342770201826582573555773145736130383368631604816364931985537029910263379052","seed":79342770201826582573555773145736130383368631604816364931985537029910263379052,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/11.rv_dm_stress_all/latest/run.log","log_context":[]},{"name":"rv_dm_stress_all","qual_name":"12.rv_dm_stress_all.9979032434182272823640226074317476400649677942119049275750473373415543748121","seed":9979032434182272823640226074317476400649677942119049275750473373415543748121,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/12.rv_dm_stress_all/latest/run.log","log_context":[]},{"name":"rv_dm_stress_all","qual_name":"13.rv_dm_stress_all.87235894357608953068936382860625203086805748427847407466214579405038217732157","seed":87235894357608953068936382860625203086805748427847407466214579405038217732157,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_stress_all/latest/run.log","log_context":[]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_stress_all","qual_name":"18.rv_dm_stress_all.34703265458193652927795625687385558848084264964937501763249312664151776151043","seed":34703265458193652927795625687385558848084264964937501763249312664151776151043,"line":89,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"19.rv_dm_stress_all.73626561680026202321795528251431225312673794163409048234177484753124752304937","seed":73626561680026202321795528251431225312673794163409048234177484753124752304937,"line":89,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/19.rv_dm_stress_all/latest/run.log","log_context":["UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned a non-zero exit code: *":[{"name":"rv_dm","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/cov_merge/merged/cov_merge.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126\n"]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"rv_dm","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/cov_report/cov_report.log","log_context":[]}]}},"passed":2,"total":368,"percent":0.5434782608695652}