{"block":{"name":"xbar_dbg","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/tlul/data/tlul_testplan.html","stages":{"V1":{"testpoints":{"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":0.9187219385057688,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"V2":{"testpoints":{"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":1.5971836792305112,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":1.6561569068580866,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_large_delays":{"max_time":1.5876937415450811,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_slow_rsp":{"max_time":1.6040708171203732,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_zero_delays":{"max_time":0.9171446487307549,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_large_delays":{"max_time":1.609106371179223,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_slow_rsp":{"max_time":0.8935454525053501,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":120,"percent":0.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":1.6020463490858674,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":1.4259824696928263,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":1.6138419229537249,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":1.4259824696928263,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":1.6252048024907708,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_access_same_device_slow_rsp":{"max_time":1.6365479324012995,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":1.6313359010964632,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":1.6252703946083784,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_error":{"max_time":1.585418440401554,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":1.6534916823729873,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_reset_error":{"max_time":1.6118767047300935,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0}},"passed":0,"total":430,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"xbar_smoke","qual_name":"0.xbar_smoke.90497484906015483390094003423443580798955795260857807988878974517996881707092","seed":90497484906015483390094003423443580798955795260857807988878974517996881707092,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4040425556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4040425556' seed=90497484906015483390094003423443580798955795260857807988878974517996881707092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90497484906015483390094003423443580798955795260857807988878974517996881707092 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"0.xbar_smoke_zero_delays.101440928671883565768521620134253181289352550000730080806507611327558890685045","seed":101440928671883565768521620134253181289352550000730080806507611327558890685045,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1407320693 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1407320693' seed=101440928671883565768521620134253181289352550000730080806507611327558890685045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101440928671883565768521620134253181289352550000730080806507611327558890685045 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"0.xbar_smoke_large_delays.111760876111961637900850854849517067339903061132007583128586182403376760201481","seed":111760876111961637900850854849517067339903061132007583128586182403376760201481,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394764553 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.394764553' seed=111760876111961637900850854849517067339903061132007583128586182403376760201481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111760876111961637900850854849517067339903061132007583128586182403376760201481 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"0.xbar_smoke_slow_rsp.3169847894607033270409644560954301042202247176607380721791384177598188324533","seed":3169847894607033270409644560954301042202247176607380721791384177598188324533,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3242821301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3242821301' seed=3169847894607033270409644560954301042202247176607380721791384177598188324533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3169847894607033270409644560954301042202247176607380721791384177598188324533 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"0.xbar_random.42436286868733128863650005937430951117304813128314708402445341219103292387838","seed":42436286868733128863650005937430951117304813128314708402445341219103292387838,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3597005310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3597005310' seed=42436286868733128863650005937430951117304813128314708402445341219103292387838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42436286868733128863650005937430951117304813128314708402445341219103292387838 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"0.xbar_random_zero_delays.114156479415883935881192856026121317490991853779649638938941821479841424054086","seed":114156479415883935881192856026121317490991853779649638938941821479841424054086,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1628280646 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1628280646' seed=114156479415883935881192856026121317490991853779649638938941821479841424054086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114156479415883935881192856026121317490991853779649638938941821479841424054086 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"0.xbar_random_large_delays.60156730263819835169283103050698909204245343368883980240711152182405289901692","seed":60156730263819835169283103050698909204245343368883980240711152182405289901692,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2300214908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2300214908' seed=60156730263819835169283103050698909204245343368883980240711152182405289901692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60156730263819835169283103050698909204245343368883980240711152182405289901692 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"0.xbar_random_slow_rsp.14795567263771438477531323636269993884759654263070081857898976703216195786374","seed":14795567263771438477531323636269993884759654263070081857898976703216195786374,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=264033926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.264033926' seed=14795567263771438477531323636269993884759654263070081857898976703216195786374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14795567263771438477531323636269993884759654263070081857898976703216195786374 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"0.xbar_access_same_device.53210114979665960995908666578398378140623047363182596717725778440995954709159","seed":53210114979665960995908666578398378140623047363182596717725778440995954709159,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=986665639 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.986665639' seed=53210114979665960995908666578398378140623047363182596717725778440995954709159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53210114979665960995908666578398378140623047363182596717725778440995954709159 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.4351918976899948725359696633787691764627170305525788350332601147007760987014","seed":4351918976899948725359696633787691764627170305525788350332601147007760987014,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3486643078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3486643078' seed=4351918976899948725359696633787691764627170305525788350332601147007760987014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4351918976899948725359696633787691764627170305525788350332601147007760987014 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"0.xbar_same_source.26005722575159199410819678047962964573367934370508047848414604129098049256027","seed":26005722575159199410819678047962964573367934370508047848414604129098049256027,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1416362587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1416362587' seed=26005722575159199410819678047962964573367934370508047848414604129098049256027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26005722575159199410819678047962964573367934370508047848414604129098049256027 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"0.xbar_error_random.27878272253074539727677298182066144164784307225014015035807271384443199162485","seed":27878272253074539727677298182066144164784307225014015035807271384443199162485,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=294652021 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.294652021' seed=27878272253074539727677298182066144164784307225014015035807271384443199162485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27878272253074539727677298182066144164784307225014015035807271384443199162485 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"0.xbar_unmapped_addr.15505035863972686881847378792713289670546684860441612357047585086076231655950","seed":15505035863972686881847378792713289670546684860441612357047585086076231655950,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967956494 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1967956494' seed=15505035863972686881847378792713289670546684860441612357047585086076231655950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15505035863972686881847378792713289670546684860441612357047585086076231655950 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"0.xbar_error_and_unmapped_addr.2948828281973175143982905724466423518555613557098517163876589622790368334632","seed":2948828281973175143982905724466423518555613557098517163876589622790368334632,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2322666280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2322666280' seed=2948828281973175143982905724466423518555613557098517163876589622790368334632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2948828281973175143982905724466423518555613557098517163876589622790368334632 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"0.xbar_stress_all.65263040628858901680533215129014746489446264265639804989490594224499089501085","seed":65263040628858901680533215129014746489446264265639804989490594224499089501085,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177761181 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.177761181' seed=65263040628858901680533215129014746489446264265639804989490594224499089501085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65263040628858901680533215129014746489446264265639804989490594224499089501085 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"0.xbar_stress_all_with_rand_reset.36525677327985303276367643605015962189132372535297112679236669619091193110210","seed":36525677327985303276367643605015962189132372535297112679236669619091193110210,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603102914 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.603102914' seed=36525677327985303276367643605015962189132372535297112679236669619091193110210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36525677327985303276367643605015962189132372535297112679236669619091193110210 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"0.xbar_stress_all_with_error.67240831979120943252336999382104543589683546713396641814802770038164367202925","seed":67240831979120943252336999382104543589683546713396641814802770038164367202925,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221688429 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4221688429' seed=67240831979120943252336999382104543589683546713396641814802770038164367202925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67240831979120943252336999382104543589683546713396641814802770038164367202925 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"0.xbar_stress_all_with_reset_error.105747891528978058189432819373539079878116786433636786680814717013379511532518","seed":105747891528978058189432819373539079878116786433636786680814717013379511532518,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871676902 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.871676902' seed=105747891528978058189432819373539079878116786433636786680814717013379511532518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105747891528978058189432819373539079878116786433636786680814717013379511532518 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/0.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"1.xbar_smoke.50763066671264653801367942228684043904544431602231300872995742622614991254923","seed":50763066671264653801367942228684043904544431602231300872995742622614991254923,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747984779 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3747984779' seed=50763066671264653801367942228684043904544431602231300872995742622614991254923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50763066671264653801367942228684043904544431602231300872995742622614991254923 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"1.xbar_smoke_zero_delays.45003385055548440835917524444951802751597046939185102407695419584628165484555","seed":45003385055548440835917524444951802751597046939185102407695419584628165484555,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4192247819 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4192247819' seed=45003385055548440835917524444951802751597046939185102407695419584628165484555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45003385055548440835917524444951802751597046939185102407695419584628165484555 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"1.xbar_smoke_large_delays.5766904914805410083321971337877585113597665162528489305953669491761111756158","seed":5766904914805410083321971337877585113597665162528489305953669491761111756158,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2449599870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2449599870' seed=5766904914805410083321971337877585113597665162528489305953669491761111756158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5766904914805410083321971337877585113597665162528489305953669491761111756158 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"1.xbar_smoke_slow_rsp.74174685040166642565925291502941694118854439445071941542079685111766606751858","seed":74174685040166642565925291502941694118854439445071941542079685111766606751858,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221905010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.4221905010' seed=74174685040166642565925291502941694118854439445071941542079685111766606751858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74174685040166642565925291502941694118854439445071941542079685111766606751858 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"1.xbar_random.43233246617948801335898432815955248548111403111342169747774796858625773071622","seed":43233246617948801335898432815955248548111403111342169747774796858625773071622,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1805708550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1805708550' seed=43233246617948801335898432815955248548111403111342169747774796858625773071622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43233246617948801335898432815955248548111403111342169747774796858625773071622 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"1.xbar_random_zero_delays.107589276066374571416964061558240462384452621494453086864761912705364074566332","seed":107589276066374571416964061558240462384452621494453086864761912705364074566332,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1954943676 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1954943676' seed=107589276066374571416964061558240462384452621494453086864761912705364074566332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107589276066374571416964061558240462384452621494453086864761912705364074566332 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"1.xbar_random_large_delays.56283550456857527450742600686904307063756977340966801771921595845837653964643","seed":56283550456857527450742600686904307063756977340966801771921595845837653964643,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387324259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3387324259' seed=56283550456857527450742600686904307063756977340966801771921595845837653964643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56283550456857527450742600686904307063756977340966801771921595845837653964643 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"1.xbar_random_slow_rsp.48581413613736089853411740145494403021648889482354184422826401945550960579225","seed":48581413613736089853411740145494403021648889482354184422826401945550960579225,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953878681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1953878681' seed=48581413613736089853411740145494403021648889482354184422826401945550960579225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48581413613736089853411740145494403021648889482354184422826401945550960579225 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"1.xbar_access_same_device.54658547343440049461351358965130021523554731516102938258504110172816648828170","seed":54658547343440049461351358965130021523554731516102938258504110172816648828170,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=341964042 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.341964042' seed=54658547343440049461351358965130021523554731516102938258504110172816648828170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54658547343440049461351358965130021523554731516102938258504110172816648828170 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"1.xbar_access_same_device_slow_rsp.90267130106581279158552780260517314153561335068056722315980660650112925301020","seed":90267130106581279158552780260517314153561335068056722315980660650112925301020,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439772444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2439772444' seed=90267130106581279158552780260517314153561335068056722315980660650112925301020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90267130106581279158552780260517314153561335068056722315980660650112925301020 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"1.xbar_same_source.80451736645427691669526942853118657420065467993740827994636505843808074898919","seed":80451736645427691669526942853118657420065467993740827994636505843808074898919,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2899484135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2899484135' seed=80451736645427691669526942853118657420065467993740827994636505843808074898919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80451736645427691669526942853118657420065467993740827994636505843808074898919 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"1.xbar_error_random.110965711191582516803781209045021879794139926331086392133423623747358225466303","seed":110965711191582516803781209045021879794139926331086392133423623747358225466303,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543111615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1543111615' seed=110965711191582516803781209045021879794139926331086392133423623747358225466303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110965711191582516803781209045021879794139926331086392133423623747358225466303 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"1.xbar_unmapped_addr.13510351373327523300356430681463613038885230511773585297659531259319649530576","seed":13510351373327523300356430681463613038885230511773585297659531259319649530576,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3059708624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3059708624' seed=13510351373327523300356430681463613038885230511773585297659531259319649530576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13510351373327523300356430681463613038885230511773585297659531259319649530576 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"1.xbar_error_and_unmapped_addr.12834279568850257186624022714719391390869354716666808006479547312864211374398","seed":12834279568850257186624022714719391390869354716666808006479547312864211374398,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2553155902 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2553155902' seed=12834279568850257186624022714719391390869354716666808006479547312864211374398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12834279568850257186624022714719391390869354716666808006479547312864211374398 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"1.xbar_stress_all.24652683499103940368788537895205616552993484999475397653492494193058354383576","seed":24652683499103940368788537895205616552993484999475397653492494193058354383576,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1425885912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1425885912' seed=24652683499103940368788537895205616552993484999475397653492494193058354383576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24652683499103940368788537895205616552993484999475397653492494193058354383576 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"1.xbar_stress_all_with_rand_reset.25379514119034549042842273269643717194635060138327593795430746627171923875749","seed":25379514119034549042842273269643717194635060138327593795430746627171923875749,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342527397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1342527397' seed=25379514119034549042842273269643717194635060138327593795430746627171923875749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25379514119034549042842273269643717194635060138327593795430746627171923875749 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"1.xbar_stress_all_with_error.105323615374746564298215697011684584823601367803830823790827816762368181424249","seed":105323615374746564298215697011684584823601367803830823790827816762368181424249,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774393977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.774393977' seed=105323615374746564298215697011684584823601367803830823790827816762368181424249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105323615374746564298215697011684584823601367803830823790827816762368181424249 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"1.xbar_stress_all_with_reset_error.90966043714159292161779613807858638144350272262909643157835145766164068841549","seed":90966043714159292161779613807858638144350272262909643157835145766164068841549,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4226037837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.4226037837' seed=90966043714159292161779613807858638144350272262909643157835145766164068841549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90966043714159292161779613807858638144350272262909643157835145766164068841549 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/1.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"2.xbar_smoke.85507462898249621806413897376632710899676741158970722728212888855020912745962","seed":85507462898249621806413897376632710899676741158970722728212888855020912745962,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4196638186 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.4196638186' seed=85507462898249621806413897376632710899676741158970722728212888855020912745962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85507462898249621806413897376632710899676741158970722728212888855020912745962 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"2.xbar_smoke_zero_delays.72957312637855962925762979658914203539739246952296601123444267619416103112444","seed":72957312637855962925762979658914203539739246952296601123444267619416103112444,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1763888892 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1763888892' seed=72957312637855962925762979658914203539739246952296601123444267619416103112444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72957312637855962925762979658914203539739246952296601123444267619416103112444 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"2.xbar_smoke_large_delays.19218732697607608399092236999587500608016532837382265587534421374813133261744","seed":19218732697607608399092236999587500608016532837382265587534421374813133261744,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2995964848 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2995964848' seed=19218732697607608399092236999587500608016532837382265587534421374813133261744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19218732697607608399092236999587500608016532837382265587534421374813133261744 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"2.xbar_smoke_slow_rsp.15815293040750603582130451785658723409757506309145264254660567973188007834845","seed":15815293040750603582130451785658723409757506309145264254660567973188007834845,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=297219293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.297219293' seed=15815293040750603582130451785658723409757506309145264254660567973188007834845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15815293040750603582130451785658723409757506309145264254660567973188007834845 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"2.xbar_random.52166242945698187642364155396694032790698020656986064900607394379398657591544","seed":52166242945698187642364155396694032790698020656986064900607394379398657591544,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2622736632 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2622736632' seed=52166242945698187642364155396694032790698020656986064900607394379398657591544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52166242945698187642364155396694032790698020656986064900607394379398657591544 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"2.xbar_random_zero_delays.61511461241316463887710646838722295397876363582774513062715968350614381953593","seed":61511461241316463887710646838722295397876363582774513062715968350614381953593,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3562046009 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3562046009' seed=61511461241316463887710646838722295397876363582774513062715968350614381953593 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61511461241316463887710646838722295397876363582774513062715968350614381953593 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"2.xbar_random_large_delays.84143838438191538333426246605093520301205647065284766485183613217864862279099","seed":84143838438191538333426246605093520301205647065284766485183613217864862279099,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4171638203 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4171638203' seed=84143838438191538333426246605093520301205647065284766485183613217864862279099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84143838438191538333426246605093520301205647065284766485183613217864862279099 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"2.xbar_random_slow_rsp.112285664477640240665860060407212455641307153551598216798368189301566738591489","seed":112285664477640240665860060407212455641307153551598216798368189301566738591489,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210800897 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3210800897' seed=112285664477640240665860060407212455641307153551598216798368189301566738591489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112285664477640240665860060407212455641307153551598216798368189301566738591489 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"2.xbar_access_same_device.46898964419070771805983102872820060173041476875032000436860792225354758137198","seed":46898964419070771805983102872820060173041476875032000436860792225354758137198,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2161812846 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2161812846' seed=46898964419070771805983102872820060173041476875032000436860792225354758137198 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46898964419070771805983102872820060173041476875032000436860792225354758137198 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"2.xbar_access_same_device_slow_rsp.43200992356745049314059661131868941878923769274072512511979458806644368995859","seed":43200992356745049314059661131868941878923769274072512511979458806644368995859,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2533357075 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.2533357075' seed=43200992356745049314059661131868941878923769274072512511979458806644368995859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43200992356745049314059661131868941878923769274072512511979458806644368995859 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"2.xbar_same_source.82233027499583162776421414752665522976373930788893528771460320982678240699063","seed":82233027499583162776421414752665522976373930788893528771460320982678240699063,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=791093943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.791093943' seed=82233027499583162776421414752665522976373930788893528771460320982678240699063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82233027499583162776421414752665522976373930788893528771460320982678240699063 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"2.xbar_error_random.44959078789499534149093875158870474992211437073444409706024201603325506927247","seed":44959078789499534149093875158870474992211437073444409706024201603325506927247,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2315303567 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2315303567' seed=44959078789499534149093875158870474992211437073444409706024201603325506927247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44959078789499534149093875158870474992211437073444409706024201603325506927247 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"2.xbar_unmapped_addr.65218664630393541652368405545623534392104331468725114240211734290413724920713","seed":65218664630393541652368405545623534392104331468725114240211734290413724920713,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=259550089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.259550089' seed=65218664630393541652368405545623534392104331468725114240211734290413724920713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65218664630393541652368405545623534392104331468725114240211734290413724920713 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"2.xbar_error_and_unmapped_addr.51144884241117364402774865668624221193421205020848922070102088223672316631778","seed":51144884241117364402774865668624221193421205020848922070102088223672316631778,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1422826210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1422826210' seed=51144884241117364402774865668624221193421205020848922070102088223672316631778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51144884241117364402774865668624221193421205020848922070102088223672316631778 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"2.xbar_stress_all.108176473848142934065151570473072890219417793660659261689640774431977064483192","seed":108176473848142934065151570473072890219417793660659261689640774431977064483192,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007433080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3007433080' seed=108176473848142934065151570473072890219417793660659261689640774431977064483192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108176473848142934065151570473072890219417793660659261689640774431977064483192 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"2.xbar_stress_all_with_rand_reset.63344687428062033739702540298264164347571923633550423248442771852152964836088","seed":63344687428062033739702540298264164347571923633550423248442771852152964836088,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181650168 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.4181650168' seed=63344687428062033739702540298264164347571923633550423248442771852152964836088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63344687428062033739702540298264164347571923633550423248442771852152964836088 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"2.xbar_stress_all_with_error.94994491612271535939864263795894999456812859530206402520031139912186042343091","seed":94994491612271535939864263795894999456812859530206402520031139912186042343091,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504955059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3504955059' seed=94994491612271535939864263795894999456812859530206402520031139912186042343091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94994491612271535939864263795894999456812859530206402520031139912186042343091 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"2.xbar_stress_all_with_reset_error.58974888384955388618454919732148508136040340724733699694586253007545390099510","seed":58974888384955388618454919732148508136040340724733699694586253007545390099510,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941648950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.941648950' seed=58974888384955388618454919732148508136040340724733699694586253007545390099510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58974888384955388618454919732148508136040340724733699694586253007545390099510 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/2.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"3.xbar_smoke.115667220278988725465409237982551682975251076777066933258434953936849048809287","seed":115667220278988725465409237982551682975251076777066933258434953936849048809287,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2340269895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2340269895' seed=115667220278988725465409237982551682975251076777066933258434953936849048809287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115667220278988725465409237982551682975251076777066933258434953936849048809287 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"3.xbar_smoke_zero_delays.22745299404578361954041566151945323071645559039946971049413338462871508719950","seed":22745299404578361954041566151945323071645559039946971049413338462871508719950,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2648938830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2648938830' seed=22745299404578361954041566151945323071645559039946971049413338462871508719950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22745299404578361954041566151945323071645559039946971049413338462871508719950 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"3.xbar_smoke_large_delays.61268981688484859443049191136245680926320186542106714991871942002881723657230","seed":61268981688484859443049191136245680926320186542106714991871942002881723657230,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=858024974 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.858024974' seed=61268981688484859443049191136245680926320186542106714991871942002881723657230 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61268981688484859443049191136245680926320186542106714991871942002881723657230 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"3.xbar_smoke_slow_rsp.59304636180475238607597066161887301750591101039993896138711521990792315451015","seed":59304636180475238607597066161887301750591101039993896138711521990792315451015,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=955823751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.955823751' seed=59304636180475238607597066161887301750591101039993896138711521990792315451015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59304636180475238607597066161887301750591101039993896138711521990792315451015 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"3.xbar_random.74828474922532420203870134674229337726688511280781794139700239981229061674383","seed":74828474922532420203870134674229337726688511280781794139700239981229061674383,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3209401743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3209401743' seed=74828474922532420203870134674229337726688511280781794139700239981229061674383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74828474922532420203870134674229337726688511280781794139700239981229061674383 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"3.xbar_random_zero_delays.3635353200849813685683418732729913194728572490790163409599349166569158327620","seed":3635353200849813685683418732729913194728572490790163409599349166569158327620,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1438367044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1438367044' seed=3635353200849813685683418732729913194728572490790163409599349166569158327620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3635353200849813685683418732729913194728572490790163409599349166569158327620 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"3.xbar_random_large_delays.97552829423143468274338061292235125782491679270075770676800673995259282197270","seed":97552829423143468274338061292235125782491679270075770676800673995259282197270,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3134196502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3134196502' seed=97552829423143468274338061292235125782491679270075770676800673995259282197270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97552829423143468274338061292235125782491679270075770676800673995259282197270 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"3.xbar_random_slow_rsp.61932553990621621434903864800876336664978374709325872935864721659847898196853","seed":61932553990621621434903864800876336664978374709325872935864721659847898196853,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=511863669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.511863669' seed=61932553990621621434903864800876336664978374709325872935864721659847898196853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61932553990621621434903864800876336664978374709325872935864721659847898196853 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"3.xbar_access_same_device.112246244337487138910171340500805517097484837987320417779010659571140474020813","seed":112246244337487138910171340500805517097484837987320417779010659571140474020813,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=668312525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.668312525' seed=112246244337487138910171340500805517097484837987320417779010659571140474020813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112246244337487138910171340500805517097484837987320417779010659571140474020813 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"3.xbar_access_same_device_slow_rsp.71175164449364064415657942595290834842079641645091475282799194679431165072228","seed":71175164449364064415657942595290834842079641645091475282799194679431165072228,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1678201700 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1678201700' seed=71175164449364064415657942595290834842079641645091475282799194679431165072228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71175164449364064415657942595290834842079641645091475282799194679431165072228 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"3.xbar_same_source.70368065994793119818990533952755748650404989955518088800301004987715886769916","seed":70368065994793119818990533952755748650404989955518088800301004987715886769916,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641722108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.641722108' seed=70368065994793119818990533952755748650404989955518088800301004987715886769916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70368065994793119818990533952755748650404989955518088800301004987715886769916 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"3.xbar_error_random.22577055291152012012308421998110948134529590993820077349933873522107521985078","seed":22577055291152012012308421998110948134529590993820077349933873522107521985078,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3873466934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3873466934' seed=22577055291152012012308421998110948134529590993820077349933873522107521985078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22577055291152012012308421998110948134529590993820077349933873522107521985078 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"3.xbar_unmapped_addr.29501226642109683762320568264294997368995824523957709752528681203730335842680","seed":29501226642109683762320568264294997368995824523957709752528681203730335842680,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=529973624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.529973624' seed=29501226642109683762320568264294997368995824523957709752528681203730335842680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29501226642109683762320568264294997368995824523957709752528681203730335842680 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"3.xbar_error_and_unmapped_addr.48980857845049959051117527784405765097041602285420575147967579802400152261624","seed":48980857845049959051117527784405765097041602285420575147967579802400152261624,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2761593848 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2761593848' seed=48980857845049959051117527784405765097041602285420575147967579802400152261624 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48980857845049959051117527784405765097041602285420575147967579802400152261624 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"3.xbar_stress_all.227264539675463636417456317531003087255644718253389825010480589581373208073","seed":227264539675463636417456317531003087255644718253389825010480589581373208073,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4178114057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4178114057' seed=227264539675463636417456317531003087255644718253389825010480589581373208073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=227264539675463636417456317531003087255644718253389825010480589581373208073 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"3.xbar_stress_all_with_rand_reset.76885739832808168362112233720072023856038911189978992544843009554040418136135","seed":76885739832808168362112233720072023856038911189978992544843009554040418136135,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=462876743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.462876743' seed=76885739832808168362112233720072023856038911189978992544843009554040418136135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76885739832808168362112233720072023856038911189978992544843009554040418136135 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"3.xbar_stress_all_with_error.73796396770391338543559608868559972797749510636478614692630524679748741831619","seed":73796396770391338543559608868559972797749510636478614692630524679748741831619,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2872122307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2872122307' seed=73796396770391338543559608868559972797749510636478614692630524679748741831619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73796396770391338543559608868559972797749510636478614692630524679748741831619 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"3.xbar_stress_all_with_reset_error.113578156707461092499706292914274272310674170275333655839429988754943718126269","seed":113578156707461092499706292914274272310674170275333655839429988754943718126269,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385441469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2385441469' seed=113578156707461092499706292914274272310674170275333655839429988754943718126269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113578156707461092499706292914274272310674170275333655839429988754943718126269 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/3.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"4.xbar_smoke.115312113432356845181416891276909649860134179108531001835908400557843498687590","seed":115312113432356845181416891276909649860134179108531001835908400557843498687590,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=961305702 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.961305702' seed=115312113432356845181416891276909649860134179108531001835908400557843498687590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115312113432356845181416891276909649860134179108531001835908400557843498687590 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"4.xbar_smoke_zero_delays.32410888411070940934726018263498390913842409235406828176095243992059556037563","seed":32410888411070940934726018263498390913842409235406828176095243992059556037563,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3723920315 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3723920315' seed=32410888411070940934726018263498390913842409235406828176095243992059556037563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32410888411070940934726018263498390913842409235406828176095243992059556037563 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"4.xbar_smoke_large_delays.24872305579185026918369759972044593837460053768508650263426707319358091897124","seed":24872305579185026918369759972044593837460053768508650263426707319358091897124,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3600492836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3600492836' seed=24872305579185026918369759972044593837460053768508650263426707319358091897124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24872305579185026918369759972044593837460053768508650263426707319358091897124 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"4.xbar_smoke_slow_rsp.20762880416957162180392413739149793996969514193719308169465546813684865760067","seed":20762880416957162180392413739149793996969514193719308169465546813684865760067,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305306947 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3305306947' seed=20762880416957162180392413739149793996969514193719308169465546813684865760067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20762880416957162180392413739149793996969514193719308169465546813684865760067 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"4.xbar_random.33907509722846480872506825011403038709287189971371403162333116960879348380444","seed":33907509722846480872506825011403038709287189971371403162333116960879348380444,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3682693916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3682693916' seed=33907509722846480872506825011403038709287189971371403162333116960879348380444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33907509722846480872506825011403038709287189971371403162333116960879348380444 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"4.xbar_random_zero_delays.25917472347010587564388152234564854399043397750328519366341367156702342338284","seed":25917472347010587564388152234564854399043397750328519366341367156702342338284,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3153647340 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3153647340' seed=25917472347010587564388152234564854399043397750328519366341367156702342338284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25917472347010587564388152234564854399043397750328519366341367156702342338284 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"4.xbar_random_large_delays.42156217733580947394714001044451146283707309296475344486457075740639368378648","seed":42156217733580947394714001044451146283707309296475344486457075740639368378648,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=367065368 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.367065368' seed=42156217733580947394714001044451146283707309296475344486457075740639368378648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42156217733580947394714001044451146283707309296475344486457075740639368378648 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"4.xbar_random_slow_rsp.66047054541653798153891240172866253327007630759589204300926842262721529967398","seed":66047054541653798153891240172866253327007630759589204300926842262721529967398,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3348165414 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3348165414' seed=66047054541653798153891240172866253327007630759589204300926842262721529967398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66047054541653798153891240172866253327007630759589204300926842262721529967398 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"4.xbar_access_same_device.95798639468878958829446314661221939690018453169881774892656665518551993749200","seed":95798639468878958829446314661221939690018453169881774892656665518551993749200,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871674064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3871674064' seed=95798639468878958829446314661221939690018453169881774892656665518551993749200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95798639468878958829446314661221939690018453169881774892656665518551993749200 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"4.xbar_access_same_device_slow_rsp.49675147252958272209151354484396025047520082932113048486740383576590273578767","seed":49675147252958272209151354484396025047520082932113048486740383576590273578767,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2151253775 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2151253775' seed=49675147252958272209151354484396025047520082932113048486740383576590273578767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49675147252958272209151354484396025047520082932113048486740383576590273578767 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"4.xbar_same_source.55740162155867230674774542878346247343407519863756008097415609574180093330118","seed":55740162155867230674774542878346247343407519863756008097415609574180093330118,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1383236294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1383236294' seed=55740162155867230674774542878346247343407519863756008097415609574180093330118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55740162155867230674774542878346247343407519863756008097415609574180093330118 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"4.xbar_error_random.11110962490636415914223137517879167457589031840295156242906174152688542157514","seed":11110962490636415914223137517879167457589031840295156242906174152688542157514,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3764652746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3764652746' seed=11110962490636415914223137517879167457589031840295156242906174152688542157514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11110962490636415914223137517879167457589031840295156242906174152688542157514 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"4.xbar_unmapped_addr.81546317296200454070345363147822491167149547184413635228922272667251261266909","seed":81546317296200454070345363147822491167149547184413635228922272667251261266909,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1693932509 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1693932509' seed=81546317296200454070345363147822491167149547184413635228922272667251261266909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81546317296200454070345363147822491167149547184413635228922272667251261266909 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"4.xbar_error_and_unmapped_addr.41011041955817126253510933380754133625187171340873143853300521719444458508326","seed":41011041955817126253510933380754133625187171340873143853300521719444458508326,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=447549478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.447549478' seed=41011041955817126253510933380754133625187171340873143853300521719444458508326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41011041955817126253510933380754133625187171340873143853300521719444458508326 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"4.xbar_stress_all.53477914120597693237828973284140861775844017003242357028249866715469763622779","seed":53477914120597693237828973284140861775844017003242357028249866715469763622779,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1868347259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1868347259' seed=53477914120597693237828973284140861775844017003242357028249866715469763622779 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53477914120597693237828973284140861775844017003242357028249866715469763622779 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"4.xbar_stress_all_with_rand_reset.38379092741266436689639844671541280703251227261666469744248975062687369020407","seed":38379092741266436689639844671541280703251227261666469744248975062687369020407,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155075575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.155075575' seed=38379092741266436689639844671541280703251227261666469744248975062687369020407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38379092741266436689639844671541280703251227261666469744248975062687369020407 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"4.xbar_stress_all_with_error.87071015861814797238391971338667121373664418763989052351519862727755928917113","seed":87071015861814797238391971338667121373664418763989052351519862727755928917113,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186602617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.186602617' seed=87071015861814797238391971338667121373664418763989052351519862727755928917113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87071015861814797238391971338667121373664418763989052351519862727755928917113 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"4.xbar_stress_all_with_reset_error.101280307342487758119478855927681960606143204255101566824414623749575525798434","seed":101280307342487758119478855927681960606143204255101566824414623749575525798434,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2864452130 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2864452130' seed=101280307342487758119478855927681960606143204255101566824414623749575525798434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101280307342487758119478855927681960606143204255101566824414623749575525798434 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/4.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"5.xbar_smoke.100744723882627480970474196269139583016675712330398702676888368233625943111748","seed":100744723882627480970474196269139583016675712330398702676888368233625943111748,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1410431044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1410431044' seed=100744723882627480970474196269139583016675712330398702676888368233625943111748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100744723882627480970474196269139583016675712330398702676888368233625943111748 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"5.xbar_smoke_zero_delays.100466113159201457227500072341006423985507976680777897674835256902095181634798","seed":100466113159201457227500072341006423985507976680777897674835256902095181634798,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2462506222 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2462506222' seed=100466113159201457227500072341006423985507976680777897674835256902095181634798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100466113159201457227500072341006423985507976680777897674835256902095181634798 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"5.xbar_smoke_large_delays.32053597799792889565611627507747027242771604119253380640447427653915080789318","seed":32053597799792889565611627507747027242771604119253380640447427653915080789318,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=718146886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.718146886' seed=32053597799792889565611627507747027242771604119253380640447427653915080789318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32053597799792889565611627507747027242771604119253380640447427653915080789318 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"5.xbar_smoke_slow_rsp.109055980487951115498062172928367255372324585397386516492653330729999184082505","seed":109055980487951115498062172928367255372324585397386516492653330729999184082505,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286756425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4286756425' seed=109055980487951115498062172928367255372324585397386516492653330729999184082505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109055980487951115498062172928367255372324585397386516492653330729999184082505 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"5.xbar_random.21505677886560594771003457406237958218552970835759819786961858607941267156359","seed":21505677886560594771003457406237958218552970835759819786961858607941267156359,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=758312327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.758312327' seed=21505677886560594771003457406237958218552970835759819786961858607941267156359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21505677886560594771003457406237958218552970835759819786961858607941267156359 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"5.xbar_random_zero_delays.80031560842305490124368699226813404785919786289068603015304462423248571585794","seed":80031560842305490124368699226813404785919786289068603015304462423248571585794,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2283656450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2283656450' seed=80031560842305490124368699226813404785919786289068603015304462423248571585794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80031560842305490124368699226813404785919786289068603015304462423248571585794 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"5.xbar_random_large_delays.67737358311497445868657952623201693251886879280614955637476311902642719486370","seed":67737358311497445868657952623201693251886879280614955637476311902642719486370,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1289548194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1289548194' seed=67737358311497445868657952623201693251886879280614955637476311902642719486370 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67737358311497445868657952623201693251886879280614955637476311902642719486370 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"5.xbar_random_slow_rsp.61815166079328580764659653648643076718092776719031443283973167422501967520299","seed":61815166079328580764659653648643076718092776719031443283973167422501967520299,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854380075 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2854380075' seed=61815166079328580764659653648643076718092776719031443283973167422501967520299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61815166079328580764659653648643076718092776719031443283973167422501967520299 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"5.xbar_access_same_device.20192703659389629371242651964379456905243521704025922326189902752947122892094","seed":20192703659389629371242651964379456905243521704025922326189902752947122892094,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1405513022 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1405513022' seed=20192703659389629371242651964379456905243521704025922326189902752947122892094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20192703659389629371242651964379456905243521704025922326189902752947122892094 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"5.xbar_access_same_device_slow_rsp.19651573477436760768630236339195449282195117736232091111621000774920316790001","seed":19651573477436760768630236339195449282195117736232091111621000774920316790001,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1110058225 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1110058225' seed=19651573477436760768630236339195449282195117736232091111621000774920316790001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19651573477436760768630236339195449282195117736232091111621000774920316790001 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"5.xbar_same_source.34041953573296676842415137193049081302201982518779479658357237902239497995879","seed":34041953573296676842415137193049081302201982518779479658357237902239497995879,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913303655 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3913303655' seed=34041953573296676842415137193049081302201982518779479658357237902239497995879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34041953573296676842415137193049081302201982518779479658357237902239497995879 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"5.xbar_error_random.16328797769662560548986564041968894115108746403628164055938549099781744097274","seed":16328797769662560548986564041968894115108746403628164055938549099781744097274,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387029498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3387029498' seed=16328797769662560548986564041968894115108746403628164055938549099781744097274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16328797769662560548986564041968894115108746403628164055938549099781744097274 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"5.xbar_unmapped_addr.110170317036888031447693790756566760200445275194735632551059972481749634125657","seed":110170317036888031447693790756566760200445275194735632551059972481749634125657,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2213154649 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2213154649' seed=110170317036888031447693790756566760200445275194735632551059972481749634125657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110170317036888031447693790756566760200445275194735632551059972481749634125657 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"5.xbar_error_and_unmapped_addr.96195246543747852552837678243234280710534756729697640493658272858559969504488","seed":96195246543747852552837678243234280710534756729697640493658272858559969504488,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2249207016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2249207016' seed=96195246543747852552837678243234280710534756729697640493658272858559969504488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96195246543747852552837678243234280710534756729697640493658272858559969504488 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"5.xbar_stress_all.28738532098327345763898296625384342901667918018385333115477215334535926255660","seed":28738532098327345763898296625384342901667918018385333115477215334535926255660,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1442189356 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1442189356' seed=28738532098327345763898296625384342901667918018385333115477215334535926255660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28738532098327345763898296625384342901667918018385333115477215334535926255660 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"5.xbar_stress_all_with_rand_reset.85951414616041209445247902481683225325462926071885353321264244472766321242720","seed":85951414616041209445247902481683225325462926071885353321264244472766321242720,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=412463712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.412463712' seed=85951414616041209445247902481683225325462926071885353321264244472766321242720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85951414616041209445247902481683225325462926071885353321264244472766321242720 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"5.xbar_stress_all_with_error.44686959838262007531143866022927807838950030354508145509750561078611427945143","seed":44686959838262007531143866022927807838950030354508145509750561078611427945143,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1498639031 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1498639031' seed=44686959838262007531143866022927807838950030354508145509750561078611427945143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44686959838262007531143866022927807838950030354508145509750561078611427945143 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"5.xbar_stress_all_with_reset_error.81693308012186848289178418553265937652020707150879836068734664496175446812936","seed":81693308012186848289178418553265937652020707150879836068734664496175446812936,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726984968 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.726984968' seed=81693308012186848289178418553265937652020707150879836068734664496175446812936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81693308012186848289178418553265937652020707150879836068734664496175446812936 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/5.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"6.xbar_smoke.11561288618004611462764286020286844749660998781426822599877628028467571609913","seed":11561288618004611462764286020286844749660998781426822599877628028467571609913,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4133769529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4133769529' seed=11561288618004611462764286020286844749660998781426822599877628028467571609913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11561288618004611462764286020286844749660998781426822599877628028467571609913 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"6.xbar_smoke_zero_delays.44555858310002156450336165494401336849965554305296945805503023451316554857524","seed":44555858310002156450336165494401336849965554305296945805503023451316554857524,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3831528500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3831528500' seed=44555858310002156450336165494401336849965554305296945805503023451316554857524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44555858310002156450336165494401336849965554305296945805503023451316554857524 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"6.xbar_smoke_large_delays.68733041967375737742168232606107821074414259669028529704387710205993252842080","seed":68733041967375737742168232606107821074414259669028529704387710205993252842080,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509373024 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.509373024' seed=68733041967375737742168232606107821074414259669028529704387710205993252842080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68733041967375737742168232606107821074414259669028529704387710205993252842080 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"6.xbar_smoke_slow_rsp.83527697589409593532497609560149828063731027216734813377549884878166094352735","seed":83527697589409593532497609560149828063731027216734813377549884878166094352735,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1201770847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1201770847' seed=83527697589409593532497609560149828063731027216734813377549884878166094352735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83527697589409593532497609560149828063731027216734813377549884878166094352735 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"6.xbar_random.52941799922948231291621490406574399025150327255694348270012294986941448030347","seed":52941799922948231291621490406574399025150327255694348270012294986941448030347,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748549259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2748549259' seed=52941799922948231291621490406574399025150327255694348270012294986941448030347 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52941799922948231291621490406574399025150327255694348270012294986941448030347 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"6.xbar_random_zero_delays.31089051560213903980480857595151423829930361923749294574047629754449189313150","seed":31089051560213903980480857595151423829930361923749294574047629754449189313150,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=331520638 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.331520638' seed=31089051560213903980480857595151423829930361923749294574047629754449189313150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31089051560213903980480857595151423829930361923749294574047629754449189313150 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"6.xbar_random_large_delays.50640872420465364305759397953225085367663949942510504384459866749986966357350","seed":50640872420465364305759397953225085367663949942510504384459866749986966357350,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310396262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.310396262' seed=50640872420465364305759397953225085367663949942510504384459866749986966357350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50640872420465364305759397953225085367663949942510504384459866749986966357350 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"6.xbar_random_slow_rsp.39897642326725672048262967104010051441664600703148329835824605621722212791306","seed":39897642326725672048262967104010051441664600703148329835824605621722212791306,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=461435914 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.461435914' seed=39897642326725672048262967104010051441664600703148329835824605621722212791306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39897642326725672048262967104010051441664600703148329835824605621722212791306 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"6.xbar_access_same_device.10459343737071721900692894675382804730582771307554666766990397479813629755445","seed":10459343737071721900692894675382804730582771307554666766990397479813629755445,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198645813 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.4198645813' seed=10459343737071721900692894675382804730582771307554666766990397479813629755445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10459343737071721900692894675382804730582771307554666766990397479813629755445 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"6.xbar_access_same_device_slow_rsp.105999952790674730808236563150359398349876945958987069396302386408378086512281","seed":105999952790674730808236563150359398349876945958987069396302386408378086512281,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2525812377 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.2525812377' seed=105999952790674730808236563150359398349876945958987069396302386408378086512281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105999952790674730808236563150359398349876945958987069396302386408378086512281 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"6.xbar_same_source.29807430155035158958780253769209694967925660445470007020457764888443508686747","seed":29807430155035158958780253769209694967925660445470007020457764888443508686747,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1831272347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1831272347' seed=29807430155035158958780253769209694967925660445470007020457764888443508686747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29807430155035158958780253769209694967925660445470007020457764888443508686747 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"6.xbar_error_random.9070818725732965007320952282815437970511684899605279512281859235420417026966","seed":9070818725732965007320952282815437970511684899605279512281859235420417026966,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2015882134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2015882134' seed=9070818725732965007320952282815437970511684899605279512281859235420417026966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9070818725732965007320952282815437970511684899605279512281859235420417026966 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"6.xbar_unmapped_addr.9348498977172921420617093383577033045350529174336008119503687214122613865825","seed":9348498977172921420617093383577033045350529174336008119503687214122613865825,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3907255649 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3907255649' seed=9348498977172921420617093383577033045350529174336008119503687214122613865825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9348498977172921420617093383577033045350529174336008119503687214122613865825 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"6.xbar_error_and_unmapped_addr.2894327704779594194444298703470605159416757400075055186436273559698588316183","seed":2894327704779594194444298703470605159416757400075055186436273559698588316183,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=415773207 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.415773207' seed=2894327704779594194444298703470605159416757400075055186436273559698588316183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2894327704779594194444298703470605159416757400075055186436273559698588316183 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"6.xbar_stress_all.102831209539526931202308070979951785445794884895534044100968416618516604849873","seed":102831209539526931202308070979951785445794884895534044100968416618516604849873,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2780106449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2780106449' seed=102831209539526931202308070979951785445794884895534044100968416618516604849873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102831209539526931202308070979951785445794884895534044100968416618516604849873 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"6.xbar_stress_all_with_rand_reset.21482552847588509362128233272227467732089609558378737396673234411060801344999","seed":21482552847588509362128233272227467732089609558378737396673234411060801344999,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=685807079 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.685807079' seed=21482552847588509362128233272227467732089609558378737396673234411060801344999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21482552847588509362128233272227467732089609558378737396673234411060801344999 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"6.xbar_stress_all_with_error.23121703440460898619895340922732863369450083939091152205570262446063669095377","seed":23121703440460898619895340922732863369450083939091152205570262446063669095377,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3095014353 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3095014353' seed=23121703440460898619895340922732863369450083939091152205570262446063669095377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23121703440460898619895340922732863369450083939091152205570262446063669095377 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"6.xbar_stress_all_with_reset_error.110274875385863047430659896865341426495942686209716243063449892081010016953029","seed":110274875385863047430659896865341426495942686209716243063449892081010016953029,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=330474181 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.330474181' seed=110274875385863047430659896865341426495942686209716243063449892081010016953029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110274875385863047430659896865341426495942686209716243063449892081010016953029 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/6.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"7.xbar_smoke.41954813326025293974279190835010717522413336918591608740733177695470440917974","seed":41954813326025293974279190835010717522413336918591608740733177695470440917974,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161983446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.161983446' seed=41954813326025293974279190835010717522413336918591608740733177695470440917974 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41954813326025293974279190835010717522413336918591608740733177695470440917974 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"7.xbar_smoke_zero_delays.53505803766442892926670056362172672581959560165775074566631445220010418348064","seed":53505803766442892926670056362172672581959560165775074566631445220010418348064,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2266865696 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2266865696' seed=53505803766442892926670056362172672581959560165775074566631445220010418348064 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53505803766442892926670056362172672581959560165775074566631445220010418348064 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"7.xbar_smoke_large_delays.93718200608202700479763851917338003482200850317968065025726690256872920131013","seed":93718200608202700479763851917338003482200850317968065025726690256872920131013,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596953029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3596953029' seed=93718200608202700479763851917338003482200850317968065025726690256872920131013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93718200608202700479763851917338003482200850317968065025726690256872920131013 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"7.xbar_smoke_slow_rsp.10534937870181385482853659016254073259924301673565675328320143423416357032981","seed":10534937870181385482853659016254073259924301673565675328320143423416357032981,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2641302549 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2641302549' seed=10534937870181385482853659016254073259924301673565675328320143423416357032981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10534937870181385482853659016254073259924301673565675328320143423416357032981 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"7.xbar_random.17728738793173662443490347343115279879545299127283118689326441483813828592595","seed":17728738793173662443490347343115279879545299127283118689326441483813828592595,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1296991187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1296991187' seed=17728738793173662443490347343115279879545299127283118689326441483813828592595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17728738793173662443490347343115279879545299127283118689326441483813828592595 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"7.xbar_random_zero_delays.13602865728772880765826905695368853576779431791578163019276556087780593083148","seed":13602865728772880765826905695368853576779431791578163019276556087780593083148,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4074742540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4074742540' seed=13602865728772880765826905695368853576779431791578163019276556087780593083148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13602865728772880765826905695368853576779431791578163019276556087780593083148 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"7.xbar_random_large_delays.110939388958666571200025568098125528747437789895179060602063631158037636736204","seed":110939388958666571200025568098125528747437789895179060602063631158037636736204,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2421449932 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2421449932' seed=110939388958666571200025568098125528747437789895179060602063631158037636736204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110939388958666571200025568098125528747437789895179060602063631158037636736204 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"7.xbar_random_slow_rsp.9765290855927853645842616436388802763176699517380216229031713481981085110795","seed":9765290855927853645842616436388802763176699517380216229031713481981085110795,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3329511947 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3329511947' seed=9765290855927853645842616436388802763176699517380216229031713481981085110795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9765290855927853645842616436388802763176699517380216229031713481981085110795 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"7.xbar_access_same_device.12511684830112603465708860222176645640356252059567241307366184876450288074000","seed":12511684830112603465708860222176645640356252059567241307366184876450288074000,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1587117328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1587117328' seed=12511684830112603465708860222176645640356252059567241307366184876450288074000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12511684830112603465708860222176645640356252059567241307366184876450288074000 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"7.xbar_access_same_device_slow_rsp.114933180990942592482154503084674480751130423578654686379110694969752104814278","seed":114933180990942592482154503084674480751130423578654686379110694969752104814278,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3585164998 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3585164998' seed=114933180990942592482154503084674480751130423578654686379110694969752104814278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114933180990942592482154503084674480751130423578654686379110694969752104814278 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"7.xbar_same_source.114899122380414327104134320297655988825174735499768577135363822013801926821417","seed":114899122380414327104134320297655988825174735499768577135363822013801926821417,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202497577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4202497577' seed=114899122380414327104134320297655988825174735499768577135363822013801926821417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114899122380414327104134320297655988825174735499768577135363822013801926821417 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"7.xbar_error_random.14012365558489800971601466353535668131416177391506495168018049888890397606449","seed":14012365558489800971601466353535668131416177391506495168018049888890397606449,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083892785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4083892785' seed=14012365558489800971601466353535668131416177391506495168018049888890397606449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14012365558489800971601466353535668131416177391506495168018049888890397606449 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"7.xbar_unmapped_addr.99158892926063034830645603115512922361233551165855250964908816180549191881196","seed":99158892926063034830645603115512922361233551165855250964908816180549191881196,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4133114348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4133114348' seed=99158892926063034830645603115512922361233551165855250964908816180549191881196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99158892926063034830645603115512922361233551165855250964908816180549191881196 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"7.xbar_error_and_unmapped_addr.53894374781558981242273211169151193321136762685191625786773589491351916313067","seed":53894374781558981242273211169151193321136762685191625786773589491351916313067,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1180105195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1180105195' seed=53894374781558981242273211169151193321136762685191625786773589491351916313067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53894374781558981242273211169151193321136762685191625786773589491351916313067 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"7.xbar_stress_all.23701979433469482175077496713208096555026879654470172475186641644085635596295","seed":23701979433469482175077496713208096555026879654470172475186641644085635596295,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255975943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3255975943' seed=23701979433469482175077496713208096555026879654470172475186641644085635596295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23701979433469482175077496713208096555026879654470172475186641644085635596295 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"7.xbar_stress_all_with_rand_reset.65713419984205656757704117537694371941515985650409220300973391518089990364726","seed":65713419984205656757704117537694371941515985650409220300973391518089990364726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2207768118 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2207768118' seed=65713419984205656757704117537694371941515985650409220300973391518089990364726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65713419984205656757704117537694371941515985650409220300973391518089990364726 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"7.xbar_stress_all_with_error.11098362029563674255055287577015197571231173037039771081292405606612338944660","seed":11098362029563674255055287577015197571231173037039771081292405606612338944660,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025007764 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2025007764' seed=11098362029563674255055287577015197571231173037039771081292405606612338944660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11098362029563674255055287577015197571231173037039771081292405606612338944660 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"7.xbar_stress_all_with_reset_error.87146918610098025891401072747029246616773020692154625723634638459956331665808","seed":87146918610098025891401072747029246616773020692154625723634638459956331665808,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2164119952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2164119952' seed=87146918610098025891401072747029246616773020692154625723634638459956331665808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87146918610098025891401072747029246616773020692154625723634638459956331665808 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/7.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"8.xbar_smoke.34694564815788778228382896790908214941397149922298448973370141099715808543878","seed":34694564815788778228382896790908214941397149922298448973370141099715808543878,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=190137478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.190137478' seed=34694564815788778228382896790908214941397149922298448973370141099715808543878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34694564815788778228382896790908214941397149922298448973370141099715808543878 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"8.xbar_smoke_zero_delays.109583574087639993809861567190524055757844907437976185149059506050701932446935","seed":109583574087639993809861567190524055757844907437976185149059506050701932446935,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3878765783 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3878765783' seed=109583574087639993809861567190524055757844907437976185149059506050701932446935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109583574087639993809861567190524055757844907437976185149059506050701932446935 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"8.xbar_smoke_large_delays.13959615714023895380586297163878753423660805728494424275322279671125210903020","seed":13959615714023895380586297163878753423660805728494424275322279671125210903020,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=566833644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.566833644' seed=13959615714023895380586297163878753423660805728494424275322279671125210903020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13959615714023895380586297163878753423660805728494424275322279671125210903020 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"8.xbar_smoke_slow_rsp.72986294848368725911624831326696733109124166379645372900583809173531019013056","seed":72986294848368725911624831326696733109124166379645372900583809173531019013056,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=692415424 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.692415424' seed=72986294848368725911624831326696733109124166379645372900583809173531019013056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72986294848368725911624831326696733109124166379645372900583809173531019013056 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"8.xbar_random.11170409807447148806018358033747198780042749127845926842092132222005338681859","seed":11170409807447148806018358033747198780042749127845926842092132222005338681859,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3823350275 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3823350275' seed=11170409807447148806018358033747198780042749127845926842092132222005338681859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11170409807447148806018358033747198780042749127845926842092132222005338681859 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"8.xbar_random_zero_delays.86454305873145562417477900729051676033995100022662581202123476048966459042290","seed":86454305873145562417477900729051676033995100022662581202123476048966459042290,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=835168754 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.835168754' seed=86454305873145562417477900729051676033995100022662581202123476048966459042290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86454305873145562417477900729051676033995100022662581202123476048966459042290 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"8.xbar_random_large_delays.44780053312473775719577793300290056860079650121024905844959140095119911222951","seed":44780053312473775719577793300290056860079650121024905844959140095119911222951,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556727975 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.556727975' seed=44780053312473775719577793300290056860079650121024905844959140095119911222951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44780053312473775719577793300290056860079650121024905844959140095119911222951 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"8.xbar_random_slow_rsp.17523154695604318447037575597597913105820995281213406849697399320010870292271","seed":17523154695604318447037575597597913105820995281213406849697399320010870292271,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3582263087 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3582263087' seed=17523154695604318447037575597597913105820995281213406849697399320010870292271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17523154695604318447037575597597913105820995281213406849697399320010870292271 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"8.xbar_access_same_device.83369815437044969978672142668769703192906133940455293154420729083354087893122","seed":83369815437044969978672142668769703192906133940455293154420729083354087893122,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3311347842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3311347842' seed=83369815437044969978672142668769703192906133940455293154420729083354087893122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83369815437044969978672142668769703192906133940455293154420729083354087893122 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"8.xbar_access_same_device_slow_rsp.8321035401199015009622999283195537755853273655758132645270757086454357337118","seed":8321035401199015009622999283195537755853273655758132645270757086454357337118,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2698159134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2698159134' seed=8321035401199015009622999283195537755853273655758132645270757086454357337118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8321035401199015009622999283195537755853273655758132645270757086454357337118 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"8.xbar_same_source.100563477998652570449858471558959309090398564202146210688629045780168578374064","seed":100563477998652570449858471558959309090398564202146210688629045780168578374064,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526222768 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2526222768' seed=100563477998652570449858471558959309090398564202146210688629045780168578374064 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100563477998652570449858471558959309090398564202146210688629045780168578374064 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"8.xbar_error_random.29873536991409311082564614620117469271643192961173498314015495725837769773915","seed":29873536991409311082564614620117469271643192961173498314015495725837769773915,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4217115483 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.4217115483' seed=29873536991409311082564614620117469271643192961173498314015495725837769773915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29873536991409311082564614620117469271643192961173498314015495725837769773915 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"8.xbar_unmapped_addr.65586406102420523805016156684288035230541804969132000359697203090100997735790","seed":65586406102420523805016156684288035230541804969132000359697203090100997735790,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3238151534 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3238151534' seed=65586406102420523805016156684288035230541804969132000359697203090100997735790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65586406102420523805016156684288035230541804969132000359697203090100997735790 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"8.xbar_error_and_unmapped_addr.95479348833864039327394925843626519085652504828646518821535110945333452599457","seed":95479348833864039327394925843626519085652504828646518821535110945333452599457,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695150241 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1695150241' seed=95479348833864039327394925843626519085652504828646518821535110945333452599457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95479348833864039327394925843626519085652504828646518821535110945333452599457 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"8.xbar_stress_all.15095553192331737644000831838354949924682481113662035819168603976264523087205","seed":15095553192331737644000831838354949924682481113662035819168603976264523087205,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2989129061 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2989129061' seed=15095553192331737644000831838354949924682481113662035819168603976264523087205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15095553192331737644000831838354949924682481113662035819168603976264523087205 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"8.xbar_stress_all_with_rand_reset.55859684638848613490256192309562774372203475052983150494321597524422415326573","seed":55859684638848613490256192309562774372203475052983150494321597524422415326573,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312346989 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2312346989' seed=55859684638848613490256192309562774372203475052983150494321597524422415326573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55859684638848613490256192309562774372203475052983150494321597524422415326573 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"8.xbar_stress_all_with_error.105032504199438952464080757849249824400865781033201029984988096170284291785630","seed":105032504199438952464080757849249824400865781033201029984988096170284291785630,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2467890078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2467890078' seed=105032504199438952464080757849249824400865781033201029984988096170284291785630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105032504199438952464080757849249824400865781033201029984988096170284291785630 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"8.xbar_stress_all_with_reset_error.46409538982063850460014629116390047923607185930726933157688593470624129098241","seed":46409538982063850460014629116390047923607185930726933157688593470624129098241,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28844545 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.28844545' seed=46409538982063850460014629116390047923607185930726933157688593470624129098241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46409538982063850460014629116390047923607185930726933157688593470624129098241 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/8.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"9.xbar_smoke.1918869658708382627502363851912091160206311958343210413855272481228287109735","seed":1918869658708382627502363851912091160206311958343210413855272481228287109735,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1696590439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1696590439' seed=1918869658708382627502363851912091160206311958343210413855272481228287109735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1918869658708382627502363851912091160206311958343210413855272481228287109735 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"9.xbar_smoke_zero_delays.66480309592386655708367754767198234651902805620567443302414701264216075900686","seed":66480309592386655708367754767198234651902805620567443302414701264216075900686,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2489161486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2489161486' seed=66480309592386655708367754767198234651902805620567443302414701264216075900686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66480309592386655708367754767198234651902805620567443302414701264216075900686 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"9.xbar_smoke_large_delays.94054833706380658181155320742422185526291490369998534185126551108663412829456","seed":94054833706380658181155320742422185526291490369998534185126551108663412829456,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2654252304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2654252304' seed=94054833706380658181155320742422185526291490369998534185126551108663412829456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94054833706380658181155320742422185526291490369998534185126551108663412829456 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"9.xbar_smoke_slow_rsp.17775968871004968516968800091619907202697023472082803885818912982578680864187","seed":17775968871004968516968800091619907202697023472082803885818912982578680864187,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1074568635 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1074568635' seed=17775968871004968516968800091619907202697023472082803885818912982578680864187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17775968871004968516968800091619907202697023472082803885818912982578680864187 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"9.xbar_random.80674434912797442853338566101220327696162282976742824512219849177767642965758","seed":80674434912797442853338566101220327696162282976742824512219849177767642965758,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376823038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1376823038' seed=80674434912797442853338566101220327696162282976742824512219849177767642965758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80674434912797442853338566101220327696162282976742824512219849177767642965758 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"9.xbar_random_zero_delays.12135721632136209179228826079765955353782473749869745414934898172905361200655","seed":12135721632136209179228826079765955353782473749869745414934898172905361200655,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3112654351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3112654351' seed=12135721632136209179228826079765955353782473749869745414934898172905361200655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12135721632136209179228826079765955353782473749869745414934898172905361200655 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"9.xbar_random_large_delays.15830336954418072870851551068537387440999526243094919858108157421865527330760","seed":15830336954418072870851551068537387440999526243094919858108157421865527330760,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027762632 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4027762632' seed=15830336954418072870851551068537387440999526243094919858108157421865527330760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15830336954418072870851551068537387440999526243094919858108157421865527330760 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"9.xbar_random_slow_rsp.108672181452080683712792708908391697563813696419278082123170997211693441428976","seed":108672181452080683712792708908391697563813696419278082123170997211693441428976,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3535351280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3535351280' seed=108672181452080683712792708908391697563813696419278082123170997211693441428976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108672181452080683712792708908391697563813696419278082123170997211693441428976 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"9.xbar_access_same_device.77373243793819485826602421261677712633312952009071195304554291325396110210136","seed":77373243793819485826602421261677712633312952009071195304554291325396110210136,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1419441240 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1419441240' seed=77373243793819485826602421261677712633312952009071195304554291325396110210136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77373243793819485826602421261677712633312952009071195304554291325396110210136 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"9.xbar_access_same_device_slow_rsp.57373995071718768521908015645908874773498330110210140123704507143074580515081","seed":57373995071718768521908015645908874773498330110210140123704507143074580515081,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2693515529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2693515529' seed=57373995071718768521908015645908874773498330110210140123704507143074580515081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57373995071718768521908015645908874773498330110210140123704507143074580515081 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"9.xbar_same_source.72390361947318369577550036102159370310025152534418991964057059005304578975282","seed":72390361947318369577550036102159370310025152534418991964057059005304578975282,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=839853618 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.839853618' seed=72390361947318369577550036102159370310025152534418991964057059005304578975282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72390361947318369577550036102159370310025152534418991964057059005304578975282 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"9.xbar_error_random.60534990275619779438470324116752675614971432481836112562863627721940503246173","seed":60534990275619779438470324116752675614971432481836112562863627721940503246173,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334878557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3334878557' seed=60534990275619779438470324116752675614971432481836112562863627721940503246173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60534990275619779438470324116752675614971432481836112562863627721940503246173 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"9.xbar_unmapped_addr.69249102470228571057642074691110967381346775185846320626688056856754108617708","seed":69249102470228571057642074691110967381346775185846320626688056856754108617708,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=398054380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.398054380' seed=69249102470228571057642074691110967381346775185846320626688056856754108617708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69249102470228571057642074691110967381346775185846320626688056856754108617708 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"9.xbar_error_and_unmapped_addr.111097042917687211896636899805205919131537405324946236780614193178928664509039","seed":111097042917687211896636899805205919131537405324946236780614193178928664509039,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3531307631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3531307631' seed=111097042917687211896636899805205919131537405324946236780614193178928664509039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111097042917687211896636899805205919131537405324946236780614193178928664509039 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"9.xbar_stress_all.43806498438479343063310342724185908167090271716820984518802277042409470388894","seed":43806498438479343063310342724185908167090271716820984518802277042409470388894,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530620574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1530620574' seed=43806498438479343063310342724185908167090271716820984518802277042409470388894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43806498438479343063310342724185908167090271716820984518802277042409470388894 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"9.xbar_stress_all_with_rand_reset.29874677740563476640166831760200690484867008481782671675042796260277195557247","seed":29874677740563476640166831760200690484867008481782671675042796260277195557247,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1078380927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1078380927' seed=29874677740563476640166831760200690484867008481782671675042796260277195557247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29874677740563476640166831760200690484867008481782671675042796260277195557247 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"9.xbar_stress_all_with_error.9398946830981384987967155945117527395097711581813524282399752496030627533362","seed":9398946830981384987967155945117527395097711581813524282399752496030627533362,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3717075506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3717075506' seed=9398946830981384987967155945117527395097711581813524282399752496030627533362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9398946830981384987967155945117527395097711581813524282399752496030627533362 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"9.xbar_stress_all_with_reset_error.39992289357827709475778497450300287302437084563726771381229331968149343904793","seed":39992289357827709475778497450300287302437084563726771381229331968149343904793,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2247566361 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.2247566361' seed=39992289357827709475778497450300287302437084563726771381229331968149343904793 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39992289357827709475778497450300287302437084563726771381229331968149343904793 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/9.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"10.xbar_smoke.9421879657844094421578551059428486400106125994956346055289878793137168141096","seed":9421879657844094421578551059428486400106125994956346055289878793137168141096,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171526952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.171526952' seed=9421879657844094421578551059428486400106125994956346055289878793137168141096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9421879657844094421578551059428486400106125994956346055289878793137168141096 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"10.xbar_smoke_zero_delays.50320291445765615210641915608793307986875052815372750013357336420437067582351","seed":50320291445765615210641915608793307986875052815372750013357336420437067582351,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=824986511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.824986511' seed=50320291445765615210641915608793307986875052815372750013357336420437067582351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50320291445765615210641915608793307986875052815372750013357336420437067582351 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"10.xbar_smoke_large_delays.106352365505980058577001226748451558092257571527532709396336451721904834191901","seed":106352365505980058577001226748451558092257571527532709396336451721904834191901,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2997330461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2997330461' seed=106352365505980058577001226748451558092257571527532709396336451721904834191901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106352365505980058577001226748451558092257571527532709396336451721904834191901 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"10.xbar_smoke_slow_rsp.43024929947508677000115432488185225060543625111056232120706365735932979862159","seed":43024929947508677000115432488185225060543625111056232120706365735932979862159,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=329538191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.329538191' seed=43024929947508677000115432488185225060543625111056232120706365735932979862159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43024929947508677000115432488185225060543625111056232120706365735932979862159 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"10.xbar_random.50536160403694251409148710405505187719592523538124019375403944648007437820529","seed":50536160403694251409148710405505187719592523538124019375403944648007437820529,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=183018097 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.183018097' seed=50536160403694251409148710405505187719592523538124019375403944648007437820529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50536160403694251409148710405505187719592523538124019375403944648007437820529 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"10.xbar_random_zero_delays.17993846749220825962281156072053409526649140886931181683318548999861897392812","seed":17993846749220825962281156072053409526649140886931181683318548999861897392812,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641331884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.641331884' seed=17993846749220825962281156072053409526649140886931181683318548999861897392812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17993846749220825962281156072053409526649140886931181683318548999861897392812 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"10.xbar_random_large_delays.93975098260885657329851187436248184979137817255181837407416135029423273601365","seed":93975098260885657329851187436248184979137817255181837407416135029423273601365,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2824005973 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2824005973' seed=93975098260885657329851187436248184979137817255181837407416135029423273601365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93975098260885657329851187436248184979137817255181837407416135029423273601365 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"10.xbar_random_slow_rsp.4250868587519541085702388792548237052245531803760582484162986752380454618985","seed":4250868587519541085702388792548237052245531803760582484162986752380454618985,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=940361577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.940361577' seed=4250868587519541085702388792548237052245531803760582484162986752380454618985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4250868587519541085702388792548237052245531803760582484162986752380454618985 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"10.xbar_access_same_device.33504773752854908873338933408995025924314309631745485688824746472867996788139","seed":33504773752854908873338933408995025924314309631745485688824746472867996788139,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1481270699 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1481270699' seed=33504773752854908873338933408995025924314309631745485688824746472867996788139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33504773752854908873338933408995025924314309631745485688824746472867996788139 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"10.xbar_access_same_device_slow_rsp.25197076185786968694172324606367715338379530897460670403087277502192157075320","seed":25197076185786968694172324606367715338379530897460670403087277502192157075320,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3670419320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3670419320' seed=25197076185786968694172324606367715338379530897460670403087277502192157075320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25197076185786968694172324606367715338379530897460670403087277502192157075320 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"10.xbar_same_source.41896360162018779143235386296849351711897536547821729838097532783156271598622","seed":41896360162018779143235386296849351711897536547821729838097532783156271598622,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2709867550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2709867550' seed=41896360162018779143235386296849351711897536547821729838097532783156271598622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41896360162018779143235386296849351711897536547821729838097532783156271598622 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"10.xbar_error_random.69308009040906875058637751741000818359619335715123130224323978501165241597789","seed":69308009040906875058637751741000818359619335715123130224323978501165241597789,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=397672285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.397672285' seed=69308009040906875058637751741000818359619335715123130224323978501165241597789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69308009040906875058637751741000818359619335715123130224323978501165241597789 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"10.xbar_unmapped_addr.25846868188200973609344472102952433819493130664530450888833619157427086595190","seed":25846868188200973609344472102952433819493130664530450888833619157427086595190,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2129564790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2129564790' seed=25846868188200973609344472102952433819493130664530450888833619157427086595190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25846868188200973609344472102952433819493130664530450888833619157427086595190 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"10.xbar_error_and_unmapped_addr.21151684175701706561033569396430899437060943729479744909079962577016487058810","seed":21151684175701706561033569396430899437060943729479744909079962577016487058810,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064372602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3064372602' seed=21151684175701706561033569396430899437060943729479744909079962577016487058810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21151684175701706561033569396430899437060943729479744909079962577016487058810 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"10.xbar_stress_all.87429976832491044062421870121957575858356959405261839691675554350503953589307","seed":87429976832491044062421870121957575858356959405261839691675554350503953589307,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1522689083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1522689083' seed=87429976832491044062421870121957575858356959405261839691675554350503953589307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87429976832491044062421870121957575858356959405261839691675554350503953589307 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"10.xbar_stress_all_with_rand_reset.4540335222196358694846346854051747714533787574589031552708209173492642330953","seed":4540335222196358694846346854051747714533787574589031552708209173492642330953,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2918168905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2918168905' seed=4540335222196358694846346854051747714533787574589031552708209173492642330953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4540335222196358694846346854051747714533787574589031552708209173492642330953 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"10.xbar_stress_all_with_error.43021897527694399425691909882100043437881019336774064186419627610257529236976","seed":43021897527694399425691909882100043437881019336774064186419627610257529236976,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2723671536 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2723671536' seed=43021897527694399425691909882100043437881019336774064186419627610257529236976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43021897527694399425691909882100043437881019336774064186419627610257529236976 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"10.xbar_stress_all_with_reset_error.32487399152902495739649950638909861093264023258229866683143708072751955541714","seed":32487399152902495739649950638909861093264023258229866683143708072751955541714,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3073212114 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3073212114' seed=32487399152902495739649950638909861093264023258229866683143708072751955541714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32487399152902495739649950638909861093264023258229866683143708072751955541714 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/10.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"11.xbar_smoke.111064554429090954957910184014929290019793484597858129808821302879344703107255","seed":111064554429090954957910184014929290019793484597858129808821302879344703107255,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=881389751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.881389751' seed=111064554429090954957910184014929290019793484597858129808821302879344703107255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111064554429090954957910184014929290019793484597858129808821302879344703107255 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"11.xbar_smoke_zero_delays.9975172348340350594914136306513414220134277927397809423849579818383473987328","seed":9975172348340350594914136306513414220134277927397809423849579818383473987328,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3141095168 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3141095168' seed=9975172348340350594914136306513414220134277927397809423849579818383473987328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9975172348340350594914136306513414220134277927397809423849579818383473987328 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"11.xbar_smoke_large_delays.77690057670574260537048828111569734399422989335701877950204272552378576867317","seed":77690057670574260537048828111569734399422989335701877950204272552378576867317,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3660779509 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3660779509' seed=77690057670574260537048828111569734399422989335701877950204272552378576867317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77690057670574260537048828111569734399422989335701877950204272552378576867317 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"11.xbar_smoke_slow_rsp.99733148917626979126769980817469375050330982021187443627839566661951200902324","seed":99733148917626979126769980817469375050330982021187443627839566661951200902324,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44776628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.44776628' seed=99733148917626979126769980817469375050330982021187443627839566661951200902324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99733148917626979126769980817469375050330982021187443627839566661951200902324 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"11.xbar_random.19668664647825035656971385028507242653962609145078187134279990680153677222951","seed":19668664647825035656971385028507242653962609145078187134279990680153677222951,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454494759 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1454494759' seed=19668664647825035656971385028507242653962609145078187134279990680153677222951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19668664647825035656971385028507242653962609145078187134279990680153677222951 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"11.xbar_random_zero_delays.87589524215649001683678990089200662249914401306753719355914926629941113504257","seed":87589524215649001683678990089200662249914401306753719355914926629941113504257,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=272089601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.272089601' seed=87589524215649001683678990089200662249914401306753719355914926629941113504257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87589524215649001683678990089200662249914401306753719355914926629941113504257 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"11.xbar_random_large_delays.58005252438723130559512392257588709741696319961460709772106377988953849436342","seed":58005252438723130559512392257588709741696319961460709772106377988953849436342,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=438278326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.438278326' seed=58005252438723130559512392257588709741696319961460709772106377988953849436342 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58005252438723130559512392257588709741696319961460709772106377988953849436342 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"11.xbar_random_slow_rsp.58763486206643489989471095729702012639042694367544411322149083464356275143966","seed":58763486206643489989471095729702012639042694367544411322149083464356275143966,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023998750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2023998750' seed=58763486206643489989471095729702012639042694367544411322149083464356275143966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58763486206643489989471095729702012639042694367544411322149083464356275143966 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"11.xbar_access_same_device.42177655644471943699941091662830327874156124234522700868463633277638620101864","seed":42177655644471943699941091662830327874156124234522700868463633277638620101864,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2525117672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2525117672' seed=42177655644471943699941091662830327874156124234522700868463633277638620101864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42177655644471943699941091662830327874156124234522700868463633277638620101864 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"11.xbar_access_same_device_slow_rsp.41957859419308361103377515842944996727763384593376459549120084135976522855842","seed":41957859419308361103377515842944996727763384593376459549120084135976522855842,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=544847266 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.544847266' seed=41957859419308361103377515842944996727763384593376459549120084135976522855842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41957859419308361103377515842944996727763384593376459549120084135976522855842 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"11.xbar_same_source.6224367249896294501694436739092907258736135051959952446148307595021917228226","seed":6224367249896294501694436739092907258736135051959952446148307595021917228226,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=547228866 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.547228866' seed=6224367249896294501694436739092907258736135051959952446148307595021917228226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6224367249896294501694436739092907258736135051959952446148307595021917228226 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"11.xbar_error_random.113014718073014219983581703677099962169008669923044086308215198786688401315648","seed":113014718073014219983581703677099962169008669923044086308215198786688401315648,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3216545600 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3216545600' seed=113014718073014219983581703677099962169008669923044086308215198786688401315648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113014718073014219983581703677099962169008669923044086308215198786688401315648 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"11.xbar_unmapped_addr.35293911282109540925934561398854105462738199458532863674180519343212207365022","seed":35293911282109540925934561398854105462738199458532863674180519343212207365022,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2461096862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2461096862' seed=35293911282109540925934561398854105462738199458532863674180519343212207365022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35293911282109540925934561398854105462738199458532863674180519343212207365022 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"11.xbar_error_and_unmapped_addr.80219684332994052649468963107947243162733170804209534309566087249437248637088","seed":80219684332994052649468963107947243162733170804209534309566087249437248637088,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2923874464 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2923874464' seed=80219684332994052649468963107947243162733170804209534309566087249437248637088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80219684332994052649468963107947243162733170804209534309566087249437248637088 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"11.xbar_stress_all.15576400774533249019161903427275846870868602726072647391730174811624566588818","seed":15576400774533249019161903427275846870868602726072647391730174811624566588818,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292455826 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.292455826' seed=15576400774533249019161903427275846870868602726072647391730174811624566588818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15576400774533249019161903427275846870868602726072647391730174811624566588818 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"11.xbar_stress_all_with_rand_reset.46496820689542464570253093777201709501905218914568800943695278025673540984602","seed":46496820689542464570253093777201709501905218914568800943695278025673540984602,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706385178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.1706385178' seed=46496820689542464570253093777201709501905218914568800943695278025673540984602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46496820689542464570253093777201709501905218914568800943695278025673540984602 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"11.xbar_stress_all_with_error.96071431869579365858581800894775768304689422464917074477873469553991162238363","seed":96071431869579365858581800894775768304689422464917074477873469553991162238363,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=876320155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.876320155' seed=96071431869579365858581800894775768304689422464917074477873469553991162238363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96071431869579365858581800894775768304689422464917074477873469553991162238363 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"11.xbar_stress_all_with_reset_error.32741988584638646994313309928620157004778555326081209094556854829636733691956","seed":32741988584638646994313309928620157004778555326081209094556854829636733691956,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=770500660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.770500660' seed=32741988584638646994313309928620157004778555326081209094556854829636733691956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32741988584638646994313309928620157004778555326081209094556854829636733691956 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/11.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"12.xbar_smoke.57557504337832477366092982653877667117165040809970593902960056673596022772487","seed":57557504337832477366092982653877667117165040809970593902960056673596022772487,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919917319 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.919917319' seed=57557504337832477366092982653877667117165040809970593902960056673596022772487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57557504337832477366092982653877667117165040809970593902960056673596022772487 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"12.xbar_smoke_zero_delays.22211832724510914029419882669511538417024104512076884847143880995482501505400","seed":22211832724510914029419882669511538417024104512076884847143880995482501505400,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662036856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.662036856' seed=22211832724510914029419882669511538417024104512076884847143880995482501505400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22211832724510914029419882669511538417024104512076884847143880995482501505400 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"12.xbar_smoke_large_delays.2713278372857998813931418306994465835133967475485151926213646472057180157337","seed":2713278372857998813931418306994465835133967475485151926213646472057180157337,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4184110489 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4184110489' seed=2713278372857998813931418306994465835133967475485151926213646472057180157337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2713278372857998813931418306994465835133967475485151926213646472057180157337 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"12.xbar_smoke_slow_rsp.28339870010411855907480417585381390577061954338173164170380639057934595714364","seed":28339870010411855907480417585381390577061954338173164170380639057934595714364,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180208956 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4180208956' seed=28339870010411855907480417585381390577061954338173164170380639057934595714364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28339870010411855907480417585381390577061954338173164170380639057934595714364 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"12.xbar_random.37795578502425711816969000762365521984956108095916173694179301088280658904893","seed":37795578502425711816969000762365521984956108095916173694179301088280658904893,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818298173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1818298173' seed=37795578502425711816969000762365521984956108095916173694179301088280658904893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37795578502425711816969000762365521984956108095916173694179301088280658904893 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"12.xbar_random_zero_delays.47631300730953209184781940686021081324253259272916406164477298895604597706698","seed":47631300730953209184781940686021081324253259272916406164477298895604597706698,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4207726538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4207726538' seed=47631300730953209184781940686021081324253259272916406164477298895604597706698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47631300730953209184781940686021081324253259272916406164477298895604597706698 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"12.xbar_random_large_delays.78044060438169142424077118033695910741417077623709030602943079745294985744250","seed":78044060438169142424077118033695910741417077623709030602943079745294985744250,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2680049530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2680049530' seed=78044060438169142424077118033695910741417077623709030602943079745294985744250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78044060438169142424077118033695910741417077623709030602943079745294985744250 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"12.xbar_random_slow_rsp.23045008420794167779940281540972671563213250211484191315680645573170904178344","seed":23045008420794167779940281540972671563213250211484191315680645573170904178344,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156825256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4156825256' seed=23045008420794167779940281540972671563213250211484191315680645573170904178344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23045008420794167779940281540972671563213250211484191315680645573170904178344 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"12.xbar_access_same_device.98487162990921798269187745125102564732690830568939985744472231354126450494366","seed":98487162990921798269187745125102564732690830568939985744472231354126450494366,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1053232030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1053232030' seed=98487162990921798269187745125102564732690830568939985744472231354126450494366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98487162990921798269187745125102564732690830568939985744472231354126450494366 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"12.xbar_access_same_device_slow_rsp.61632741464289045810553278674234894877249752087299452731833591130795256479531","seed":61632741464289045810553278674234894877249752087299452731833591130795256479531,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3864166187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3864166187' seed=61632741464289045810553278674234894877249752087299452731833591130795256479531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61632741464289045810553278674234894877249752087299452731833591130795256479531 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"12.xbar_same_source.85950520567400528638924059106962571003021971948655490246124270091857575032633","seed":85950520567400528638924059106962571003021971948655490246124270091857575032633,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484170041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3484170041' seed=85950520567400528638924059106962571003021971948655490246124270091857575032633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85950520567400528638924059106962571003021971948655490246124270091857575032633 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"12.xbar_error_random.61062234960084692098606750189009622759710856036562429746111212938847032215638","seed":61062234960084692098606750189009622759710856036562429746111212938847032215638,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1071155286 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1071155286' seed=61062234960084692098606750189009622759710856036562429746111212938847032215638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61062234960084692098606750189009622759710856036562429746111212938847032215638 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"12.xbar_unmapped_addr.70302450103619836617581991314477697417042983264349242378538421465445914810177","seed":70302450103619836617581991314477697417042983264349242378538421465445914810177,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121804609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.121804609' seed=70302450103619836617581991314477697417042983264349242378538421465445914810177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70302450103619836617581991314477697417042983264349242378538421465445914810177 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"12.xbar_error_and_unmapped_addr.58446667792561992596074836725878531831279885353289015458792185125340807369887","seed":58446667792561992596074836725878531831279885353289015458792185125340807369887,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6231199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.6231199' seed=58446667792561992596074836725878531831279885353289015458792185125340807369887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58446667792561992596074836725878531831279885353289015458792185125340807369887 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"12.xbar_stress_all.93341602517179617283925011075632463318647200585980892580463804596378837541972","seed":93341602517179617283925011075632463318647200585980892580463804596378837541972,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1082745940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1082745940' seed=93341602517179617283925011075632463318647200585980892580463804596378837541972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93341602517179617283925011075632463318647200585980892580463804596378837541972 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"12.xbar_stress_all_with_rand_reset.107459895712185326741743034354586990049759333478444463991679952770105426778126","seed":107459895712185326741743034354586990049759333478444463991679952770105426778126,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3173980174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.3173980174' seed=107459895712185326741743034354586990049759333478444463991679952770105426778126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107459895712185326741743034354586990049759333478444463991679952770105426778126 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"12.xbar_stress_all_with_error.90992011392638484657962704583701218705458226246649654383094973521114806137356","seed":90992011392638484657962704583701218705458226246649654383094973521114806137356,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1131721228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1131721228' seed=90992011392638484657962704583701218705458226246649654383094973521114806137356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90992011392638484657962704583701218705458226246649654383094973521114806137356 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"12.xbar_stress_all_with_reset_error.99315307173275156270466844723504672363431429064521152832173860855784626515165","seed":99315307173275156270466844723504672363431429064521152832173860855784626515165,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558141149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3558141149' seed=99315307173275156270466844723504672363431429064521152832173860855784626515165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99315307173275156270466844723504672363431429064521152832173860855784626515165 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/12.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"13.xbar_smoke.78089522326289604799309238655591711834363386800304043463201177835182285448619","seed":78089522326289604799309238655591711834363386800304043463201177835182285448619,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2425677227 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2425677227' seed=78089522326289604799309238655591711834363386800304043463201177835182285448619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78089522326289604799309238655591711834363386800304043463201177835182285448619 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"13.xbar_smoke_zero_delays.17989012129446243187761190934636769791785630761862513500390679797751637523688","seed":17989012129446243187761190934636769791785630761862513500390679797751637523688,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4115578088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4115578088' seed=17989012129446243187761190934636769791785630761862513500390679797751637523688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17989012129446243187761190934636769791785630761862513500390679797751637523688 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"13.xbar_smoke_large_delays.107426432842916542737959053480760000554560118599730282676639603173384724338930","seed":107426432842916542737959053480760000554560118599730282676639603173384724338930,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3247626482 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3247626482' seed=107426432842916542737959053480760000554560118599730282676639603173384724338930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107426432842916542737959053480760000554560118599730282676639603173384724338930 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"13.xbar_smoke_slow_rsp.115050975308970214524405400756994927183617475968871412872375219009687384587530","seed":115050975308970214524405400756994927183617475968871412872375219009687384587530,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936293130 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1936293130' seed=115050975308970214524405400756994927183617475968871412872375219009687384587530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115050975308970214524405400756994927183617475968871412872375219009687384587530 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"13.xbar_random.93045829151455124634941796825483274095403044848100912721908664309553143151681","seed":93045829151455124634941796825483274095403044848100912721908664309553143151681,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3209624641 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3209624641' seed=93045829151455124634941796825483274095403044848100912721908664309553143151681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93045829151455124634941796825483274095403044848100912721908664309553143151681 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"13.xbar_random_zero_delays.40507570777274811612466282680040093597974130390404927085291869106030525121419","seed":40507570777274811612466282680040093597974130390404927085291869106030525121419,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1315275659 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1315275659' seed=40507570777274811612466282680040093597974130390404927085291869106030525121419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40507570777274811612466282680040093597974130390404927085291869106030525121419 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"13.xbar_random_large_delays.42091972727968866168348189515779878151959358003577592669455784588452956738877","seed":42091972727968866168348189515779878151959358003577592669455784588452956738877,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3292009789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3292009789' seed=42091972727968866168348189515779878151959358003577592669455784588452956738877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42091972727968866168348189515779878151959358003577592669455784588452956738877 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"13.xbar_random_slow_rsp.23946668329058565527822519210579243454914621443580731797840052651080491194322","seed":23946668329058565527822519210579243454914621443580731797840052651080491194322,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1761073106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1761073106' seed=23946668329058565527822519210579243454914621443580731797840052651080491194322 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23946668329058565527822519210579243454914621443580731797840052651080491194322 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"13.xbar_access_same_device.32439524160063306940004222870846305648562808801363652325649690878737256530203","seed":32439524160063306940004222870846305648562808801363652325649690878737256530203,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454358811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1454358811' seed=32439524160063306940004222870846305648562808801363652325649690878737256530203 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32439524160063306940004222870846305648562808801363652325649690878737256530203 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"13.xbar_access_same_device_slow_rsp.42723604567888947604806032973713362724307075524606464480428992435764576169980","seed":42723604567888947604806032973713362724307075524606464480428992435764576169980,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556052476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.556052476' seed=42723604567888947604806032973713362724307075524606464480428992435764576169980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42723604567888947604806032973713362724307075524606464480428992435764576169980 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"13.xbar_same_source.108972705566578292996536851357825980204232140702983889271742898793900988928055","seed":108972705566578292996536851357825980204232140702983889271742898793900988928055,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3270742071 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3270742071' seed=108972705566578292996536851357825980204232140702983889271742898793900988928055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108972705566578292996536851357825980204232140702983889271742898793900988928055 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"13.xbar_error_random.65050202279092475765195028798881649233882712994253441121775742356008177563492","seed":65050202279092475765195028798881649233882712994253441121775742356008177563492,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319696228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1319696228' seed=65050202279092475765195028798881649233882712994253441121775742356008177563492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65050202279092475765195028798881649233882712994253441121775742356008177563492 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"13.xbar_unmapped_addr.63587568442238064962215391762397788117944969001627239877026845168065613327904","seed":63587568442238064962215391762397788117944969001627239877026845168065613327904,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=665513504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.665513504' seed=63587568442238064962215391762397788117944969001627239877026845168065613327904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63587568442238064962215391762397788117944969001627239877026845168065613327904 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"13.xbar_error_and_unmapped_addr.98305849298127777213002216483589654589529231714670038276686089940902420818708","seed":98305849298127777213002216483589654589529231714670038276686089940902420818708,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1544170260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1544170260' seed=98305849298127777213002216483589654589529231714670038276686089940902420818708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98305849298127777213002216483589654589529231714670038276686089940902420818708 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"13.xbar_stress_all.33558074983929709074847885594170337507330184021531444487928553362359874760082","seed":33558074983929709074847885594170337507330184021531444487928553362359874760082,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833446802 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1833446802' seed=33558074983929709074847885594170337507330184021531444487928553362359874760082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33558074983929709074847885594170337507330184021531444487928553362359874760082 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"13.xbar_stress_all_with_rand_reset.40480000238144349776542952573953412538902000306430545834142529395893736144756","seed":40480000238144349776542952573953412538902000306430545834142529395893736144756,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3211362164 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.3211362164' seed=40480000238144349776542952573953412538902000306430545834142529395893736144756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40480000238144349776542952573953412538902000306430545834142529395893736144756 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"13.xbar_stress_all_with_error.78821948855085306681349194030378663776931744492192297980389848847725904330410","seed":78821948855085306681349194030378663776931744492192297980389848847725904330410,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3277913770 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3277913770' seed=78821948855085306681349194030378663776931744492192297980389848847725904330410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78821948855085306681349194030378663776931744492192297980389848847725904330410 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"13.xbar_stress_all_with_reset_error.58082417339998674067585545759077899974709324703879279038383892496823993059881","seed":58082417339998674067585545759077899974709324703879279038383892496823993059881,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1184975401 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1184975401' seed=58082417339998674067585545759077899974709324703879279038383892496823993059881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58082417339998674067585545759077899974709324703879279038383892496823993059881 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/13.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"14.xbar_smoke.50067896180001175190448585823469028099794511053302618568112348712664955875937","seed":50067896180001175190448585823469028099794511053302618568112348712664955875937,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69202529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.69202529' seed=50067896180001175190448585823469028099794511053302618568112348712664955875937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50067896180001175190448585823469028099794511053302618568112348712664955875937 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"14.xbar_smoke_zero_delays.31366156632882671252237693927514223141543412497605501534249556613535626511538","seed":31366156632882671252237693927514223141543412497605501534249556613535626511538,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2469741746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2469741746' seed=31366156632882671252237693927514223141543412497605501534249556613535626511538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31366156632882671252237693927514223141543412497605501534249556613535626511538 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"14.xbar_smoke_large_delays.21068208891042144509826767424368613156835968831189590798845520971758424798957","seed":21068208891042144509826767424368613156835968831189590798845520971758424798957,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1757394669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1757394669' seed=21068208891042144509826767424368613156835968831189590798845520971758424798957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21068208891042144509826767424368613156835968831189590798845520971758424798957 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"14.xbar_smoke_slow_rsp.105718284766767455618387133158125580448231781917274326115364375048384733318132","seed":105718284766767455618387133158125580448231781917274326115364375048384733318132,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1806502900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1806502900' seed=105718284766767455618387133158125580448231781917274326115364375048384733318132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105718284766767455618387133158125580448231781917274326115364375048384733318132 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"14.xbar_random.108935633256482694193572409187570993800252608505114739599826113715297604365362","seed":108935633256482694193572409187570993800252608505114739599826113715297604365362,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1128557618 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1128557618' seed=108935633256482694193572409187570993800252608505114739599826113715297604365362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108935633256482694193572409187570993800252608505114739599826113715297604365362 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"14.xbar_random_zero_delays.80577232503891541597610359968456923524809494823480340321854286688995362328862","seed":80577232503891541597610359968456923524809494823480340321854286688995362328862,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942868254 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1942868254' seed=80577232503891541597610359968456923524809494823480340321854286688995362328862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80577232503891541597610359968456923524809494823480340321854286688995362328862 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"14.xbar_random_large_delays.83478581260965656452053915550244444153026935368294220743560999884351422399260","seed":83478581260965656452053915550244444153026935368294220743560999884351422399260,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941687580 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.941687580' seed=83478581260965656452053915550244444153026935368294220743560999884351422399260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83478581260965656452053915550244444153026935368294220743560999884351422399260 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"14.xbar_random_slow_rsp.24658563091338904777404722420957163541284027312427772933550810410238363930995","seed":24658563091338904777404722420957163541284027312427772933550810410238363930995,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3858600307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3858600307' seed=24658563091338904777404722420957163541284027312427772933550810410238363930995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24658563091338904777404722420957163541284027312427772933550810410238363930995 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"14.xbar_access_same_device.22311461683789655001083407954157681944022430271986904228889815837017404808538","seed":22311461683789655001083407954157681944022430271986904228889815837017404808538,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1238048090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1238048090' seed=22311461683789655001083407954157681944022430271986904228889815837017404808538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22311461683789655001083407954157681944022430271986904228889815837017404808538 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"14.xbar_access_same_device_slow_rsp.41810291847397478584742942677046112703791874177877596362895546131383258313163","seed":41810291847397478584742942677046112703791874177877596362895546131383258313163,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554641355 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1554641355' seed=41810291847397478584742942677046112703791874177877596362895546131383258313163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41810291847397478584742942677046112703791874177877596362895546131383258313163 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"14.xbar_same_source.19195973233580754328524403297886151409041315299865301707620954703033401178424","seed":19195973233580754328524403297886151409041315299865301707620954703033401178424,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4075649336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4075649336' seed=19195973233580754328524403297886151409041315299865301707620954703033401178424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19195973233580754328524403297886151409041315299865301707620954703033401178424 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"14.xbar_error_random.69307178501337969076351203501187528350180593397408569845232137212833202414824","seed":69307178501337969076351203501187528350180593397408569845232137212833202414824,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2808587496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2808587496' seed=69307178501337969076351203501187528350180593397408569845232137212833202414824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69307178501337969076351203501187528350180593397408569845232137212833202414824 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"14.xbar_unmapped_addr.86941830201807705959787485252563835853834034742547571422667459657819913260249","seed":86941830201807705959787485252563835853834034742547571422667459657819913260249,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2188709081 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2188709081' seed=86941830201807705959787485252563835853834034742547571422667459657819913260249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86941830201807705959787485252563835853834034742547571422667459657819913260249 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"14.xbar_error_and_unmapped_addr.71739632129086451438115899205580380064650533577413693293120437486212897085405","seed":71739632129086451438115899205580380064650533577413693293120437486212897085405,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719099869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.719099869' seed=71739632129086451438115899205580380064650533577413693293120437486212897085405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71739632129086451438115899205580380064650533577413693293120437486212897085405 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"14.xbar_stress_all.68964188863586436981076511658658443354894327066659106190910440528650429689732","seed":68964188863586436981076511658658443354894327066659106190910440528650429689732,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3698749316 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3698749316' seed=68964188863586436981076511658658443354894327066659106190910440528650429689732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68964188863586436981076511658658443354894327066659106190910440528650429689732 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"14.xbar_stress_all_with_rand_reset.54896303257427569003316705198071541221811036844885961013678694266280065348613","seed":54896303257427569003316705198071541221811036844885961013678694266280065348613,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3838555141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.3838555141' seed=54896303257427569003316705198071541221811036844885961013678694266280065348613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54896303257427569003316705198071541221811036844885961013678694266280065348613 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"14.xbar_stress_all_with_error.73570360050336172767158488816508977147236636103175625805316500048645848160336","seed":73570360050336172767158488816508977147236636103175625805316500048645848160336,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667015248 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.667015248' seed=73570360050336172767158488816508977147236636103175625805316500048645848160336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73570360050336172767158488816508977147236636103175625805316500048645848160336 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"14.xbar_stress_all_with_reset_error.66819929501690992100492659119218661334111914680667862381448092630169125591675","seed":66819929501690992100492659119218661334111914680667862381448092630169125591675,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210156667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3210156667' seed=66819929501690992100492659119218661334111914680667862381448092630169125591675 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66819929501690992100492659119218661334111914680667862381448092630169125591675 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/14.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"15.xbar_smoke.92082048569513666913020746542090291364817970264343240688146887976661342374588","seed":92082048569513666913020746542090291364817970264343240688146887976661342374588,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=690899644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.690899644' seed=92082048569513666913020746542090291364817970264343240688146887976661342374588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92082048569513666913020746542090291364817970264343240688146887976661342374588 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"15.xbar_smoke_zero_delays.52949695200411334680962817695388050910753158649647024121266767926127859518269","seed":52949695200411334680962817695388050910753158649647024121266767926127859518269,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2018954045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2018954045' seed=52949695200411334680962817695388050910753158649647024121266767926127859518269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52949695200411334680962817695388050910753158649647024121266767926127859518269 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"15.xbar_smoke_large_delays.80359956470327580295689685408632449615824168970293142572280770980825901067743","seed":80359956470327580295689685408632449615824168970293142572280770980825901067743,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3378015711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3378015711' seed=80359956470327580295689685408632449615824168970293142572280770980825901067743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80359956470327580295689685408632449615824168970293142572280770980825901067743 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"15.xbar_smoke_slow_rsp.23863155532563232273601274462500250540392696670550223977821128535685339273092","seed":23863155532563232273601274462500250540392696670550223977821128535685339273092,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243576708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4243576708' seed=23863155532563232273601274462500250540392696670550223977821128535685339273092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23863155532563232273601274462500250540392696670550223977821128535685339273092 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"15.xbar_random.63429254554561286453582434043693975783002753283093402580058140471874393576375","seed":63429254554561286453582434043693975783002753283093402580058140471874393576375,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=391222199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.391222199' seed=63429254554561286453582434043693975783002753283093402580058140471874393576375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63429254554561286453582434043693975783002753283093402580058140471874393576375 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"15.xbar_random_zero_delays.66958591755760732003776815202775604340652336223898911158240304114849243411446","seed":66958591755760732003776815202775604340652336223898911158240304114849243411446,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3952292854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3952292854' seed=66958591755760732003776815202775604340652336223898911158240304114849243411446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66958591755760732003776815202775604340652336223898911158240304114849243411446 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"15.xbar_random_large_delays.70821475960008185357210472899909457714759092083094506236002101850468643103546","seed":70821475960008185357210472899909457714759092083094506236002101850468643103546,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3757433658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3757433658' seed=70821475960008185357210472899909457714759092083094506236002101850468643103546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70821475960008185357210472899909457714759092083094506236002101850468643103546 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"15.xbar_random_slow_rsp.98355259938760073961643544503296563867208905286102101321775845262421228093725","seed":98355259938760073961643544503296563867208905286102101321775845262421228093725,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4070932765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4070932765' seed=98355259938760073961643544503296563867208905286102101321775845262421228093725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98355259938760073961643544503296563867208905286102101321775845262421228093725 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"15.xbar_access_same_device.54915588773062368611153597705121028333232187775810860579290089562037783207784","seed":54915588773062368611153597705121028333232187775810860579290089562037783207784,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3063258984 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3063258984' seed=54915588773062368611153597705121028333232187775810860579290089562037783207784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54915588773062368611153597705121028333232187775810860579290089562037783207784 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"15.xbar_access_same_device_slow_rsp.103341902815771204049202195909438092024010620128375859559086657488034480265799","seed":103341902815771204049202195909438092024010620128375859559086657488034480265799,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973506119 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.2973506119' seed=103341902815771204049202195909438092024010620128375859559086657488034480265799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103341902815771204049202195909438092024010620128375859559086657488034480265799 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"15.xbar_same_source.93986133133785740782721200477684272294675907336181729642822867226886760837189","seed":93986133133785740782721200477684272294675907336181729642822867226886760837189,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2254712901 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2254712901' seed=93986133133785740782721200477684272294675907336181729642822867226886760837189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93986133133785740782721200477684272294675907336181729642822867226886760837189 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"15.xbar_error_random.85562387999870477901977706622171242584534573809249467806353476896240261305566","seed":85562387999870477901977706622171242584534573809249467806353476896240261305566,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3944912094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3944912094' seed=85562387999870477901977706622171242584534573809249467806353476896240261305566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85562387999870477901977706622171242584534573809249467806353476896240261305566 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"15.xbar_unmapped_addr.56819785779550027571207020591879789619048328951020109818171662418422559706724","seed":56819785779550027571207020591879789619048328951020109818171662418422559706724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1231326820 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1231326820' seed=56819785779550027571207020591879789619048328951020109818171662418422559706724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56819785779550027571207020591879789619048328951020109818171662418422559706724 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"15.xbar_error_and_unmapped_addr.31670349157297741000538729305450282055452832058929879647791035287983605858230","seed":31670349157297741000538729305450282055452832058929879647791035287983605858230,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=50773942 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.50773942' seed=31670349157297741000538729305450282055452832058929879647791035287983605858230 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31670349157297741000538729305450282055452832058929879647791035287983605858230 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"15.xbar_stress_all.78988981460760626939711693827016351449899990596378472712281629767929860772667","seed":78988981460760626939711693827016351449899990596378472712281629767929860772667,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3356283707 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3356283707' seed=78988981460760626939711693827016351449899990596378472712281629767929860772667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78988981460760626939711693827016351449899990596378472712281629767929860772667 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"15.xbar_stress_all_with_rand_reset.96027432379439939800891649304637153807132060847966070525392741006034359451063","seed":96027432379439939800891649304637153807132060847966070525392741006034359451063,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61504951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.61504951' seed=96027432379439939800891649304637153807132060847966070525392741006034359451063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96027432379439939800891649304637153807132060847966070525392741006034359451063 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"15.xbar_stress_all_with_error.16404260767129546931877401148485163460263709267337069423371402677337336496120","seed":16404260767129546931877401148485163460263709267337069423371402677337336496120,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690039800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2690039800' seed=16404260767129546931877401148485163460263709267337069423371402677337336496120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16404260767129546931877401148485163460263709267337069423371402677337336496120 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"15.xbar_stress_all_with_reset_error.12563386716946696791183433167989487924650506271025930356700276976276502356608","seed":12563386716946696791183433167989487924650506271025930356700276976276502356608,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376920192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.1376920192' seed=12563386716946696791183433167989487924650506271025930356700276976276502356608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12563386716946696791183433167989487924650506271025930356700276976276502356608 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/15.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"16.xbar_smoke.88923810621486083409519777736736049390830020135474353798501522095687457712966","seed":88923810621486083409519777736736049390830020135474353798501522095687457712966,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3559009094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3559009094' seed=88923810621486083409519777736736049390830020135474353798501522095687457712966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88923810621486083409519777736736049390830020135474353798501522095687457712966 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"16.xbar_smoke_zero_delays.26366697001432792162192451782883640963298389486804893974786044661193800368311","seed":26366697001432792162192451782883640963298389486804893974786044661193800368311,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=847200439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.847200439' seed=26366697001432792162192451782883640963298389486804893974786044661193800368311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26366697001432792162192451782883640963298389486804893974786044661193800368311 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"16.xbar_smoke_large_delays.34420613417320001823487298770140926636034430619030835442796660014142219791207","seed":34420613417320001823487298770140926636034430619030835442796660014142219791207,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2079239015 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2079239015' seed=34420613417320001823487298770140926636034430619030835442796660014142219791207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34420613417320001823487298770140926636034430619030835442796660014142219791207 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"16.xbar_smoke_slow_rsp.22881789248117166811152345460255496177909005148497002290003251312841665939444","seed":22881789248117166811152345460255496177909005148497002290003251312841665939444,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154432500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2154432500' seed=22881789248117166811152345460255496177909005148497002290003251312841665939444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22881789248117166811152345460255496177909005148497002290003251312841665939444 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"16.xbar_random.75990721894465743621324818847591313458014349950250180702773327865496212544740","seed":75990721894465743621324818847591313458014349950250180702773327865496212544740,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012500708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3012500708' seed=75990721894465743621324818847591313458014349950250180702773327865496212544740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75990721894465743621324818847591313458014349950250180702773327865496212544740 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"16.xbar_random_zero_delays.99253415761123642043143068670593581824188302918432868673751375512024529003271","seed":99253415761123642043143068670593581824188302918432868673751375512024529003271,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2481742599 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2481742599' seed=99253415761123642043143068670593581824188302918432868673751375512024529003271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99253415761123642043143068670593581824188302918432868673751375512024529003271 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"16.xbar_random_large_delays.11765879959955922054810009274363144650707676758022596394404398127588933285103","seed":11765879959955922054810009274363144650707676758022596394404398127588933285103,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652629743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3652629743' seed=11765879959955922054810009274363144650707676758022596394404398127588933285103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11765879959955922054810009274363144650707676758022596394404398127588933285103 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"16.xbar_random_slow_rsp.54119665832469682702425413343648210986680827690446226449900616765974496754968","seed":54119665832469682702425413343648210986680827690446226449900616765974496754968,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2543664408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2543664408' seed=54119665832469682702425413343648210986680827690446226449900616765974496754968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54119665832469682702425413343648210986680827690446226449900616765974496754968 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"16.xbar_access_same_device.82951937497454776245169155042741083530823129015403850127039804625207841918909","seed":82951937497454776245169155042741083530823129015403850127039804625207841918909,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2254049213 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2254049213' seed=82951937497454776245169155042741083530823129015403850127039804625207841918909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82951937497454776245169155042741083530823129015403850127039804625207841918909 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"16.xbar_access_same_device_slow_rsp.32485461812037861796797004970623503345134449804366610914473425001774115782470","seed":32485461812037861796797004970623503345134449804366610914473425001774115782470,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=270073670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.270073670' seed=32485461812037861796797004970623503345134449804366610914473425001774115782470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32485461812037861796797004970623503345134449804366610914473425001774115782470 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"16.xbar_same_source.26772134567406807493225423932306041622191640929175123791967031413623850732376","seed":26772134567406807493225423932306041622191640929175123791967031413623850732376,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2698447704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2698447704' seed=26772134567406807493225423932306041622191640929175123791967031413623850732376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26772134567406807493225423932306041622191640929175123791967031413623850732376 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"16.xbar_error_random.62483760857041943429986660220286449118588446327070054557879341742707773377905","seed":62483760857041943429986660220286449118588446327070054557879341742707773377905,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3857026417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3857026417' seed=62483760857041943429986660220286449118588446327070054557879341742707773377905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62483760857041943429986660220286449118588446327070054557879341742707773377905 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"16.xbar_unmapped_addr.80366828889225741051120967771601611836437739766353810455638218548101657924783","seed":80366828889225741051120967771601611836437739766353810455638218548101657924783,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3644855471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3644855471' seed=80366828889225741051120967771601611836437739766353810455638218548101657924783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80366828889225741051120967771601611836437739766353810455638218548101657924783 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"16.xbar_error_and_unmapped_addr.32714432272054352745454810512568047325237882271011002921482200805999259410338","seed":32714432272054352745454810512568047325237882271011002921482200805999259410338,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=545775522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.545775522' seed=32714432272054352745454810512568047325237882271011002921482200805999259410338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32714432272054352745454810512568047325237882271011002921482200805999259410338 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"16.xbar_stress_all.101967116484453921888473828793128337623729061804466152106302492916682049579613","seed":101967116484453921888473828793128337623729061804466152106302492916682049579613,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3886410333 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3886410333' seed=101967116484453921888473828793128337623729061804466152106302492916682049579613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101967116484453921888473828793128337623729061804466152106302492916682049579613 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"16.xbar_stress_all_with_rand_reset.57129399638750030811252680290901648094064941667841846734594968091008483738196","seed":57129399638750030811252680290901648094064941667841846734594968091008483738196,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1236550228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1236550228' seed=57129399638750030811252680290901648094064941667841846734594968091008483738196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57129399638750030811252680290901648094064941667841846734594968091008483738196 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"16.xbar_stress_all_with_error.88069314545380554772084569735806638073994134983018925047136208937530744108998","seed":88069314545380554772084569735806638073994134983018925047136208937530744108998,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1572861894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1572861894' seed=88069314545380554772084569735806638073994134983018925047136208937530744108998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88069314545380554772084569735806638073994134983018925047136208937530744108998 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"16.xbar_stress_all_with_reset_error.102781314582821036059269825799060118312513863955292075075707306130903974241468","seed":102781314582821036059269825799060118312513863955292075075707306130903974241468,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1999856828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1999856828' seed=102781314582821036059269825799060118312513863955292075075707306130903974241468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102781314582821036059269825799060118312513863955292075075707306130903974241468 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/16.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"17.xbar_smoke.112600313590990937276420092538256411267408284497830735320290426702094324433478","seed":112600313590990937276420092538256411267408284497830735320290426702094324433478,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3680993862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3680993862' seed=112600313590990937276420092538256411267408284497830735320290426702094324433478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112600313590990937276420092538256411267408284497830735320290426702094324433478 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"17.xbar_smoke_zero_delays.97071790776228968512227114101352284380643616837493038312610366890044945585154","seed":97071790776228968512227114101352284380643616837493038312610366890044945585154,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1843647490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1843647490' seed=97071790776228968512227114101352284380643616837493038312610366890044945585154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97071790776228968512227114101352284380643616837493038312610366890044945585154 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"17.xbar_smoke_large_delays.69061667604581596247057783488391809051896084562089545625334642941472012230020","seed":69061667604581596247057783488391809051896084562089545625334642941472012230020,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495602052 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2495602052' seed=69061667604581596247057783488391809051896084562089545625334642941472012230020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69061667604581596247057783488391809051896084562089545625334642941472012230020 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"17.xbar_smoke_slow_rsp.84155007414223589274821125099957344525800714120439806111444893811915768386865","seed":84155007414223589274821125099957344525800714120439806111444893811915768386865,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043518769 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1043518769' seed=84155007414223589274821125099957344525800714120439806111444893811915768386865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84155007414223589274821125099957344525800714120439806111444893811915768386865 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"17.xbar_random.46148611242744805313943530156063786729126467652374662181537973871800343954657","seed":46148611242744805313943530156063786729126467652374662181537973871800343954657,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3928589537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3928589537' seed=46148611242744805313943530156063786729126467652374662181537973871800343954657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46148611242744805313943530156063786729126467652374662181537973871800343954657 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"17.xbar_random_zero_delays.68658774862625404511796343343150553516610175928981939009848644271478077703154","seed":68658774862625404511796343343150553516610175928981939009848644271478077703154,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3483157490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3483157490' seed=68658774862625404511796343343150553516610175928981939009848644271478077703154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68658774862625404511796343343150553516610175928981939009848644271478077703154 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"17.xbar_random_large_delays.108183490037886383076583400030097991883875595480384776434638105156317427585712","seed":108183490037886383076583400030097991883875595480384776434638105156317427585712,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2963329712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2963329712' seed=108183490037886383076583400030097991883875595480384776434638105156317427585712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108183490037886383076583400030097991883875595480384776434638105156317427585712 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"17.xbar_random_slow_rsp.34704669622308425808531749087533148623846088624149154840199461721714667161170","seed":34704669622308425808531749087533148623846088624149154840199461721714667161170,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2173568594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2173568594' seed=34704669622308425808531749087533148623846088624149154840199461721714667161170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34704669622308425808531749087533148623846088624149154840199461721714667161170 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"17.xbar_access_same_device.79095818448682497257804906347255264154159177981154246598563260762765536092163","seed":79095818448682497257804906347255264154159177981154246598563260762765536092163,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=991518723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.991518723' seed=79095818448682497257804906347255264154159177981154246598563260762765536092163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79095818448682497257804906347255264154159177981154246598563260762765536092163 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"17.xbar_access_same_device_slow_rsp.105689142849214383913797875853507390188092587534924011502793715476950445740580","seed":105689142849214383913797875853507390188092587534924011502793715476950445740580,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251655204 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.3251655204' seed=105689142849214383913797875853507390188092587534924011502793715476950445740580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105689142849214383913797875853507390188092587534924011502793715476950445740580 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"17.xbar_same_source.8014510476264383154201548923158359459158540211921677218842026733848307601848","seed":8014510476264383154201548923158359459158540211921677218842026733848307601848,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812107704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1812107704' seed=8014510476264383154201548923158359459158540211921677218842026733848307601848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8014510476264383154201548923158359459158540211921677218842026733848307601848 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"17.xbar_error_random.71403202738394511019989694073586302391038976752344965641418077971673617993841","seed":71403202738394511019989694073586302391038976752344965641418077971673617993841,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1500713073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1500713073' seed=71403202738394511019989694073586302391038976752344965641418077971673617993841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71403202738394511019989694073586302391038976752344965641418077971673617993841 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"17.xbar_unmapped_addr.2909306798017098489927609963854166024511512654041820247944619637967071837710","seed":2909306798017098489927609963854166024511512654041820247944619637967071837710,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=499744270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.499744270' seed=2909306798017098489927609963854166024511512654041820247944619637967071837710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2909306798017098489927609963854166024511512654041820247944619637967071837710 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"17.xbar_error_and_unmapped_addr.3300394685891333740399400958373425479974626338383514202788411511541995180715","seed":3300394685891333740399400958373425479974626338383514202788411511541995180715,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4121465515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4121465515' seed=3300394685891333740399400958373425479974626338383514202788411511541995180715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3300394685891333740399400958373425479974626338383514202788411511541995180715 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"17.xbar_stress_all.34496843459005126850644472704707056846794083821522348526809910339588200531716","seed":34496843459005126850644472704707056846794083821522348526809910339588200531716,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614377732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3614377732' seed=34496843459005126850644472704707056846794083821522348526809910339588200531716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34496843459005126850644472704707056846794083821522348526809910339588200531716 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"17.xbar_stress_all_with_rand_reset.9442113517580684038594872148806222975483603043122137418310743431938541158575","seed":9442113517580684038594872148806222975483603043122137418310743431938541158575,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1891958959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1891958959' seed=9442113517580684038594872148806222975483603043122137418310743431938541158575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9442113517580684038594872148806222975483603043122137418310743431938541158575 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"17.xbar_stress_all_with_error.87247058041727477834250206555695649153087578296923970218910504654369480691219","seed":87247058041727477834250206555695649153087578296923970218910504654369480691219,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3338063379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3338063379' seed=87247058041727477834250206555695649153087578296923970218910504654369480691219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87247058041727477834250206555695649153087578296923970218910504654369480691219 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"17.xbar_stress_all_with_reset_error.64207369008733027412361405753564448210236024075149607590212818352903944711447","seed":64207369008733027412361405753564448210236024075149607590212818352903944711447,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2534976791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2534976791' seed=64207369008733027412361405753564448210236024075149607590212818352903944711447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64207369008733027412361405753564448210236024075149607590212818352903944711447 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/17.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"18.xbar_smoke.37687404447522438391973525029623996840559661331880828762803871856208564967131","seed":37687404447522438391973525029623996840559661331880828762803871856208564967131,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3920090843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3920090843' seed=37687404447522438391973525029623996840559661331880828762803871856208564967131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37687404447522438391973525029623996840559661331880828762803871856208564967131 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"18.xbar_smoke_zero_delays.2349607111178497964284110719013552970548703258167239406375099880123339713010","seed":2349607111178497964284110719013552970548703258167239406375099880123339713010,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557108210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3557108210' seed=2349607111178497964284110719013552970548703258167239406375099880123339713010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2349607111178497964284110719013552970548703258167239406375099880123339713010 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"18.xbar_smoke_large_delays.4109423063638133047369663929066027801404863343247038484608587387483746092061","seed":4109423063638133047369663929066027801404863343247038484608587387483746092061,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3694281757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3694281757' seed=4109423063638133047369663929066027801404863343247038484608587387483746092061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4109423063638133047369663929066027801404863343247038484608587387483746092061 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"18.xbar_smoke_slow_rsp.105887396225683930546631882174536741259340145658349440296368420255271498307590","seed":105887396225683930546631882174536741259340145658349440296368420255271498307590,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848558598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3848558598' seed=105887396225683930546631882174536741259340145658349440296368420255271498307590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105887396225683930546631882174536741259340145658349440296368420255271498307590 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"18.xbar_random.36256217342256511447589393004801928429982204369139667004562386996220169234422","seed":36256217342256511447589393004801928429982204369139667004562386996220169234422,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2946705398 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2946705398' seed=36256217342256511447589393004801928429982204369139667004562386996220169234422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36256217342256511447589393004801928429982204369139667004562386996220169234422 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"18.xbar_random_zero_delays.8203472693393971859776760610175768993637116688799465482702477560923086236484","seed":8203472693393971859776760610175768993637116688799465482702477560923086236484,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3517033284 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3517033284' seed=8203472693393971859776760610175768993637116688799465482702477560923086236484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8203472693393971859776760610175768993637116688799465482702477560923086236484 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"18.xbar_random_large_delays.14748159546159747116495299930895787083500928707599003112581939596185257569880","seed":14748159546159747116495299930895787083500928707599003112581939596185257569880,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569386072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1569386072' seed=14748159546159747116495299930895787083500928707599003112581939596185257569880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14748159546159747116495299930895787083500928707599003112581939596185257569880 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"18.xbar_random_slow_rsp.106165689873482491573900270192308068348070329623450269310274684497866601057762","seed":106165689873482491573900270192308068348070329623450269310274684497866601057762,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1477234146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1477234146' seed=106165689873482491573900270192308068348070329623450269310274684497866601057762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106165689873482491573900270192308068348070329623450269310274684497866601057762 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"18.xbar_access_same_device.15796465703059669808670619937094649454217403477890985910291454208957669875044","seed":15796465703059669808670619937094649454217403477890985910291454208957669875044,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3827473764 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3827473764' seed=15796465703059669808670619937094649454217403477890985910291454208957669875044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15796465703059669808670619937094649454217403477890985910291454208957669875044 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"18.xbar_access_same_device_slow_rsp.21274893433055872343884932076606302451078960450483574820043673366801529811140","seed":21274893433055872343884932076606302451078960450483574820043673366801529811140,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1023783108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.1023783108' seed=21274893433055872343884932076606302451078960450483574820043673366801529811140 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21274893433055872343884932076606302451078960450483574820043673366801529811140 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"18.xbar_same_source.45413495846943292027523373248303805620026397631565315813828132924844951903678","seed":45413495846943292027523373248303805620026397631565315813828132924844951903678,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176753086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2176753086' seed=45413495846943292027523373248303805620026397631565315813828132924844951903678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45413495846943292027523373248303805620026397631565315813828132924844951903678 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"18.xbar_error_random.70557384051529772400247897909538222688801172532707795595616386817388684876397","seed":70557384051529772400247897909538222688801172532707795595616386817388684876397,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2130811501 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2130811501' seed=70557384051529772400247897909538222688801172532707795595616386817388684876397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70557384051529772400247897909538222688801172532707795595616386817388684876397 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"18.xbar_unmapped_addr.1689427982811016194507343846757166731446331705569587096095253232441649269267","seed":1689427982811016194507343846757166731446331705569587096095253232441649269267,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=255330835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.255330835' seed=1689427982811016194507343846757166731446331705569587096095253232441649269267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1689427982811016194507343846757166731446331705569587096095253232441649269267 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"18.xbar_error_and_unmapped_addr.11824277279766422725745978392349010463987267971072549489300065779115345125280","seed":11824277279766422725745978392349010463987267971072549489300065779115345125280,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905860512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1905860512' seed=11824277279766422725745978392349010463987267971072549489300065779115345125280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11824277279766422725745978392349010463987267971072549489300065779115345125280 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"18.xbar_stress_all.61329401866078263966182564859692374307573286192736580525631645365957672610576","seed":61329401866078263966182564859692374307573286192736580525631645365957672610576,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=986753808 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.986753808' seed=61329401866078263966182564859692374307573286192736580525631645365957672610576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61329401866078263966182564859692374307573286192736580525631645365957672610576 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"18.xbar_stress_all_with_rand_reset.63379384956385684282550876975974530408577189431920435266226229987966937297579","seed":63379384956385684282550876975974530408577189431920435266226229987966937297579,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2339467947 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2339467947' seed=63379384956385684282550876975974530408577189431920435266226229987966937297579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63379384956385684282550876975974530408577189431920435266226229987966937297579 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"18.xbar_stress_all_with_error.65034928585588157045995297106667583476603076828530799760186680467092566615219","seed":65034928585588157045995297106667583476603076828530799760186680467092566615219,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2121180339 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2121180339' seed=65034928585588157045995297106667583476603076828530799760186680467092566615219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65034928585588157045995297106667583476603076828530799760186680467092566615219 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"18.xbar_stress_all_with_reset_error.27416493411014520283866736381648879982205881920161395925202915699338006273657","seed":27416493411014520283866736381648879982205881920161395925202915699338006273657,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=318021241 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.318021241' seed=27416493411014520283866736381648879982205881920161395925202915699338006273657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27416493411014520283866736381648879982205881920161395925202915699338006273657 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/18.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"19.xbar_smoke.34002461450586764993484605958920486938969946852082355804452937006301062180123","seed":34002461450586764993484605958920486938969946852082355804452937006301062180123,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100112667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2100112667' seed=34002461450586764993484605958920486938969946852082355804452937006301062180123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34002461450586764993484605958920486938969946852082355804452937006301062180123 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"19.xbar_smoke_zero_delays.64154821815586155788145043974783667890419272352240397658168549625327955030165","seed":64154821815586155788145043974783667890419272352240397658168549625327955030165,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=506540181 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.506540181' seed=64154821815586155788145043974783667890419272352240397658168549625327955030165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64154821815586155788145043974783667890419272352240397658168549625327955030165 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"19.xbar_smoke_large_delays.35982412491621208191766506041397976376923111309513891769462021224669175720526","seed":35982412491621208191766506041397976376923111309513891769462021224669175720526,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3133778510 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3133778510' seed=35982412491621208191766506041397976376923111309513891769462021224669175720526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35982412491621208191766506041397976376923111309513891769462021224669175720526 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"19.xbar_smoke_slow_rsp.91999104083850513364516270684925940294332704731478353296951859938624221870539","seed":91999104083850513364516270684925940294332704731478353296951859938624221870539,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2413689291 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2413689291' seed=91999104083850513364516270684925940294332704731478353296951859938624221870539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91999104083850513364516270684925940294332704731478353296951859938624221870539 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"19.xbar_random.81233957106822196725157377851354759921048430606147871864543241963515860237366","seed":81233957106822196725157377851354759921048430606147871864543241963515860237366,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194001974 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.194001974' seed=81233957106822196725157377851354759921048430606147871864543241963515860237366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81233957106822196725157377851354759921048430606147871864543241963515860237366 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"19.xbar_random_zero_delays.45057149267119282485736913484601682808034479663228775526570710700187664332304","seed":45057149267119282485736913484601682808034479663228775526570710700187664332304,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=200357392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.200357392' seed=45057149267119282485736913484601682808034479663228775526570710700187664332304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45057149267119282485736913484601682808034479663228775526570710700187664332304 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"19.xbar_random_large_delays.100569409865308817626215387917089877493486686351094647622521353745145294475581","seed":100569409865308817626215387917089877493486686351094647622521353745145294475581,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1217384765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1217384765' seed=100569409865308817626215387917089877493486686351094647622521353745145294475581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100569409865308817626215387917089877493486686351094647622521353745145294475581 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"19.xbar_random_slow_rsp.14319812239068312395944710237855090150387115327466218750904480067942384938816","seed":14319812239068312395944710237855090150387115327466218750904480067942384938816,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177380160 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2177380160' seed=14319812239068312395944710237855090150387115327466218750904480067942384938816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14319812239068312395944710237855090150387115327466218750904480067942384938816 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"19.xbar_access_same_device.35546858519107892795448049082915765012183230000095815834692700840814262880707","seed":35546858519107892795448049082915765012183230000095815834692700840814262880707,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221331395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1221331395' seed=35546858519107892795448049082915765012183230000095815834692700840814262880707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35546858519107892795448049082915765012183230000095815834692700840814262880707 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"19.xbar_access_same_device_slow_rsp.62305176213184831827097998407947765148171551145557584747343481990289626066441","seed":62305176213184831827097998407947765148171551145557584747343481990289626066441,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2452975113 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2452975113' seed=62305176213184831827097998407947765148171551145557584747343481990289626066441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62305176213184831827097998407947765148171551145557584747343481990289626066441 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"19.xbar_same_source.41998661702095754483971889867303323609786744174809388783354800356264077054913","seed":41998661702095754483971889867303323609786744174809388783354800356264077054913,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767185857 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.767185857' seed=41998661702095754483971889867303323609786744174809388783354800356264077054913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41998661702095754483971889867303323609786744174809388783354800356264077054913 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"19.xbar_error_random.6881781831248898738465512878121263811173937558080205557133165912902230986699","seed":6881781831248898738465512878121263811173937558080205557133165912902230986699,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=389402571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.389402571' seed=6881781831248898738465512878121263811173937558080205557133165912902230986699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6881781831248898738465512878121263811173937558080205557133165912902230986699 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"19.xbar_unmapped_addr.58332511019777519263939499269212641680111730201618492409354302334452758616335","seed":58332511019777519263939499269212641680111730201618492409354302334452758616335,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=502405391 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.502405391' seed=58332511019777519263939499269212641680111730201618492409354302334452758616335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58332511019777519263939499269212641680111730201618492409354302334452758616335 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"19.xbar_error_and_unmapped_addr.82501684406783451498508494436475651503261790751375761169632990111577850966850","seed":82501684406783451498508494436475651503261790751375761169632990111577850966850,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1565455170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1565455170' seed=82501684406783451498508494436475651503261790751375761169632990111577850966850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82501684406783451498508494436475651503261790751375761169632990111577850966850 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"19.xbar_stress_all.15678144796573350127818633291855105430342107296525658418312842956324635837421","seed":15678144796573350127818633291855105430342107296525658418312842956324635837421,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224798189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3224798189' seed=15678144796573350127818633291855105430342107296525658418312842956324635837421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15678144796573350127818633291855105430342107296525658418312842956324635837421 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"19.xbar_stress_all_with_rand_reset.15251199542461231277690129544117522070752991626462731887338585385223703348080","seed":15251199542461231277690129544117522070752991626462731887338585385223703348080,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3036791664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3036791664' seed=15251199542461231277690129544117522070752991626462731887338585385223703348080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15251199542461231277690129544117522070752991626462731887338585385223703348080 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"19.xbar_stress_all_with_error.78556872945043085406906036183274767352720455907623992724714261823133227085928","seed":78556872945043085406906036183274767352720455907623992724714261823133227085928,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398993000 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1398993000' seed=78556872945043085406906036183274767352720455907623992724714261823133227085928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78556872945043085406906036183274767352720455907623992724714261823133227085928 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"19.xbar_stress_all_with_reset_error.27655867925306443753391819044883739503632613550747375713140490524967000545586","seed":27655867925306443753391819044883739503632613550747375713140490524967000545586,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966886706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2966886706' seed=27655867925306443753391819044883739503632613550747375713140490524967000545586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27655867925306443753391819044883739503632613550747375713140490524967000545586 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/19.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"20.xbar_access_same_device_slow_rsp.68756387160681388228736346554396855011147033238876742477941230319471702262245","seed":68756387160681388228736346554396855011147033238876742477941230319471702262245,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4166992357 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.4166992357' seed=68756387160681388228736346554396855011147033238876742477941230319471702262245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68756387160681388228736346554396855011147033238876742477941230319471702262245 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"20.xbar_stress_all_with_error.41780376544493040064640424273650950397872642710541323569386655998319677093783","seed":41780376544493040064640424273650950397872642710541323569386655998319677093783,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=587413399 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.587413399' seed=41780376544493040064640424273650950397872642710541323569386655998319677093783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41780376544493040064640424273650950397872642710541323569386655998319677093783 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"20.xbar_stress_all_with_reset_error.85083310355474202093101596700344478019839774430330444574959370879510293572237","seed":85083310355474202093101596700344478019839774430330444574959370879510293572237,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=534833805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.534833805' seed=85083310355474202093101596700344478019839774430330444574959370879510293572237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85083310355474202093101596700344478019839774430330444574959370879510293572237 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/20.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"21.xbar_access_same_device_slow_rsp.26556404557585433473629880546159178732710908112803225752301791552752739388398","seed":26556404557585433473629880546159178732710908112803225752301791552752739388398,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885468654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3885468654' seed=26556404557585433473629880546159178732710908112803225752301791552752739388398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26556404557585433473629880546159178732710908112803225752301791552752739388398 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"21.xbar_stress_all_with_error.3484040354896443709962035565068457583392337587344211030809041789656827737554","seed":3484040354896443709962035565068457583392337587344211030809041789656827737554,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4148475346 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4148475346' seed=3484040354896443709962035565068457583392337587344211030809041789656827737554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3484040354896443709962035565068457583392337587344211030809041789656827737554 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"21.xbar_stress_all_with_reset_error.33926831036600551912689386850826086580648964525102126947067949333624355126855","seed":33926831036600551912689386850826086580648964525102126947067949333624355126855,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336690759 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.336690759' seed=33926831036600551912689386850826086580648964525102126947067949333624355126855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33926831036600551912689386850826086580648964525102126947067949333624355126855 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/21.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"22.xbar_access_same_device_slow_rsp.108676336010652763292520586998148182662449573397088400058684983051236264916634","seed":108676336010652763292520586998148182662449573397088400058684983051236264916634,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1426339482 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1426339482' seed=108676336010652763292520586998148182662449573397088400058684983051236264916634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108676336010652763292520586998148182662449573397088400058684983051236264916634 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"22.xbar_stress_all_with_error.6765694551865339772781037963321671738993639205313158364101181754253793856838","seed":6765694551865339772781037963321671738993639205313158364101181754253793856838,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250621766 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3250621766' seed=6765694551865339772781037963321671738993639205313158364101181754253793856838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6765694551865339772781037963321671738993639205313158364101181754253793856838 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"22.xbar_stress_all_with_reset_error.42290063240841023589118000896884435085681217170340970702997070115145967149752","seed":42290063240841023589118000896884435085681217170340970702997070115145967149752,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2649957048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2649957048' seed=42290063240841023589118000896884435085681217170340970702997070115145967149752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42290063240841023589118000896884435085681217170340970702997070115145967149752 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/22.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"23.xbar_access_same_device_slow_rsp.59127121551567398519806100195300575326124190774863641179668679319278978739935","seed":59127121551567398519806100195300575326124190774863641179668679319278978739935,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=610938591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.610938591' seed=59127121551567398519806100195300575326124190774863641179668679319278978739935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59127121551567398519806100195300575326124190774863641179668679319278978739935 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"23.xbar_stress_all_with_error.27734435516978021365347309327235613785167406420737059704066014045227698231992","seed":27734435516978021365347309327235613785167406420737059704066014045227698231992,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3397786296 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3397786296' seed=27734435516978021365347309327235613785167406420737059704066014045227698231992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27734435516978021365347309327235613785167406420737059704066014045227698231992 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"23.xbar_stress_all_with_reset_error.66670002548565293576441107703014503296899115338880924167657253506340386156758","seed":66670002548565293576441107703014503296899115338880924167657253506340386156758,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1426763990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.1426763990' seed=66670002548565293576441107703014503296899115338880924167657253506340386156758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66670002548565293576441107703014503296899115338880924167657253506340386156758 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/23.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"24.xbar_access_same_device_slow_rsp.72553236002375256666786442375970371444846130398879850672348624826890639146333","seed":72553236002375256666786442375970371444846130398879850672348624826890639146333,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3097001309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3097001309' seed=72553236002375256666786442375970371444846130398879850672348624826890639146333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72553236002375256666786442375970371444846130398879850672348624826890639146333 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"24.xbar_stress_all_with_error.108139816852033673514717936030106376099836167053089835496207725290718499535608","seed":108139816852033673514717936030106376099836167053089835496207725290718499535608,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2380888824 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2380888824' seed=108139816852033673514717936030106376099836167053089835496207725290718499535608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108139816852033673514717936030106376099836167053089835496207725290718499535608 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"24.xbar_stress_all_with_reset_error.74349750532756743162020364386099582469412580459382222533187896195070730476208","seed":74349750532756743162020364386099582469412580459382222533187896195070730476208,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2139396784 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2139396784' seed=74349750532756743162020364386099582469412580459382222533187896195070730476208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74349750532756743162020364386099582469412580459382222533187896195070730476208 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/24.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"25.xbar_access_same_device_slow_rsp.51136972354283582874899571204134282673806899701577893046732730160683552711123","seed":51136972354283582874899571204134282673806899701577893046732730160683552711123,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1405985235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1405985235' seed=51136972354283582874899571204134282673806899701577893046732730160683552711123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51136972354283582874899571204134282673806899701577893046732730160683552711123 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"25.xbar_stress_all_with_error.21703841646097477847966384778293942987866088109443451064854631176097896514330","seed":21703841646097477847966384778293942987866088109443451064854631176097896514330,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2356069146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2356069146' seed=21703841646097477847966384778293942987866088109443451064854631176097896514330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21703841646097477847966384778293942987866088109443451064854631176097896514330 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"25.xbar_stress_all_with_reset_error.88649266070111514412861416439907813014490340895569927526217152316216250757578","seed":88649266070111514412861416439907813014490340895569927526217152316216250757578,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1655468490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1655468490' seed=88649266070111514412861416439907813014490340895569927526217152316216250757578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88649266070111514412861416439907813014490340895569927526217152316216250757578 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/25.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"26.xbar_access_same_device_slow_rsp.7650415850100752453650538964862345823458803880605756253910371551538858882266","seed":7650415850100752453650538964862345823458803880605756253910371551538858882266,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3070686426 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.3070686426' seed=7650415850100752453650538964862345823458803880605756253910371551538858882266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7650415850100752453650538964862345823458803880605756253910371551538858882266 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"26.xbar_stress_all_with_error.34997054758550001746296240693591914773410131281223670494716714218386983356785","seed":34997054758550001746296240693591914773410131281223670494716714218386983356785,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=983697777 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.983697777' seed=34997054758550001746296240693591914773410131281223670494716714218386983356785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34997054758550001746296240693591914773410131281223670494716714218386983356785 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"26.xbar_stress_all_with_reset_error.95754858790350941415039312273826450534027945832055732335388074795730305738361","seed":95754858790350941415039312273826450534027945832055732335388074795730305738361,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1116137081 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.1116137081' seed=95754858790350941415039312273826450534027945832055732335388074795730305738361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95754858790350941415039312273826450534027945832055732335388074795730305738361 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/26.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"27.xbar_access_same_device_slow_rsp.67362390089497843212303881799417801605392578409444663464141734804761528905852","seed":67362390089497843212303881799417801605392578409444663464141734804761528905852,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779473532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.3779473532' seed=67362390089497843212303881799417801605392578409444663464141734804761528905852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67362390089497843212303881799417801605392578409444663464141734804761528905852 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"27.xbar_stress_all_with_error.56164176526111470041859902878862524066119335582777018382548617910801466042278","seed":56164176526111470041859902878862524066119335582777018382548617910801466042278,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=521316262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.521316262' seed=56164176526111470041859902878862524066119335582777018382548617910801466042278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56164176526111470041859902878862524066119335582777018382548617910801466042278 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"27.xbar_stress_all_with_reset_error.89008748425349640696195918524475471336042009737261145738347806412604895512291","seed":89008748425349640696195918524475471336042009737261145738347806412604895512291,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2147337955 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2147337955' seed=89008748425349640696195918524475471336042009737261145738347806412604895512291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89008748425349640696195918524475471336042009737261145738347806412604895512291 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/27.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"28.xbar_access_same_device_slow_rsp.112176688744535540374669709969141177652318875321255929934146316078177574627586","seed":112176688744535540374669709969141177652318875321255929934146316078177574627586,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3546196226 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.3546196226' seed=112176688744535540374669709969141177652318875321255929934146316078177574627586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112176688744535540374669709969141177652318875321255929934146316078177574627586 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"28.xbar_stress_all_with_error.11614275782307929900152386264546846371577582097939292894459641068863606288479","seed":11614275782307929900152386264546846371577582097939292894459641068863606288479,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463952991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2463952991' seed=11614275782307929900152386264546846371577582097939292894459641068863606288479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11614275782307929900152386264546846371577582097939292894459641068863606288479 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"28.xbar_stress_all_with_reset_error.92672621200569815461274085078077850266452258619241118137662365499583668551724","seed":92672621200569815461274085078077850266452258619241118137662365499583668551724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958426156 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.2958426156' seed=92672621200569815461274085078077850266452258619241118137662365499583668551724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92672621200569815461274085078077850266452258619241118137662365499583668551724 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/28.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"29.xbar_access_same_device_slow_rsp.81948805910224823150583144651531507081525287801660455676630599971493872542392","seed":81948805910224823150583144651531507081525287801660455676630599971493872542392,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832526520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1832526520' seed=81948805910224823150583144651531507081525287801660455676630599971493872542392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81948805910224823150583144651531507081525287801660455676630599971493872542392 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"29.xbar_stress_all_with_error.87221744665990015199989386628468350014259625962236961453027498093550726939272","seed":87221744665990015199989386628468350014259625962236961453027498093550726939272,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1571422856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1571422856' seed=87221744665990015199989386628468350014259625962236961453027498093550726939272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87221744665990015199989386628468350014259625962236961453027498093550726939272 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"29.xbar_stress_all_with_reset_error.23016090460455177319219517879333434127803317905913793087656428071854057308297","seed":23016090460455177319219517879333434127803317905913793087656428071854057308297,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225638025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.1225638025' seed=23016090460455177319219517879333434127803317905913793087656428071854057308297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23016090460455177319219517879333434127803317905913793087656428071854057308297 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/29.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"30.xbar_access_same_device_slow_rsp.92015881690411065005396070579289756099689390605596846649002626229041067793114","seed":92015881690411065005396070579289756099689390605596846649002626229041067793114,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578338010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3578338010' seed=92015881690411065005396070579289756099689390605596846649002626229041067793114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92015881690411065005396070579289756099689390605596846649002626229041067793114 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"30.xbar_stress_all_with_error.7861377309524409075574787657185406930695301604570820864431804802717987537569","seed":7861377309524409075574787657185406930695301604570820864431804802717987537569,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1229357729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1229357729' seed=7861377309524409075574787657185406930695301604570820864431804802717987537569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7861377309524409075574787657185406930695301604570820864431804802717987537569 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"30.xbar_stress_all_with_reset_error.37313611314246563720943413431528535741365771847063436416453982648455968422902","seed":37313611314246563720943413431528535741365771847063436416453982648455968422902,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2164882422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2164882422' seed=37313611314246563720943413431528535741365771847063436416453982648455968422902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37313611314246563720943413431528535741365771847063436416453982648455968422902 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/30.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"31.xbar_access_same_device_slow_rsp.55892864622911563826367799290200573533438728418302877634604033812458007534724","seed":55892864622911563826367799290200573533438728418302877634604033812458007534724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1639292036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1639292036' seed=55892864622911563826367799290200573533438728418302877634604033812458007534724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55892864622911563826367799290200573533438728418302877634604033812458007534724 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"31.xbar_stress_all_with_error.94872302967323071887609309365092280051485498856517110470148614546230195855716","seed":94872302967323071887609309365092280051485498856517110470148614546230195855716,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2322669924 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2322669924' seed=94872302967323071887609309365092280051485498856517110470148614546230195855716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94872302967323071887609309365092280051485498856517110470148614546230195855716 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"31.xbar_stress_all_with_reset_error.30739170380824020770554728691125497534599096273969143122637768018460175610900","seed":30739170380824020770554728691125497534599096273969143122637768018460175610900,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1590277140 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.1590277140' seed=30739170380824020770554728691125497534599096273969143122637768018460175610900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30739170380824020770554728691125497534599096273969143122637768018460175610900 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/31.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"32.xbar_access_same_device_slow_rsp.7187272146597463042504994608994261878163442323850907443258473503378048127834","seed":7187272146597463042504994608994261878163442323850907443258473503378048127834,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039400794 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3039400794' seed=7187272146597463042504994608994261878163442323850907443258473503378048127834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7187272146597463042504994608994261878163442323850907443258473503378048127834 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"32.xbar_stress_all_with_error.107385482404507028272593702380341220527895120460512584788699057467446344503996","seed":107385482404507028272593702380341220527895120460512584788699057467446344503996,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=537875132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.537875132' seed=107385482404507028272593702380341220527895120460512584788699057467446344503996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107385482404507028272593702380341220527895120460512584788699057467446344503996 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"32.xbar_stress_all_with_reset_error.21055653971429655530068479740047382858015994201897242139128103634137345718130","seed":21055653971429655530068479740047382858015994201897242139128103634137345718130,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3556276082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3556276082' seed=21055653971429655530068479740047382858015994201897242139128103634137345718130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21055653971429655530068479740047382858015994201897242139128103634137345718130 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/32.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"33.xbar_access_same_device_slow_rsp.43886131907031934168527455223277032470429340360556009445978654854106529915524","seed":43886131907031934168527455223277032470429340360556009445978654854106529915524,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=546562692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.546562692' seed=43886131907031934168527455223277032470429340360556009445978654854106529915524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43886131907031934168527455223277032470429340360556009445978654854106529915524 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"33.xbar_stress_all_with_error.73121421390733952888689118677143697052454389833330065461989693542268030116458","seed":73121421390733952888689118677143697052454389833330065461989693542268030116458,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864065642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1864065642' seed=73121421390733952888689118677143697052454389833330065461989693542268030116458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73121421390733952888689118677143697052454389833330065461989693542268030116458 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"33.xbar_stress_all_with_reset_error.38921674860466867665431747424473758776994283222214610130222656755304169199406","seed":38921674860466867665431747424473758776994283222214610130222656755304169199406,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2035537710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2035537710' seed=38921674860466867665431747424473758776994283222214610130222656755304169199406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38921674860466867665431747424473758776994283222214610130222656755304169199406 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/33.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"34.xbar_access_same_device_slow_rsp.94219214536466519629283778285438891033722783907104412959992258385040757871117","seed":94219214536466519629283778285438891033722783907104412959992258385040757871117,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310759949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.310759949' seed=94219214536466519629283778285438891033722783907104412959992258385040757871117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94219214536466519629283778285438891033722783907104412959992258385040757871117 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"34.xbar_stress_all_with_error.92010322214708871271549662031280030113025424178348987271782624181671541610926","seed":92010322214708871271549662031280030113025424178348987271782624181671541610926,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4049869230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4049869230' seed=92010322214708871271549662031280030113025424178348987271782624181671541610926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92010322214708871271549662031280030113025424178348987271782624181671541610926 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"34.xbar_stress_all_with_reset_error.75867098733222215532899547116879460442994763586461483168875067538034074410238","seed":75867098733222215532899547116879460442994763586461483168875067538034074410238,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=950099198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.950099198' seed=75867098733222215532899547116879460442994763586461483168875067538034074410238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75867098733222215532899547116879460442994763586461483168875067538034074410238 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/34.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"35.xbar_access_same_device_slow_rsp.47937807805891119516980001380324641279741406122908671184706474861186217813548","seed":47937807805891119516980001380324641279741406122908671184706474861186217813548,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2783585836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2783585836' seed=47937807805891119516980001380324641279741406122908671184706474861186217813548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47937807805891119516980001380324641279741406122908671184706474861186217813548 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"35.xbar_stress_all_with_error.41257586315410228100815414702904105353409010126846526113913809095273589491656","seed":41257586315410228100815414702904105353409010126846526113913809095273589491656,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2449721288 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2449721288' seed=41257586315410228100815414702904105353409010126846526113913809095273589491656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41257586315410228100815414702904105353409010126846526113913809095273589491656 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"35.xbar_stress_all_with_reset_error.54246152743914777866194086622019685583394532240171881130937790137788566554090","seed":54246152743914777866194086622019685583394532240171881130937790137788566554090,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2791523818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2791523818' seed=54246152743914777866194086622019685583394532240171881130937790137788566554090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54246152743914777866194086622019685583394532240171881130937790137788566554090 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/35.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"36.xbar_access_same_device_slow_rsp.58641554716058965974709115111335889721235685339077334817926902429036371007093","seed":58641554716058965974709115111335889721235685339077334817926902429036371007093,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064040565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.4064040565' seed=58641554716058965974709115111335889721235685339077334817926902429036371007093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58641554716058965974709115111335889721235685339077334817926902429036371007093 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"36.xbar_stress_all_with_error.43734765415784189410933125574833020405214985055707497440456890233696006853566","seed":43734765415784189410933125574833020405214985055707497440456890233696006853566,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1202869182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1202869182' seed=43734765415784189410933125574833020405214985055707497440456890233696006853566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43734765415784189410933125574833020405214985055707497440456890233696006853566 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"36.xbar_stress_all_with_reset_error.83704757320059509047133318060445797339184554262249604378875168382918919880148","seed":83704757320059509047133318060445797339184554262249604378875168382918919880148,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132625364 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1132625364' seed=83704757320059509047133318060445797339184554262249604378875168382918919880148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83704757320059509047133318060445797339184554262249604378875168382918919880148 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/36.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"37.xbar_access_same_device_slow_rsp.85811666701282137931905659001747362910017053873728500922889018565005036622228","seed":85811666701282137931905659001747362910017053873728500922889018565005036622228,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2633634196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.2633634196' seed=85811666701282137931905659001747362910017053873728500922889018565005036622228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85811666701282137931905659001747362910017053873728500922889018565005036622228 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"37.xbar_stress_all_with_error.114305657964299691401442271473014012830443714523414263915481962483484366525177","seed":114305657964299691401442271473014012830443714523414263915481962483484366525177,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3147617017 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3147617017' seed=114305657964299691401442271473014012830443714523414263915481962483484366525177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114305657964299691401442271473014012830443714523414263915481962483484366525177 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"37.xbar_stress_all_with_reset_error.24599189989390330586612809705053530260600384544934960624216802936496508420956","seed":24599189989390330586612809705053530260600384544934960624216802936496508420956,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576321884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1576321884' seed=24599189989390330586612809705053530260600384544934960624216802936496508420956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24599189989390330586612809705053530260600384544934960624216802936496508420956 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/37.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"38.xbar_access_same_device_slow_rsp.55066588465696487635730959412971664093267888867876093618034008788611714380451","seed":55066588465696487635730959412971664093267888867876093618034008788611714380451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856003747 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3856003747' seed=55066588465696487635730959412971664093267888867876093618034008788611714380451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55066588465696487635730959412971664093267888867876093618034008788611714380451 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"38.xbar_stress_all_with_error.96960565500522244119137513177381439027654481329557902521790539743501524756703","seed":96960565500522244119137513177381439027654481329557902521790539743501524756703,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3463276767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3463276767' seed=96960565500522244119137513177381439027654481329557902521790539743501524756703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96960565500522244119137513177381439027654481329557902521790539743501524756703 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"38.xbar_stress_all_with_reset_error.18586536833860374895113648753961931581037888410905289521896962682778837342488","seed":18586536833860374895113648753961931581037888410905289521896962682778837342488,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1654413592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1654413592' seed=18586536833860374895113648753961931581037888410905289521896962682778837342488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18586536833860374895113648753961931581037888410905289521896962682778837342488 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/38.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"39.xbar_access_same_device_slow_rsp.94745239428369076517268354493666311297490389338215673985697518472261390949957","seed":94745239428369076517268354493666311297490389338215673985697518472261390949957,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1140710981 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1140710981' seed=94745239428369076517268354493666311297490389338215673985697518472261390949957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94745239428369076517268354493666311297490389338215673985697518472261390949957 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"39.xbar_stress_all_with_error.67877063851770178448554395712738198101270119812613005618916842370674434558740","seed":67877063851770178448554395712738198101270119812613005618916842370674434558740,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609616148 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1609616148' seed=67877063851770178448554395712738198101270119812613005618916842370674434558740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67877063851770178448554395712738198101270119812613005618916842370674434558740 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"39.xbar_stress_all_with_reset_error.94022519693629097703170673698672979090700489730748020230419245139530632931159","seed":94022519693629097703170673698672979090700489730748020230419245139530632931159,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754881367 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2754881367' seed=94022519693629097703170673698672979090700489730748020230419245139530632931159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94022519693629097703170673698672979090700489730748020230419245139530632931159 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/39.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"40.xbar_access_same_device_slow_rsp.77618174588172533619927020799038070349399183958761597702777229847368136678806","seed":77618174588172533619927020799038070349399183958761597702777229847368136678806,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3499908502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3499908502' seed=77618174588172533619927020799038070349399183958761597702777229847368136678806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77618174588172533619927020799038070349399183958761597702777229847368136678806 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"40.xbar_stress_all_with_error.36969201849413483843112909880618319764858244008411453709880500141313247483702","seed":36969201849413483843112909880618319764858244008411453709880500141313247483702,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=930944822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.930944822' seed=36969201849413483843112909880618319764858244008411453709880500141313247483702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36969201849413483843112909880618319764858244008411453709880500141313247483702 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"40.xbar_stress_all_with_reset_error.62209842723869080532934993381859650457359501112243326977684954684071421653486","seed":62209842723869080532934993381859650457359501112243326977684954684071421653486,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087329262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.4087329262' seed=62209842723869080532934993381859650457359501112243326977684954684071421653486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62209842723869080532934993381859650457359501112243326977684954684071421653486 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/40.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"41.xbar_access_same_device_slow_rsp.57516892210858417122397851672484711332605854456143543231893467048167376289726","seed":57516892210858417122397851672484711332605854456143543231893467048167376289726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319763902 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1319763902' seed=57516892210858417122397851672484711332605854456143543231893467048167376289726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57516892210858417122397851672484711332605854456143543231893467048167376289726 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"41.xbar_stress_all_with_error.83038506400786975257894787537754560122931474623474028578873447640978078234031","seed":83038506400786975257894787537754560122931474623474028578873447640978078234031,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1921447343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1921447343' seed=83038506400786975257894787537754560122931474623474028578873447640978078234031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83038506400786975257894787537754560122931474623474028578873447640978078234031 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"41.xbar_stress_all_with_reset_error.76945825657789351454158571511325233204773928077622934156620763275500127816500","seed":76945825657789351454158571511325233204773928077622934156620763275500127816500,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1620085556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1620085556' seed=76945825657789351454158571511325233204773928077622934156620763275500127816500 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76945825657789351454158571511325233204773928077622934156620763275500127816500 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/41.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"42.xbar_access_same_device_slow_rsp.10689789908116470412368588246101704231808122326225823986893639532297315983313","seed":10689789908116470412368588246101704231808122326225823986893639532297315983313,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3338444753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.3338444753' seed=10689789908116470412368588246101704231808122326225823986893639532297315983313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10689789908116470412368588246101704231808122326225823986893639532297315983313 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"42.xbar_stress_all_with_error.103632726540265386975190673926441584752304732789927277541835095834763234316887","seed":103632726540265386975190673926441584752304732789927277541835095834763234316887,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2617446999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2617446999' seed=103632726540265386975190673926441584752304732789927277541835095834763234316887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103632726540265386975190673926441584752304732789927277541835095834763234316887 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"42.xbar_stress_all_with_reset_error.18762507320384723103556642403068918284049733059891199043621072761242477925088","seed":18762507320384723103556642403068918284049733059891199043621072761242477925088,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3166966496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3166966496' seed=18762507320384723103556642403068918284049733059891199043621072761242477925088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18762507320384723103556642403068918284049733059891199043621072761242477925088 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/42.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"43.xbar_access_same_device_slow_rsp.56820197173480104489961242859320767506562747579623819974504766911616511959867","seed":56820197173480104489961242859320767506562747579623819974504766911616511959867,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1223746363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1223746363' seed=56820197173480104489961242859320767506562747579623819974504766911616511959867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56820197173480104489961242859320767506562747579623819974504766911616511959867 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"43.xbar_stress_all_with_error.45256589020945895797240224561066928965846516002507852868872258852246813760413","seed":45256589020945895797240224561066928965846516002507852868872258852246813760413,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=197483421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.197483421' seed=45256589020945895797240224561066928965846516002507852868872258852246813760413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45256589020945895797240224561066928965846516002507852868872258852246813760413 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"43.xbar_stress_all_with_reset_error.796057662341538879082468338098775747534234547265070167229495307339256748793","seed":796057662341538879082468338098775747534234547265070167229495307339256748793,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2145311481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2145311481' seed=796057662341538879082468338098775747534234547265070167229495307339256748793 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=796057662341538879082468338098775747534234547265070167229495307339256748793 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/43.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"44.xbar_access_same_device_slow_rsp.53552400005990102586491543290510200532247024324944067395493872309902991388572","seed":53552400005990102586491543290510200532247024324944067395493872309902991388572,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2907664284 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.2907664284' seed=53552400005990102586491543290510200532247024324944067395493872309902991388572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53552400005990102586491543290510200532247024324944067395493872309902991388572 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"44.xbar_stress_all_with_error.63176771702744085527530866964014219500280716194911003581580927969600368356327","seed":63176771702744085527530866964014219500280716194911003581580927969600368356327,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3540069351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3540069351' seed=63176771702744085527530866964014219500280716194911003581580927969600368356327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63176771702744085527530866964014219500280716194911003581580927969600368356327 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"44.xbar_stress_all_with_reset_error.4780684136914583794608609721202687922278550842861971712222701971990118165284","seed":4780684136914583794608609721202687922278550842861971712222701971990118165284,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=301755172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.301755172' seed=4780684136914583794608609721202687922278550842861971712222701971990118165284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4780684136914583794608609721202687922278550842861971712222701971990118165284 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/44.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"45.xbar_access_same_device_slow_rsp.81173277048072858460996198521234936537701845083476333234760526533860831007549","seed":81173277048072858460996198521234936537701845083476333234760526533860831007549,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039564605 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3039564605' seed=81173277048072858460996198521234936537701845083476333234760526533860831007549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81173277048072858460996198521234936537701845083476333234760526533860831007549 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"45.xbar_stress_all_with_error.111569799576991260182278652070461672527796501715392809593125162508824757450447","seed":111569799576991260182278652070461672527796501715392809593125162508824757450447,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2046605007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2046605007' seed=111569799576991260182278652070461672527796501715392809593125162508824757450447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111569799576991260182278652070461672527796501715392809593125162508824757450447 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"45.xbar_stress_all_with_reset_error.56480673777103699553717135836454109976616378700593509135244685201035250318856","seed":56480673777103699553717135836454109976616378700593509135244685201035250318856,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2290302472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2290302472' seed=56480673777103699553717135836454109976616378700593509135244685201035250318856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56480673777103699553717135836454109976616378700593509135244685201035250318856 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/45.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"46.xbar_access_same_device_slow_rsp.13211664683521462129099426682246124148058117473660764055544908129588730380116","seed":13211664683521462129099426682246124148058117473660764055544908129588730380116,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=254525268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.254525268' seed=13211664683521462129099426682246124148058117473660764055544908129588730380116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13211664683521462129099426682246124148058117473660764055544908129588730380116 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"46.xbar_stress_all_with_error.15118238737433557919631648284166180208063472171402762903805388823814813745052","seed":15118238737433557919631648284166180208063472171402762903805388823814813745052,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=229276 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.229276' seed=15118238737433557919631648284166180208063472171402762903805388823814813745052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15118238737433557919631648284166180208063472171402762903805388823814813745052 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"46.xbar_stress_all_with_reset_error.11774187811745966788297800772768179490291643645121880895158703665902016480801","seed":11774187811745966788297800772768179490291643645121880895158703665902016480801,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679929889 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3679929889' seed=11774187811745966788297800772768179490291643645121880895158703665902016480801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11774187811745966788297800772768179490291643645121880895158703665902016480801 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/46.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"47.xbar_access_same_device_slow_rsp.37173581894276363368694438217496802827764105459359397054207941733882379277884","seed":37173581894276363368694438217496802827764105459359397054207941733882379277884,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281450044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.281450044' seed=37173581894276363368694438217496802827764105459359397054207941733882379277884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37173581894276363368694438217496802827764105459359397054207941733882379277884 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"47.xbar_stress_all_with_error.8250230349751426682511891637267197532182210109442700831912724723315001203629","seed":8250230349751426682511891637267197532182210109442700831912724723315001203629,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4038532013 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4038532013' seed=8250230349751426682511891637267197532182210109442700831912724723315001203629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8250230349751426682511891637267197532182210109442700831912724723315001203629 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"47.xbar_stress_all_with_reset_error.80787409407227204290098779116728693580467210344808449016635180740413157215472","seed":80787409407227204290098779116728693580467210344808449016635180740413157215472,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2060913904 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.2060913904' seed=80787409407227204290098779116728693580467210344808449016635180740413157215472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80787409407227204290098779116728693580467210344808449016635180740413157215472 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/47.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"48.xbar_access_same_device_slow_rsp.59222209087674475010150357648709298491207173108468885251447980698400869998600","seed":59222209087674475010150357648709298491207173108468885251447980698400869998600,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723673096 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.723673096' seed=59222209087674475010150357648709298491207173108468885251447980698400869998600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59222209087674475010150357648709298491207173108468885251447980698400869998600 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"48.xbar_stress_all_with_error.93041971600549006179382178595116670685820100706433474383116003543635551903683","seed":93041971600549006179382178595116670685820100706433474383116003543635551903683,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3740852163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3740852163' seed=93041971600549006179382178595116670685820100706433474383116003543635551903683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93041971600549006179382178595116670685820100706433474383116003543635551903683 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"48.xbar_stress_all_with_reset_error.89340557345715810022455517888388613359650819236637703950883846739681298924122","seed":89340557345715810022455517888388613359650819236637703950883846739681298924122,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3954754138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3954754138' seed=89340557345715810022455517888388613359650819236637703950883846739681298924122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89340557345715810022455517888388613359650819236637703950883846739681298924122 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/48.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"49.xbar_access_same_device_slow_rsp.108228306064782972479174311081990905962218181516906518427979794214248768196940","seed":108228306064782972479174311081990905962218181516906518427979794214248768196940,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=195940684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.195940684' seed=108228306064782972479174311081990905962218181516906518427979794214248768196940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108228306064782972479174311081990905962218181516906518427979794214248768196940 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"49.xbar_stress_all_with_error.34353292014983665383675504744382892697019050362943801317165754986015162559900","seed":34353292014983665383675504744382892697019050362943801317165754986015162559900,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1153101212 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1153101212' seed=34353292014983665383675504744382892697019050362943801317165754986015162559900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34353292014983665383675504744382892697019050362943801317165754986015162559900 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"49.xbar_stress_all_with_reset_error.90519541373330699452146192875134601390998667697886344596594990636892240857466","seed":90519541373330699452146192875134601390998667697886344596594990636892240857466,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045888890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_dbg-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2045888890' seed=90519541373330699452146192875134601390998667697886344596594990636892240857466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90519541373330699452146192875134601390998667697886344596594990636892240857466 --run-dir=/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/49.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"xbar_dbg","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"xbar_dbg","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_dbg-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":450,"percent":0.0}